target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi

   1 /*
   2  * Copyright (c) 2016 MediaTek Inc.
   3  * Author: John Crispin <blogic@openwrt.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/clock/mt2701-clk.h>
  18 #include <dt-bindings/power/mt2701-power.h>
  19 #include <dt-bindings/phy/phy.h>
  20 #include <dt-bindings/reset/mt2701-resets.h>
  21 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  22 #include <dt-bindings/gpio/gpio.h>
  23 #include "skeleton64.dtsi"
  24
  25
  26 / {
  27         compatible = "mediatek,mt7623";
  28         interrupt-parent = <&sysirq>;
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33                 enable-method = "mediatek,mt6589-smp";
  34
  35                 cpu0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a7";
  38                         reg = <0x0>;
  39                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  40                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  41                         clock-names = "cpu", "intermediate";
  42                         operating-points = <
  43                                 598000 1150000
  44                                 747500 1150000
  45                                 1040000 1150000
  46                                 1196000 1200000
  47                                 1300000 1300000
  48                         >;
  49                 };
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0x1>;
  54                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  55                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  56                         clock-names = "cpu", "intermediate";
  57                         operating-points = <
  58                                 598000 1150000
  59                                 747500 1150000
  60                                 1040000 1150000
  61                                 1196000 1200000
  62                                 1300000 1300000
  63                         >;
  64                 };
  65                 cpu2: cpu@2 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a7";
  68                         reg = <0x2>;
  69                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  70                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  71                         clock-names = "cpu", "intermediate";
  72                         operating-points = <
  73                                 598000 1150000
  74                                 747500 1150000
  75                                 1040000 1150000
  76                                 1196000 1200000
  77                                 1300000 1300000
  78                         >;
  79                 };
  80                 cpu3: cpu@3 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a7";
  83                         reg = <0x3>;
  84                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  85                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  86                         clock-names = "cpu", "intermediate";
  87                         operating-points = <
  88                                 598000 1150000
  89                                 747500 1150000
  90                                 1040000 1150000
  91                                 1196000 1200000
  92                                 1300000 1300000
  93                         >;
  94                 };
  95         };
  96
  97         system_clk: dummy13m {
  98                 compatible = "fixed-clock";
  99                 clock-frequency = <13000000>;
 100                 #clock-cells = <0>;
 101         };
 102
 103         rtc_clk: dummy32k {
 104                 compatible = "fixed-clock";
 105                 clock-frequency = <32000>;
 106                 #clock-cells = <0>;
 107                 clock-output-names = "clk32k";
 108         };
 109
 110         clk26m: dummy26m {
 111                 compatible = "fixed-clock";
 112                 clock-frequency = <26000000>;
 113                 #clock-cells = <0>;
 114                 clock-output-names = "clk26m";
 115         };
 116
 117         timer {
 118                 compatible = "arm,armv7-timer";
 119                 interrupt-parent = <&gic>;
 120                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 121                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 122                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 123                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 124                 clock-frequency = <13000000>;
 125                 arm,cpu-registers-not-fw-configured;
 126         };
 127
 128         topckgen: power-controller@10000000 {
 129                 compatible = "mediatek,mt7623-topckgen",
 130                              "mediatek,mt2701-topckgen",
 131                              "syscon";
 132                 reg = <0 0x10000000 0 0x1000>;
 133                 #clock-cells = <1>;
 134         };
 135
 136         infracfg: power-controller@10001000 {
 137                 compatible = "mediatek,mt7623-infracfg",
 138                              "mediatek,mt2701-infracfg",
 139                              "syscon";
 140                 reg = <0 0x10001000 0 0x1000>;
 141                 #clock-cells = <1>;
 142                 #reset-cells = <1>;
 143         };
 144
 145         pericfg: pericfg@10003000 {
 146                 compatible = "mediatek,mt7623-pericfg",
 147                              "mediatek,mt2701-pericfg",
 148                              "syscon";
 149                 reg = <0 0x10003000 0 0x1000>;
 150                 #clock-cells = <1>;
 151                 #reset-cells = <1>;
 152         };
 153
 154         pio: pinctrl@10005000 {
 155                 compatible = "mediatek,mt7623-pinctrl";
 156                 reg = <0 0x1000b000 0 0x1000>;
 157                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 158                 pins-are-numbered;
 159                 gpio-controller;
 160                 #gpio-cells = <2>;
 161                 interrupt-controller;
 162                 interrupt-parent = <&gic>;
 163                 #interrupt-cells = <2>;
 164                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 166         };
 167
 168         syscfg_pctl_a: syscfg@10005000 {
 169                 compatible = "mediatek,mt7623-pctl-a-syscfg",
 170                              "mediatek,mt2701-pctl-a-syscfg",
 171                              "syscon";
 172                 reg = <0 0x10005000 0 0x1000>;
 173         };
 174
 175         scpsys: scpsys@10006000 {
 176                 #power-domain-cells = <1>;
 177                 compatible = "mediatek,mt7623-scpsys",
 178                              "mediatek,mt2701-scpsys";
 179                 reg = <0 0x10006000 0 0x1000>;
 180                 infracfg = <&infracfg>;
 181                 clocks = <&clk26m>,
 182                          <&topckgen CLK_TOP_MM_SEL>,
 183                          <&topckgen CLK_TOP_ETHIF_SEL>;
 184                 clock-names = "mfg", "mm", "ethif";
 185         };
 186
 187         watchdog: watchdog@10007000 {
 188                 compatible = "mediatek,mt7623-wdt",
 189                              "mediatek,mt6589-wdt";
 190                 reg = <0 0x10007000 0 0x100>;
 191         };
 192
 193         timer: timer@10008000 {
 194                 compatible = "mediatek,mt7623-timer",
 195                              "mediatek,mt6577-timer";
 196                 reg = <0 0x10008000 0 0x80>;
 197                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 198                 clocks = <&system_clk>, <&rtc_clk>;
 199                 clock-names = "system-clk", "rtc-clk";
 200         };
 201
 202         pwrap: pwrap@1000d000 {
 203                 compatible = "mediatek,mt7623-pwrap",
 204                              "mediatek,mt2701-pwrap";
 205                 reg = <0 0x1000d000 0 0x1000>;
 206                 reg-names = "pwrap";
 207                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 208                 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 209                 reset-names = "pwrap";
 210                 clocks = <&infracfg CLK_INFRA_PMICSPI>,
 211                          <&infracfg CLK_INFRA_PMICWRAP>;
 212                 clock-names = "spi", "wrap";
 213         };
 214
 215         cir: cir@10013000 {
 216                 compatible = "mediatek,mt7623-cir";
 217                 reg = <0 0x10013000 0 0x1000>;
 218                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 219                 clocks = <&infracfg CLK_INFRA_IRRX>;
 220                 clock-names = "clk";
 221                 status = "disabled";
 222         };
 223
 224         sysirq: interrupt-controller@10200100 {
 225                 compatible = "mediatek,mt7623-sysirq",
 226                              "mediatek,mt6577-sysirq";
 227                 interrupt-controller;
 228                 #interrupt-cells = <3>;
 229                 interrupt-parent = <&gic>;
 230                 reg = <0 0x10200100 0 0x1c>;
 231         };
 232
 233         efuse: efuse@10206000 {
 234                 compatible = "mediatek,mt7623-efuse",
 235                              "mediatek,efuse";
 236                 reg        = <0 0x10206000 0 0x1000>;
 237                 #address-cells = <1>;
 238                 #size-cells = <1>;
 239
 240                 /* Data cells */
 241                 thermal_calibration: calib@424 {
 242                         reg = <0x424 0xc>;
 243                 };
 244         };
 245
 246         apmixedsys: apmixedsys@10209000 {
 247                 compatible = "mediatek,mt7623-apmixedsys",
 248                              "mediatek,mt2701-apmixedsys";
 249                 reg = <0 0x10209000 0 0x1000>;
 250                 #clock-cells = <1>;
 251         };
 252
 253         rng: rng@1020f000 {
 254                 compatible = "mediatek,mt7623-rng";
 255                 reg = <0 0x1020f000 0 0x1000>;
 256                 clocks = <&infracfg CLK_INFRA_TRNG>;
 257                 clock-names = "rng";
 258         };
 259
 260         gic: interrupt-controller@10211000 {
 261                 compatible = "arm,cortex-a7-gic";
 262                 interrupt-controller;
 263                 #interrupt-cells = <3>;
 264                 interrupt-parent = <&gic>;
 265                 reg = <0 0x10211000 0 0x1000>,
 266                       <0 0x10212000 0 0x1000>,
 267                       <0 0x10214000 0 0x2000>,
 268                       <0 0x10216000 0 0x2000>;
 269         };
 270
 271         auxadc: adc@11001000 {
 272                 compatible = "mediatek,mt7623-auxadc",
 273                              "mediatek,mt2701-auxadc";
 274                 reg = <0 0x11001000 0 0x1000>;
 275                 clocks = <&pericfg CLK_PERI_AUXADC>;
 276                 clock-names = "main";
 277                 #io-channel-cells = <1>;
 278         };
 279
 280         uart0: serial@11002000 {
 281                 compatible = "mediatek,mt7623-uart",
 282                              "mediatek,mt6577-uart";
 283                 reg = <0 0x11002000 0 0x400>;
 284                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 285                 clocks = <&pericfg CLK_PERI_UART0_SEL>,
 286                          <&pericfg CLK_PERI_UART0>;
 287                 clock-names = "baud", "bus";
 288                 status = "disabled";
 289         };
 290
 291         uart1: serial@11003000 {
 292                 compatible = "mediatek,mt7623-uart",
 293                              "mediatek,mt6577-uart";
 294                 reg = <0 0x11003000 0 0x400>;
 295                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 296                 clocks = <&pericfg CLK_PERI_UART1_SEL>,
 297                          <&pericfg CLK_PERI_UART1>;
 298                 clock-names = "baud", "bus";
 299                 status = "disabled";
 300         };
 301
 302         uart2: serial@11004000 {
 303                 compatible = "mediatek,mt7623-uart",
 304                              "mediatek,mt6577-uart";
 305                 reg = <0 0x11004000 0 0x400>;
 306                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 307                 clocks = <&pericfg CLK_PERI_UART2_SEL>,
 308                          <&pericfg CLK_PERI_UART2>;
 309                 clock-names = "baud", "bus";
 310                 status = "disabled";
 311         };
 312
 313         uart3: serial@11005000 {
 314                 compatible = "mediatek,mt7623-uart",
 315                              "mediatek,mt6577-uart";
 316                 reg = <0 0x11005000 0 0x400>;
 317                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 318                 clocks = <&pericfg CLK_PERI_UART3_SEL>,
 319                          <&pericfg CLK_PERI_UART3>;
 320                 clock-names = "baud", "bus";
 321                 status = "disabled";
 322         };
 323
 324         pwm: pwm@11006000 {
 325                 compatible = "mediatek,mt7623-pwm";
 326
 327                 reg = <0 0x11006000 0 0x1000>;
 328                 resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
 329                 reset-names = "pwm";
 330
 331                 #pwm-cells = <2>;
 332                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 333                          <&pericfg CLK_PERI_PWM>,
 334                          <&pericfg CLK_PERI_PWM1>,
 335                          <&pericfg CLK_PERI_PWM2>,
 336                          <&pericfg CLK_PERI_PWM3>,
 337                          <&pericfg CLK_PERI_PWM4>,
 338                          <&pericfg CLK_PERI_PWM5>;
 339                 clock-names = "top", "main", "pwm1", "pwm2",
 340                               "pwm3", "pwm4", "pwm5";
 341
 342                 status = "disabled";
 343         };
 344
 345         i2c0: i2c@11007000 {
 346                 compatible = "mediatek,mt7623-i2c",
 347                              "mediatek,mt6577-i2c";
 348                 reg = <0 0x11007000 0 0x70>,
 349                       <0 0x11000200 0 0x80>;
 350                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 351                 clock-div = <16>;
 352                 clocks = <&pericfg CLK_PERI_I2C0>,
 353                          <&pericfg CLK_PERI_AP_DMA>;
 354                 clock-names = "main", "dma";
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 status = "disabled";
 358         };
 359
 360         i2c1: i2c@11008000 {
 361                 compatible = "mediatek,mt7623-i2c",
 362                              "mediatek,mt6577-i2c";
 363                 reg = <0 0x11008000 0 0x70>,
 364                       <0 0x11000280 0 0x80>;
 365                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 366                 clock-div = <16>;
 367                 clocks = <&pericfg CLK_PERI_I2C1>,
 368                          <&pericfg CLK_PERI_AP_DMA>;
 369                 clock-names = "main", "dma";
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 status = "disabled";
 373         };
 374
 375         i2c2: i2c@11009000 {
 376                 compatible = "mediatek,mt7623-i2c",
 377                              "mediatek,mt6577-i2c";
 378                 reg = <0 0x11009000 0 0x70>,
 379                       <0 0x11000300 0 0x80>;
 380                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 381                 clock-div = <16>;
 382                 clocks = <&pericfg CLK_PERI_I2C2>,
 383                          <&pericfg CLK_PERI_AP_DMA>;
 384                 clock-names = "main", "dma";
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 status = "disabled";
 388         };
 389
 390         spi0: spi@1100a000 {
 391                 compatible = "mediatek,mt7623-spi",
 392                              "mediatek,mt6589-spi";
 393                 reg = <0 0x1100a000 0 0x1000>;
 394                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 395                 clocks = <&pericfg CLK_PERI_SPI0>;
 396                 clock-names = "main";
 397
 398                 status = "disabled";
 399         };
 400
 401         thermal: thermal@1100b000 {
 402                 #thermal-sensor-cells = <1>;
 403                 compatible = "mediatek,mt2701-thermal",
 404                              "mediatek,mt2701-thermal";
 405                 reg = <0 0x1100b000 0 0x1000>;
 406                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 407                 clocks = <&pericfg CLK_PERI_THERM>,
 408                          <&pericfg CLK_PERI_AUXADC>;
 409                 clock-names = "therm", "auxadc";
 410                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 411                 reset-names = "therm";
 412                 mediatek,auxadc = <&auxadc>;
 413                 mediatek,apmixedsys = <&apmixedsys>;
 414
 415                 nvmem-cells = <&thermal_calibration>;
 416                 nvmem-cell-names = "calibration-data";
 417         };
 418
 419         spi1: spi@11016000 {
 420                 compatible = "mediatek,mt7623-spi",
 421                              "mediatek,mt2701-spi";
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 reg = <0 0x11016000 0 0x100>;
 425                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 426                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 427                          <&topckgen CLK_TOP_SPI1_SEL>,
 428                          <&pericfg CLK_PERI_SPI1>;
 429                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 430                 status = "disabled";
 431         };
 432
 433         spi2: spi@11017000 {
 434                 compatible = "mediatek,mt7623-spi",
 435                         "mediatek,mt2701-spi";
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 reg = <0 0x11017000 0 0x1000>;
 439                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 440                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 441                          <&topckgen CLK_TOP_SPI2_SEL>,
 442                          <&pericfg CLK_PERI_SPI2>;
 443                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 444                 status = "disabled";
 445         };
 446
 447         nandc: nfi@1100d000 {
 448                 compatible = "mediatek,mt7623-nfc",
 449                              "mediatek,mt2701-nfc";
 450                 reg = <0 0x1100d000 0 0x1000>;
 451                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 452                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 453                 clocks = <&pericfg CLK_PERI_NFI>,
 454                          <&pericfg CLK_PERI_NFI_PAD>;
 455                 clock-names = "nfi_clk", "pad_clk";
 456                 status = "disabled";
 457                 ecc-engine = <&bch>;
 458                 #address-cells = <1>;
 459                 #size-cells = <0>;
 460         };
 461
 462         bch: ecc@1100e000 {
 463                 compatible = "mediatek,mt7623-ecc",
 464                              "mediatek,mt2701-ecc";
 465                 reg = <0 0x1100e000 0 0x1000>;
 466                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 467                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 468                 clock-names = "nfiecc_clk";
 469                 status = "disabled";
 470         };
 471
 472         afe: audio-controller@11220000 {
 473         compatible = "mediatek,mt7623-audio",
 474                      "mediatek,mt2701-audio";
 475         reg = <0 0x11220000 0 0x2000>,
 476               <0 0x112a0000 0 0x20000>;
 477         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 478         power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 479
 480         clocks = <&infracfg CLK_INFRA_AUDIO>,
 481                  <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 482                  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 483                  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 484                  <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 485                  <&topckgen CLK_TOP_AUD_48K_TIMING>,
 486                  <&topckgen CLK_TOP_AUD_44K_TIMING>,
 487                  <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 488                  <&topckgen CLK_TOP_APLL_SEL>,
 489                  <&topckgen CLK_TOP_AUD1PLL_98M>,
 490                  <&topckgen CLK_TOP_AUD2PLL_90M>,
 491                  <&topckgen CLK_TOP_HADDS2PLL_98M>,
 492                  <&topckgen CLK_TOP_HADDS2PLL_294M>,
 493                  <&topckgen CLK_TOP_AUDPLL>,
 494                  <&topckgen CLK_TOP_AUDPLL_D4>,
 495                  <&topckgen CLK_TOP_AUDPLL_D8>,
 496                  <&topckgen CLK_TOP_AUDPLL_D16>,
 497                  <&topckgen CLK_TOP_AUDPLL_D24>,
 498                  <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 499                  <&clk26m>,
 500                  <&topckgen CLK_TOP_SYSPLL1_D4>,
 501                  <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 502                  <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 503                  <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 504                  <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 505                  <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 506                  <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 507                  <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 508                  <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 509                  <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 510                  <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 511                  <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 512                  <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 513                  <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 514                  <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 515                  <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 516                  <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 517                  <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 518                  <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 519                  <&topckgen CLK_TOP_ASM_M_SEL>,
 520                  <&topckgen CLK_TOP_ASM_H_SEL>,
 521                  <&topckgen CLK_TOP_UNIVPLL2_D4>,
 522                  <&topckgen CLK_TOP_UNIVPLL2_D2>,
 523                  <&topckgen CLK_TOP_SYSPLL_D5>;
 524         clock-names = "infra_sys_audio_clk",
 525                 "top_audio_mux1_sel",
 526                 "top_audio_mux2_sel",
 527                 "top_audio_mux1_div",
 528                 "top_audio_mux2_div",
 529                 "top_audio_48k_timing",
 530                 "top_audio_44k_timing",
 531                 "top_audpll_mux_sel",
 532                 "top_apll_sel",
 533                 "top_aud1_pll_98M",
 534                 "top_aud2_pll_90M",
 535                 "top_hadds2_pll_98M",
 536                 "top_hadds2_pll_294M",
 537                 "top_audpll",
 538                 "top_audpll_d4",
 539                 "top_audpll_d8",
 540                 "top_audpll_d16",
 541                 "top_audpll_d24",
 542                 "top_audintbus_sel",
 543                 "clk_26m",
 544                 "top_syspll1_d4",
 545                 "top_aud_k1_src_sel",
 546                 "top_aud_k2_src_sel",
 547                 "top_aud_k3_src_sel",
 548                 "top_aud_k4_src_sel",
 549                 "top_aud_k5_src_sel",
 550                 "top_aud_k6_src_sel",
 551                 "top_aud_k1_src_div",
 552                 "top_aud_k2_src_div",
 553                 "top_aud_k3_src_div",
 554                 "top_aud_k4_src_div",
 555                 "top_aud_k5_src_div",
 556                 "top_aud_k6_src_div",
 557                 "top_aud_i2s1_mclk",
 558                 "top_aud_i2s2_mclk",
 559                 "top_aud_i2s3_mclk",
 560                 "top_aud_i2s4_mclk",
 561                 "top_aud_i2s5_mclk",
 562                 "top_aud_i2s6_mclk",
 563                 "top_asm_m_sel",
 564                 "top_asm_h_sel",
 565                 "top_univpll2_d4",
 566                 "top_univpll2_d2",
 567                 "top_syspll_d5";
 568         };
 569
 570         mmc0: mmc@11230000 {
 571                 compatible = "mediatek,mt7623-mmc",
 572                              "mediatek,mt8135-mmc";
 573                 reg = <0 0x11230000 0 0x1000>;
 574                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 575                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 576                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 577                 clock-names = "source", "hclk";
 578                 status = "disabled";
 579         };
 580
 581         mmc1: mmc@11240000 {
 582                 compatible = "mediatek,mt7623-mmc",
 583                              "mediatek,mt8135-mmc";
 584                 reg = <0 0x11240000 0 0x1000>;
 585                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 586                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 587                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 588                 clock-names = "source", "hclk";
 589                 status = "disabled";
 590         };
 591
 592         usb1: usb@1a1c0000 {
 593                 compatible = "mediatek,mt7623-xhci",
 594                              "mediatek,mt8173-xhci";
 595                 reg = <0 0x1a1c0000 0 0x1000>,
 596                       <0 0x1a1c4700 0 0x0100>;
 597                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 598                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 599                          <&topckgen CLK_TOP_ETHIF_SEL>;
 600                 clock-names = "sys_ck", "ethif";
 601                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 602                 phys = <&phy_port0 PHY_TYPE_USB3>;
 603                 status = "disabled";
 604         };
 605
 606         u3phy1: usb-phy@1a1c4000 {
 607                 compatible = "mediatek,mt2701-u3phy",
 608                              "mediatek,mt8173-u3phy";
 609                 reg = <0 0x1a1c4000 0 0x0700>;
 610                 clocks = <&clk26m>;
 611                 clock-names = "u3phya_ref";
 612                 #phy-cells = <1>;
 613                 #address-cells = <2>;
 614                 #size-cells = <2>;
 615                 ranges;
 616                 status = "disabled";
 617
 618                 phy_port0: phy_port0: port@1a1c4800 {
 619                         reg = <0 0x1a1c4800 0 0x800>;
 620                         #phy-cells = <1>;
 621                         status = "okay";
 622                 };
 623         };
 624
 625         usb2: usb@1a240000 {
 626                 compatible = "mediatek,mt2701-xhci",
 627                              "mediatek,mt8173-xhci";
 628                 reg = <0 0x1a240000 0 0x1000>,
 629                       <0 0x1a244700 0 0x0100>;
 630                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 631                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 632                          <&topckgen CLK_TOP_ETHIF_SEL>;
 633                 clock-names = "sys_ck", "ethif";
 634                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 635                 phys = <&u3phy2 0>;
 636                 status = "disabled";
 637         };
 638
 639         u3phy2: usb-phy@1a244000 {
 640                 compatible = "mediatek,mt2701-u3phy",
 641                              "mediatek,mt8173-u3phy";
 642                 reg = <0 0x1a244000 0 0x0700>,
 643                       <0 0x1a244800 0 0x0800>;
 644                 clocks = <&clk26m>;
 645                 clock-names = "u3phya_ref";
 646                 #phy-cells = <1>;
 647                 status = "disabled";
 648         };
 649
 650         hifsys: clock-controller@1a000000 {
 651                 compatible = "mediatek,mt7623-hifsys",
 652                              "mediatek,mt2701-hifsys",
 653                              "syscon";
 654                 reg = <0 0x1a000000 0 0x1000>;
 655                 #clock-cells = <1>;
 656                 #reset-cells = <1>;
 657         };
 658
 659         pcie: pcie@1a140000 {
 660                 compatible = "mediatek,mt7623-pcie";
 661                 device_type = "pci";
 662                 reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
 663                       <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
 664                       <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
 665                       <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
 666                 reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
 667                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
 668                              <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
 669                              <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 670                 interrupt-names = "pcie0", "pcie1", "pcie2";
 671                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
 672                 clock-names = "pcie";
 673                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 674                 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
 675                          <&hifsys MT2701_HIFSYS_PCIE1_RST>,
 676                          <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 677                 reset-names = "pcie0", "pcie1", "pcie2";
 678
 679                 mediatek,hifsys = <&hifsys>;
 680
 681                 bus-range = <0x00 0xff>;
 682                 #address-cells = <3>;
 683                 #size-cells = <2>;
 684
 685                 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
 686                           0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
 687
 688                 status = "disabled";
 689
 690                 pcie@1,0 {
 691                         device_type = "pci";
 692                         reg = <0x0800 0 0 0 0>;
 693
 694                         #address-cells = <3>;
 695                         #size-cells = <2>;
 696                         ranges;
 697                 };
 698
 699                 pcie@2,0{
 700                         device_type = "pci";
 701                         reg = <0x1000 0 0 0 0>;
 702
 703                         #address-cells = <3>;
 704                         #size-cells = <2>;
 705                         ranges;
 706                 };
 707
 708                 pcie@3,0{
 709                         device_type = "pci";
 710                         reg = <0x1800 0 0 0 0>;
 711
 712                         #address-cells = <3>;
 713                         #size-cells = <2>;
 714                         ranges;
 715                 };
 716         };
 717
 718         ethsys: syscon@1b000000 {
 719                 compatible = "mediatek,mt7623-ethsys",
 720                              "mediatek,mt2701-ethsys",
 721                              "syscon";
 722                 reg = <0 0x1b000000 0 0x1000>;
 723                 #reset-cells = <1>;
 724                 #clock-cells = <1>;
 725         };
 726
 727         eth: ethernet@1b100000 {
 728                 compatible = "mediatek,mt7623-eth",
 729                              "mediatek,mt2701-eth",
 730                              "syscon";
 731                 reg = <0 0x1b100000 0 0x20000>;
 732
 733                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 734                          <&ethsys CLK_ETHSYS_ESW>,
 735                          <&ethsys CLK_ETHSYS_GP2>,
 736                          <&ethsys CLK_ETHSYS_GP1>,
 737                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 738                 clock-names = "ethif", "esw", "gp2", "gp1", "trgpll";
 739                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
 740                               GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
 741                               GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 742                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 743
 744                 resets = <&ethsys 6>;
 745                 reset-names = "eth";
 746
 747                 mediatek,ethsys = <&ethsys>;
 748                 mediatek,pctl = <&syscfg_pctl_a>;
 749
 750                 #address-cells = <1>;
 751                 #size-cells = <0>;
 752
 753                 status = "disabled";
 754
 755                 gmac1: mac@0 {
 756                         compatible = "mediatek,eth-mac";
 757                         reg = <0>;
 758
 759                         status = "disabled";
 760
 761                         phy-mode = "trgmii";
 762
 763                         fixed-link {
 764                                 speed = <1000>;
 765                                 full-duplex;
 766                                 pause;
 767                         };
 768                 };
 769
 770                 gmac2: mac@1 {
 771                         compatible = "mediatek,eth-mac";
 772                         reg = <1>;
 773
 774                         status = "disabled";
 775                 };
 776
 777                 mdio0: mdio-bus {
 778                         #address-cells = <1>;
 779                         #size-cells = <0>;
 780                 };
 781         };
 782
 783         hnat: hnat@1b000000 {
 784                 compatible = "mediatek,mt7623-hnat";
 785                 reg = <0 0x1b100000 0 0x3000>;
 786                 mtketh-wan = "eth1";
 787                 resets = <&ethsys 0>;
 788                 reset-names = "mtketh";
 789         };
 790
 791         crypto: crypto@1b240000 {
 792                 compatible = "mediatek,mt7623-crypto", "mediatek,eip97-crypto";
 793                 reg = <0 0x1b240000 0 0x20000>;
 794                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
 795                              <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
 796                              <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
 797                              <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
 798                              <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
 799                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 800                          <&ethsys CLK_ETHSYS_CRYPTO>;
 801                 clock-names = "ethif","cryp";
 802                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 803         };
 804 };