target/linux/mediatek/dts/mt7981b-openembed-som7981.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 /dts-v1/;
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7 #include <dt-bindings/leds/common.h>
   8 #include "mt7981.dtsi"
   9
  10 / {
  11         model = "OpenEmbed SOM7981";
  12         compatible = "openembed,som7981", "mediatek,mt7981";
  13
  14         aliases {
  15                 led-boot = &wlan2g_led;
  16                 led-failsafe = &wlan2g_led;
  17                 led-upgrade = &wlan2g_led;
  18                 serial0 = &uart0;
  19         };
  20
  21         chosen {
  22                 stdout-path = "serial0:115200n8";
  23         };
  24
  25         memory@40000000 {
  26                 reg = <0 0x40000000 0 0x40000000>;
  27         };
  28
  29         gpio-keys {
  30                 compatible = "gpio-keys";
  31
  32                 button-reset {
  33                         label = "reset";
  34                         linux,code = <KEY_RESTART>;
  35                         gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  36                 };
  37
  38                 button-wps {
  39                         label = "wps";
  40                         linux,code = <KEY_WPS_BUTTON>;
  41                         gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  42                 };
  43         };
  44
  45         gpio-leds {
  46                 compatible = "gpio-leds";
  47
  48                 led-0 {
  49                         function = LED_FUNCTION_LAN;
  50                         color = <LED_COLOR_ID_AMBER>;
  51                         gpios = <&pio 8 GPIO_ACTIVE_LOW>;
  52                 };
  53
  54                 led-1 {
  55                         function = LED_FUNCTION_LAN;
  56                         color = <LED_COLOR_ID_GREEN>;
  57                         gpios = <&pio 13 GPIO_ACTIVE_LOW>;
  58                 };
  59
  60                 wlan2g_led: led-2 {
  61                         function = LED_FUNCTION_WLAN_2GHZ;
  62                         color = <LED_COLOR_ID_RED>;
  63                         gpios = <&pio 34 GPIO_ACTIVE_LOW>;
  64                         linux,default-trigger = "phy0tpt";
  65                 };
  66
  67                 led-3 {
  68                         function = LED_FUNCTION_WLAN_5GHZ;
  69                         color = <LED_COLOR_ID_RED>;
  70                         gpios = <&pio 35 GPIO_ACTIVE_LOW>;
  71                         linux,default-trigger = "phy1tpt";
  72                 };
  73         };
  74 };
  75
  76 &eth {
  77         pinctrl-names = "default";
  78         pinctrl-0 = <&mdio_pins>;
  79         status = "okay";
  80
  81         gmac0: mac@0 {
  82                 compatible = "mediatek,eth-mac";
  83                 reg = <0>;
  84                 phy-mode = "2500base-x";
  85                 phy-handle = <&phy0>;
  86                 nvmem-cells = <&macaddr_factory_a 0>;
  87                 nvmem-cell-names = "mac-address";
  88         };
  89
  90         gmac1: mac@1 {
  91                 compatible = "mediatek,eth-mac";
  92                 reg = <1>;
  93                 phy-mode = "gmii";
  94                 phy-handle = <&int_gbe_phy>;
  95                 nvmem-cells = <&macaddr_factory_a 1>;
  96                 nvmem-cell-names = "mac-address";
  97         };
  98 };
  99
 100 &mdio_bus {
 101         phy0: ethernet-phy@5 {
 102                 reg = <5>;
 103                 compatible = "ethernet-phy-ieee802.3-c45";
 104                 phy-mode = "2500base-x";
 105                 reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
 106                 reset-assert-us = <10000>;
 107                 reset-deassert-us = <50000>;
 108                 realtek,aldps-enable;
 109         };
 110 };
 111
 112 &spi0 {
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&spi0_flash_pins>;
 115         status = "okay";
 116
 117         spi_nand: flash@0 {
 118                 compatible = "spi-nand";
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 reg = <0>;
 122
 123                 spi-max-frequency = <52000000>;
 124                 spi-tx-bus-width = <4>;
 125                 spi-rx-bus-width = <4>;
 126
 127                 partitions {
 128                         compatible = "fixed-partitions";
 129                         #address-cells = <1>;
 130                         #size-cells = <1>;
 131
 132                         partition@0 {
 133                                 label = "bl2";
 134                                 reg = <0x000000 0x100000>;
 135                                 read-only;
 136                         };
 137
 138                         partition@100000 {
 139                                 label = "u-boot-env";
 140                                 reg = <0x100000 0x80000>;
 141                         };
 142
 143                         partition@180000 {
 144                                 compatible = "nvmem-cells";
 145                                 label = "factory";
 146                                 reg = <0x180000 0x100000>;
 147                                 read-only;
 148
 149                                 nvmem-layout {
 150                                         compatible = "fixed-layout";
 151                                         #address-cells = <1>;
 152                                         #size-cells = <1>;
 153
 154                                         eeprom_factory_0: eeprom@0 {
 155                                                 reg = <0x0 0x1000>;
 156                                         };
 157
 158                                         macaddr_factory_a: macaddr@a {
 159                                                 compatible = "mac-base";
 160                                                 reg = <0xa 0x6>;
 161                                                 #nvmem-cell-cells = <1>;
 162                                         };
 163                                 };
 164                         };
 165
 166                         partition@280000 {
 167                                 label = "config";
 168                                 reg = <0x280000 0x100000>;
 169                                 read-only;
 170                         };
 171
 172                         partition@380000 {
 173                                 label = "fip";
 174                                 reg = <0x380000 0x200000>;
 175                                 read-only;
 176                         };
 177
 178                         partition@580000 {
 179                                 label = "ubi";
 180                                 reg = <0x580000 0xf880000>;
 181                         };
 182                 };
 183         };
 184 };
 185
 186 &pio {
 187         spi0_flash_pins: spi0-pins {
 188                 mux {
 189                         function = "spi";
 190                         groups = "spi0", "spi0_wp_hold";
 191                 };
 192
 193                 conf-pu {
 194                         pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
 195                         drive-strength = <8>;
 196                         mediatek,pull-up-adv = <0>;
 197                 };
 198
 199                 conf-pd {
 200                         pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
 201                         drive-strength = <8>;
 202                         mediatek,pull-down-adv = <0>;
 203                 };
 204         };
 205 };
 206
 207 &uart0 {
 208         status = "okay";
 209 };
 210
 211 &usb_phy {
 212         status = "okay";
 213 };
 214
 215 &watchdog {
 216         status = "okay";
 217 };
 218
 219 &wifi {
 220         nvmem-cells = <&eeprom_factory_0>;
 221         nvmem-cell-names = "eeprom";
 222         status = "okay";
 223 };
 224
 225 &xhci {
 226         status = "okay";
 227 };