target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch

   1 From 4fe33d4f4dc608fc5013390db58df06723282d01 Mon Sep 17 00:00:00 2001
   2 From: Mingkai Hu <mingkai.hu@nxp.com>
   3 Date: Thu, 2 Jun 2016 11:15:58 +0800
   4 Subject: [PATCH 129/141] clk: qoriq: add ls1046a support
   5
   6 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
   7 Integated-by: Yutang Jiang <yutang.jiang@nxp.com>
   8 ---
   9  drivers/clk/clk-qoriq.c |   41 +++++++++++++++++++++++++++++++++++++++++
  10  1 file changed, 41 insertions(+)
  11
  12 --- a/drivers/clk/clk-qoriq.c
  13 +++ b/drivers/clk/clk-qoriq.c
  14 @@ -275,6 +275,31 @@ static const struct clockgen_muxinfo ls1
  15         },
  16  };
  17
  18 +static const struct clockgen_muxinfo ls1046a_hwa1 = {
  19 +       {
  20 +               {},
  21 +               {},
  22 +               { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  23 +               { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
  24 +               { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
  25 +               { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
  26 +               { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  27 +               { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  28 +       },
  29 +};
  30 +
  31 +static const struct clockgen_muxinfo ls1046a_hwa2 = {
  32 +       {
  33 +               {},
  34 +               { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
  35 +               { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
  36 +               { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
  37 +               {},
  38 +               {},
  39 +               { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
  40 +       },
  41 +};
  42 +
  43  static const struct clockgen_muxinfo t1023_hwa1 = {
  44         {
  45                 {},
  46 @@ -508,6 +533,21 @@ static const struct clockgen_chipinfo ch
  47                 .flags = CG_PLL_8BIT,
  48         },
  49         {
  50 +               .compat = "fsl,ls1046a-clockgen",
  51 +               .init_periph = t2080_init_periph,
  52 +               .cmux_groups = {
  53 +                       &t1040_cmux
  54 +               },
  55 +               .hwaccel = {
  56 +                       &ls1046a_hwa1, &ls1046a_hwa2
  57 +               },
  58 +               .cmux_to_group = {
  59 +                       0, -1
  60 +               },
  61 +               .pll_mask = 0x07,
  62 +               .flags = CG_PLL_8BIT,
  63 +       },
  64 +       {
  65                 .compat = "fsl,ls2080a-clockgen",
  66                 .cmux_groups = {
  67                         &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
  68 @@ -1285,6 +1325,7 @@ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qo
  69  CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
  70  CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
  71  CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
  72 +CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
  73  CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
  74  CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
  75