target/linux/layerscape/patches-4.4/4044-drivers-memory-Add-deep-sleep-support-for-IFC.patch

   1 From bb35d670afd2f3501de36c158e9842817ce013b8 Mon Sep 17 00:00:00 2001
   2 From: Raghav Dogra <raghav@freescale.com>
   3 Date: Fri, 15 Jan 2016 17:10:09 +0530
   4 Subject: [PATCH 44/70] drivers/memory: Add deep sleep support for IFC
   5
   6 Add support of suspend, resume function to support deep sleep.
   7 Also make sure of SRAM initialization  during resume.
   8
   9 Signed-off-by: Raghav Dogra <raghav@freescale.com>
  10 ---
  11  drivers/memory/fsl_ifc.c |  163 ++++++++++++++++++++++++++++++++++++++++++++++
  12  include/linux/fsl_ifc.h  |    6 ++
  13  2 files changed, 169 insertions(+)
  14
  15 --- a/drivers/memory/fsl_ifc.c
  16 +++ b/drivers/memory/fsl_ifc.c
  17 @@ -24,6 +24,7 @@
  18  #include <linux/compiler.h>
  19  #include <linux/sched.h>
  20  #include <linux/spinlock.h>
  21 +#include <linux/delay.h>
  22  #include <linux/types.h>
  23  #include <linux/slab.h>
  24  #include <linux/io.h>
  25 @@ -35,6 +36,8 @@
  26
  27  struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
  28  EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
  29 +#define FSL_IFC_V1_3_0 0x01030000
  30 +#define IFC_TIMEOUT_MSECS      100000 /* 100ms */
  31
  32  /*
  33   * convert_ifc_address - convert the base address
  34 @@ -309,6 +312,161 @@ err:
  35         return ret;
  36  }
  37
  38 +#ifdef CONFIG_PM_SLEEP
  39 +/* save ifc registers */
  40 +static int fsl_ifc_suspend(struct device *dev)
  41 +{
  42 +       struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
  43 +       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  44 +       __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
  45 +                                                        gpcm_evter_intr_en;
  46 +
  47 +       ctrl->saved_regs = kzalloc(sizeof(struct fsl_ifc_regs), GFP_KERNEL);
  48 +       if (!ctrl->saved_regs)
  49 +               return -ENOMEM;
  50 +
  51 +       cm_evter_intr_en = ifc_in32(&ifc->cm_evter_intr_en);
  52 +       nand_evter_intr_en = ifc_in32(&ifc->ifc_nand.nand_evter_intr_en);
  53 +       nor_evter_intr_en = ifc_in32(&ifc->ifc_nor.nor_evter_intr_en);
  54 +       gpcm_evter_intr_en = ifc_in32(&ifc->ifc_gpcm.gpcm_evter_intr_en);
  55 +
  56 +/* IFC interrupts disabled */
  57 +
  58 +       ifc_out32(0x0, &ifc->cm_evter_intr_en);
  59 +       ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en);
  60 +       ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en);
  61 +       ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en);
  62 +
  63 +       memcpy_fromio(ctrl->saved_regs, ifc, sizeof(struct fsl_ifc_regs));
  64 +
  65 +/* save the interrupt values */
  66 +       ctrl->saved_regs->cm_evter_intr_en = cm_evter_intr_en;
  67 +       ctrl->saved_regs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
  68 +       ctrl->saved_regs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
  69 +       ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
  70 +
  71 +       return 0;
  72 +}
  73 +
  74 +/* restore ifc registers */
  75 +static int fsl_ifc_resume(struct device *dev)
  76 +{
  77 +       struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
  78 +       struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  79 +       struct fsl_ifc_regs *savd_regs = ctrl->saved_regs;
  80 +       uint32_t ver = 0, ncfgr, status, ifc_bank, i;
  81 +
  82 +/*
  83 + * IFC interrupts disabled
  84 + */
  85 +       ifc_out32(0x0, &ifc->cm_evter_intr_en);
  86 +       ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en);
  87 +       ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en);
  88 +       ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en);
  89 +
  90 +
  91 +       if (ctrl->saved_regs) {
  92 +               for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
  93 +                       ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr_ext,
  94 +                                       &ifc->cspr_cs[ifc_bank].cspr_ext);
  95 +                       ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr,
  96 +                                       &ifc->cspr_cs[ifc_bank].cspr);
  97 +                       ifc_out32(savd_regs->amask_cs[ifc_bank].amask,
  98 +                                       &ifc->amask_cs[ifc_bank].amask);
  99 +                       ifc_out32(savd_regs->csor_cs[ifc_bank].csor_ext,
 100 +                                       &ifc->csor_cs[ifc_bank].csor_ext);
 101 +                       ifc_out32(savd_regs->csor_cs[ifc_bank].csor,
 102 +                                       &ifc->csor_cs[ifc_bank].csor);
 103 +                       for (i = 0; i < 4; i++) {
 104 +                               ifc_out32(savd_regs->ftim_cs[ifc_bank].ftim[i],
 105 +                                       &ifc->ftim_cs[ifc_bank].ftim[i]);
 106 +                       }
 107 +               }
 108 +               ifc_out32(savd_regs->ifc_gcr, &ifc->ifc_gcr);
 109 +               ifc_out32(savd_regs->cm_evter_en, &ifc->cm_evter_en);
 110 +
 111 +/*
 112 +* IFC controller NAND machine registers
 113 +*/
 114 +               ifc_out32(savd_regs->ifc_nand.ncfgr, &ifc->ifc_nand.ncfgr);
 115 +               ifc_out32(savd_regs->ifc_nand.nand_fcr0,
 116 +                                               &ifc->ifc_nand.nand_fcr0);
 117 +               ifc_out32(savd_regs->ifc_nand.nand_fcr1,
 118 +                                               &ifc->ifc_nand.nand_fcr1);
 119 +               ifc_out32(savd_regs->ifc_nand.row0, &ifc->ifc_nand.row0);
 120 +               ifc_out32(savd_regs->ifc_nand.row1, &ifc->ifc_nand.row1);
 121 +               ifc_out32(savd_regs->ifc_nand.col0, &ifc->ifc_nand.col0);
 122 +               ifc_out32(savd_regs->ifc_nand.col1, &ifc->ifc_nand.col1);
 123 +               ifc_out32(savd_regs->ifc_nand.row2, &ifc->ifc_nand.row2);
 124 +               ifc_out32(savd_regs->ifc_nand.col2, &ifc->ifc_nand.col2);
 125 +               ifc_out32(savd_regs->ifc_nand.row3, &ifc->ifc_nand.row3);
 126 +               ifc_out32(savd_regs->ifc_nand.col3, &ifc->ifc_nand.col3);
 127 +               ifc_out32(savd_regs->ifc_nand.nand_fbcr,
 128 +                                               &ifc->ifc_nand.nand_fbcr);
 129 +               ifc_out32(savd_regs->ifc_nand.nand_fir0,
 130 +                                               &ifc->ifc_nand.nand_fir0);
 131 +               ifc_out32(savd_regs->ifc_nand.nand_fir1,
 132 +                                               &ifc->ifc_nand.nand_fir1);
 133 +               ifc_out32(savd_regs->ifc_nand.nand_fir2,
 134 +                                               &ifc->ifc_nand.nand_fir2);
 135 +               ifc_out32(savd_regs->ifc_nand.nand_csel,
 136 +                                               &ifc->ifc_nand.nand_csel);
 137 +               ifc_out32(savd_regs->ifc_nand.nandseq_strt,
 138 +                                               &ifc->ifc_nand.nandseq_strt);
 139 +               ifc_out32(savd_regs->ifc_nand.nand_evter_en,
 140 +                                               &ifc->ifc_nand.nand_evter_en);
 141 +               ifc_out32(savd_regs->ifc_nand.nanndcr, &ifc->ifc_nand.nanndcr);
 142 +
 143 +/*
 144 +* IFC controller NOR machine registers
 145 +*/
 146 +               ifc_out32(savd_regs->ifc_nor.nor_evter_en,
 147 +                                       &ifc->ifc_nor.nor_evter_en);
 148 +               ifc_out32(savd_regs->ifc_nor.norcr, &ifc->ifc_nor.norcr);
 149 +
 150 +/*
 151 + * IFC controller GPCM Machine registers
 152 + */
 153 +               ifc_out32(savd_regs->ifc_gpcm.gpcm_evter_en,
 154 +                                       &ifc->ifc_gpcm.gpcm_evter_en);
 155 +
 156 +
 157 +
 158 +/*
 159 + * IFC interrupts enabled
 160 + */
 161 +       ifc_out32(ctrl->saved_regs->cm_evter_intr_en, &ifc->cm_evter_intr_en);
 162 +       ifc_out32(ctrl->saved_regs->ifc_nand.nand_evter_intr_en,
 163 +                                       &ifc->ifc_nand.nand_evter_intr_en);
 164 +       ifc_out32(ctrl->saved_regs->ifc_nor.nor_evter_intr_en,
 165 +                                       &ifc->ifc_nor.nor_evter_intr_en);
 166 +       ifc_out32(ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en,
 167 +                                       &ifc->ifc_gpcm.gpcm_evter_intr_en);
 168 +
 169 +               kfree(ctrl->saved_regs);
 170 +               ctrl->saved_regs = NULL;
 171 +       }
 172 +
 173 +       ver = ifc_in32(&ctrl->regs->ifc_rev);
 174 +       ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
 175 +       if (ver >= FSL_IFC_V1_3_0) {
 176 +
 177 +               ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
 178 +                                       &ifc->ifc_nand.ncfgr);
 179 +               /* wait for  SRAM_INIT bit to be clear or timeout */
 180 +               status = spin_event_timeout(
 181 +                                       !(ifc_in32(&ifc->ifc_nand.ncfgr)
 182 +                                       & IFC_NAND_SRAM_INIT_EN),
 183 +                                       IFC_TIMEOUT_MSECS, 0);
 184 +
 185 +               if (!status)
 186 +                       dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
 187 +       }
 188 +
 189 +       return 0;
 190 +}
 191 +#endif /* CONFIG_PM_SLEEP */
 192 +
 193  static const struct of_device_id fsl_ifc_match[] = {
 194         {
 195                 .compatible = "fsl,ifc",
 196 @@ -316,10 +474,15 @@ static const struct of_device_id fsl_ifc
 197         {},
 198  };
 199
 200 +static const struct dev_pm_ops ifc_pm_ops = {
 201 +       SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
 202 +};
 203 +
 204  static struct platform_driver fsl_ifc_ctrl_driver = {
 205         .driver = {
 206                 .name   = "fsl-ifc",
 207                 .of_match_table = fsl_ifc_match,
 208 +               .pm = &ifc_pm_ops,
 209         },
 210         .probe       = fsl_ifc_ctrl_probe,
 211         .remove      = fsl_ifc_ctrl_remove,
 212 --- a/include/linux/fsl_ifc.h
 213 +++ b/include/linux/fsl_ifc.h
 214 @@ -270,6 +270,8 @@
 215   */
 216  /* Auto Boot Mode */
 217  #define IFC_NAND_NCFGR_BOOT            0x80000000
 218 +/* SRAM INIT EN */
 219 +#define IFC_NAND_SRAM_INIT_EN          0x20000000
 220  /* Addressing Mode-ROW0+n/COL0 */
 221  #define IFC_NAND_NCFGR_ADDR_MODE_RC0   0x00000000
 222  /* Addressing Mode-ROW0+n/COL0+n */
 223 @@ -842,6 +844,10 @@ struct fsl_ifc_ctrl {
 224         u32 nand_stat;
 225         wait_queue_head_t nand_wait;
 226         bool little_endian;
 227 +#ifdef CONFIG_PM_SLEEP
 228 +       /*save regs when system goes to deep sleep*/
 229 +       struct fsl_ifc_regs             *saved_regs;
 230 +#endif
 231  };
 232
 233  extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;