target/linux/layerscape/patches-4.4/3227-ls2088a-dts-add-ls2088a-dts.patch

   1 From 45ba5bb2bdc9462fe5998aeb75e2c7e33b56c9fb Mon Sep 17 00:00:00 2001
   2 From: Zhao Qiang <qiang.zhao@nxp.com>
   3 Date: Mon, 7 Nov 2016 10:23:52 +0800
   4 Subject: [PATCH 227/238] ls2088a/dts: add ls2088a dts
   5
   6 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
   7 ---
   8  arch/arm64/boot/dts/freescale/Makefile            |    2 +
   9  arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts |  241 ++++++
  10  arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts |  207 +++++
  11  arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi    |  854 +++++++++++++++++++++
  12  4 files changed, 1304 insertions(+)
  13  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
  14  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
  15  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
  16
  17 diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
  18 index b599645..e6c2a9f 100644
  19 --- a/arch/arm64/boot/dts/freescale/Makefile
  20 +++ b/arch/arm64/boot/dts/freescale/Makefile
  21 @@ -6,6 +6,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
  22  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
  23  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
  24  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
  25 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
  26 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
  27
  28  always         := $(dtb-y)
  29  subdir-y       := $(dts-dirs)
  30 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
  31 new file mode 100644
  32 index 0000000..04d3726
  33 --- /dev/null
  34 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
  35 @@ -0,0 +1,241 @@
  36 +/*
  37 + * Device Tree file for Freescale LS2080a QDS Board
  38 + *
  39 + * Copyright (C) 2016, Freescale Semiconductor
  40 + *
  41 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
  42 + *
  43 + * This file is licensed under the terms of the GNU General Public
  44 + * License version 2.  This program is licensed "as is" without any
  45 + * warranty of any kind, whether express or implied.
  46 + */
  47 +
  48 +/dts-v1/;
  49 +
  50 +#include "fsl-ls2088a.dtsi"
  51 +
  52 +/ {
  53 +       model = "Freescale Layerscape 2088a QDS Board";
  54 +       compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
  55 +};
  56 +
  57 +&esdhc {
  58 +       status = "okay";
  59 +};
  60 +
  61 +&ifc {
  62 +       status = "okay";
  63 +       #address-cells = <2>;
  64 +       #size-cells = <1>;
  65 +       ranges = <0x0 0x0 0x5 0x80000000 0x08000000
  66 +                 0x2 0x0 0x5 0x30000000 0x00010000
  67 +                 0x3 0x0 0x5 0x20000000 0x00010000>;
  68 +
  69 +       nor@0,0 {
  70 +            #address-cells = <1>;
  71 +            #size-cells = <1>;
  72 +            compatible = "cfi-flash";
  73 +            reg = <0x0 0x0 0x8000000>;
  74 +            bank-width = <2>;
  75 +            device-width = <1>;
  76 +       };
  77 +
  78 +       nand@2,0 {
  79 +            compatible = "fsl,ifc-nand";
  80 +            reg = <0x2 0x0 0x10000>;
  81 +       };
  82 +
  83 +       cpld@3,0 {
  84 +            reg = <0x3 0x0 0x10000>;
  85 +            compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
  86 +                         "fsl,fpga-qixis";
  87 +       };
  88 +};
  89 +
  90 +&ftm0 {
  91 +       status = "okay";
  92 +};
  93 +
  94 +&i2c0 {
  95 +       status = "okay";
  96 +       pca9547@77 {
  97 +               compatible = "nxp,pca9547";
  98 +               reg = <0x77>;
  99 +               #address-cells = <1>;
 100 +               #size-cells = <0>;
 101 +               i2c@0 {
 102 +                       #address-cells = <1>;
 103 +                       #size-cells = <0>;
 104 +                       reg = <0x00>;
 105 +                       rtc@68 {
 106 +                               compatible = "dallas,ds3232";
 107 +                               reg = <0x68>;
 108 +                       };
 109 +               };
 110 +
 111 +               i2c@2 {
 112 +                       #address-cells = <1>;
 113 +                       #size-cells = <0>;
 114 +                       reg = <0x02>;
 115 +
 116 +                       ina220@40 {
 117 +                               compatible = "ti,ina220";
 118 +                               reg = <0x40>;
 119 +                               shunt-resistor = <500>;
 120 +                       };
 121 +                       ina220@41 {
 122 +                               compatible = "ti,ina220";
 123 +                               reg = <0x41>;
 124 +                               shunt-resistor = <1000>;
 125 +                       };
 126 +               };
 127 +
 128 +               i2c@3 {
 129 +                       #address-cells = <1>;
 130 +                       #size-cells = <0>;
 131 +                       reg = <0x3>;
 132 +
 133 +                       adt7481@4c {
 134 +                               compatible = "adi,adt7461";
 135 +                               reg = <0x4c>;
 136 +                       };
 137 +               };
 138 +       };
 139 +};
 140 +
 141 +&i2c1 {
 142 +       status = "disabled";
 143 +};
 144 +
 145 +&i2c2 {
 146 +       status = "disabled";
 147 +};
 148 +
 149 +&i2c3 {
 150 +       status = "disabled";
 151 +};
 152 +
 153 +&dspi {
 154 +       status = "okay";
 155 +       dflash0: n25q128a {
 156 +               #address-cells = <1>;
 157 +               #size-cells = <1>;
 158 +               compatible = "st,m25p80";
 159 +               spi-max-frequency = <3000000>;
 160 +               reg = <0>;
 161 +       };
 162 +       dflash1: sst25wf040b {
 163 +               #address-cells = <1>;
 164 +               #size-cells = <1>;
 165 +               compatible = "st,m25p80";
 166 +               spi-max-frequency = <3000000>;
 167 +               reg = <1>;
 168 +       };
 169 +       dflash2: en25s64 {
 170 +               #address-cells = <1>;
 171 +               #size-cells = <1>;
 172 +               compatible = "st,m25p80";
 173 +               spi-max-frequency = <3000000>;
 174 +               reg = <2>;
 175 +       };
 176 +};
 177 +
 178 +&qspi {
 179 +       status = "okay";
 180 +       qflash0: s25fs256s1@0 {
 181 +               #address-cells = <1>;
 182 +               #size-cells = <1>;
 183 +               compatible = "st,m25p80";
 184 +               spi-max-frequency = <20000000>;
 185 +               m25p,fast-read;
 186 +               reg = <0>;
 187 +       };
 188 +
 189 +       qflash2: s25fs256s1@2 {
 190 +               #address-cells = <1>;
 191 +               #size-cells = <1>;
 192 +               compatible = "st,m25p80";
 193 +               spi-max-frequency = <20000000>;
 194 +               m25p,fast-read;
 195 +               reg = <2>;
 196 +       };
 197 +};
 198 +
 199 +&sata0 {
 200 +       status = "okay";
 201 +};
 202 +
 203 +&sata1 {
 204 +       status = "okay";
 205 +};
 206 +
 207 +&usb0 {
 208 +       status = "okay";
 209 +};
 210 +
 211 +&usb1 {
 212 +       status = "okay";
 213 +};
 214 +
 215 +&ifc {
 216 +       boardctrl: board-control@3,0 {
 217 +               #address-cells = <1>;
 218 +               #size-cells = <1>;
 219 +               compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
 220 +               reg = <3 0 0x300>;              /* TODO check address */
 221 +               ranges = <0 3 0 0x300>;
 222 +
 223 +               mdio_mux_emi1 {
 224 +                       compatible = "mdio-mux-mmioreg", "mdio-mux";
 225 +                       mdio-parent-bus = <&emdio1>;
 226 +                       reg = <0x54 1>;         /* BRDCFG4 */
 227 +                       mux-mask = <0xe0>;      /* EMI1_MDIO */
 228 +
 229 +                       #address-cells=<1>;
 230 +                       #size-cells = <0>;
 231 +
 232 +                       /* Child MDIO buses, one for each riser card:
 233 +                          reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
 234 +
 235 +                          VSC8234 PHYs on the riser cards.
 236 +                        */
 237 +
 238 +                       mdio_mux3: mdio@60 {
 239 +                               reg = <0x60>;
 240 +                               #address-cells = <1>;
 241 +                               #size-cells = <0>;
 242 +
 243 +                               mdio0_phy12: mdio_phy0@1c {
 244 +                                       reg = <0x1c>;
 245 +                                       phy-connection-type = "sgmii";
 246 +                               };
 247 +                               mdio0_phy13: mdio_phy1@1d {
 248 +                                       reg = <0x1d>;
 249 +                                       phy-connection-type = "sgmii";
 250 +                               };
 251 +                               mdio0_phy14: mdio_phy2@1e {
 252 +                                       reg = <0x1e>;
 253 +                                       phy-connection-type = "sgmii";
 254 +                               };
 255 +                               mdio0_phy15: mdio_phy3@1f {
 256 +                                       reg = <0x1f>;
 257 +                                       phy-connection-type = "sgmii";
 258 +                               };
 259 +                       };
 260 +               };
 261 +       };
 262 +};
 263 +
 264 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
 265 +&dpmac9 {
 266 +       phy-handle = <&mdio0_phy12>;
 267 +};
 268 +&dpmac10 {
 269 +       phy-handle = <&mdio0_phy13>;
 270 +};
 271 +&dpmac11 {
 272 +       phy-handle = <&mdio0_phy14>;
 273 +};
 274 +&dpmac12 {
 275 +       phy-handle = <&mdio0_phy15>;
 276 +};
 277 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
 278 new file mode 100644
 279 index 0000000..ce553fb
 280 --- /dev/null
 281 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
 282 @@ -0,0 +1,207 @@
 283 +/*
 284 + * Device Tree file for Freescale LS2080a RDB board
 285 + *
 286 + * Copyright (C) 2015, Freescale Semiconductor
 287 + *
 288 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 289 + *
 290 + * This file is licensed under the terms of the GNU General Public
 291 + * License version 2.  This program is licensed "as is" without any
 292 + * warranty of any kind, whether express or implied.
 293 + */
 294 +
 295 +/dts-v1/;
 296 +
 297 +#include "fsl-ls2088a.dtsi"
 298 +
 299 +/ {
 300 +       model = "Freescale Layerscape 2088a RDB Board";
 301 +       compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
 302 +};
 303 +
 304 +&esdhc {
 305 +       status = "okay";
 306 +};
 307 +
 308 +&ifc {
 309 +       status = "okay";
 310 +       #address-cells = <2>;
 311 +       #size-cells = <1>;
 312 +       ranges = <0x0 0x0 0x5 0x80000000 0x08000000
 313 +                 0x2 0x0 0x5 0x30000000 0x00010000
 314 +                 0x3 0x0 0x5 0x20000000 0x00010000>;
 315 +
 316 +       nor@0,0 {
 317 +            #address-cells = <1>;
 318 +            #size-cells = <1>;
 319 +            compatible = "cfi-flash";
 320 +            reg = <0x0 0x0 0x8000000>;
 321 +            bank-width = <2>;
 322 +            device-width = <1>;
 323 +       };
 324 +
 325 +       nand@2,0 {
 326 +            compatible = "fsl,ifc-nand";
 327 +            reg = <0x2 0x0 0x10000>;
 328 +       };
 329 +
 330 +       cpld@3,0 {
 331 +            reg = <0x3 0x0 0x10000>;
 332 +            compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
 333 +                         "fsl,fpga-qixis";
 334 +       };
 335 +};
 336 +
 337 +&ftm0 {
 338 +       status = "okay";
 339 +};
 340 +
 341 +&i2c0 {
 342 +       status = "okay";
 343 +       pca9547@75 {
 344 +               compatible = "nxp,pca9547";
 345 +               reg = <0x75>;
 346 +               #address-cells = <1>;
 347 +               #size-cells = <0>;
 348 +               i2c-mux-never-disable;
 349 +               i2c@1 {
 350 +                       #address-cells = <1>;
 351 +                       #size-cells = <0>;
 352 +                       reg = <0x01>;
 353 +                       rtc@68 {
 354 +                               compatible = "dallas,ds3232";
 355 +                               reg = <0x68>;
 356 +                       };
 357 +               };
 358 +
 359 +               i2c@3 {
 360 +                       #address-cells = <1>;
 361 +                       #size-cells = <0>;
 362 +                       reg = <0x3>;
 363 +
 364 +                       adt7481@4c {
 365 +                               compatible = "adi,adt7461";
 366 +                               reg = <0x4c>;
 367 +                       };
 368 +               };
 369 +       };
 370 +};
 371 +
 372 +&i2c1 {
 373 +       status = "disabled";
 374 +};
 375 +
 376 +&i2c2 {
 377 +       status = "disabled";
 378 +};
 379 +
 380 +&i2c3 {
 381 +       status = "disabled";
 382 +};
 383 +
 384 +&dspi {
 385 +       status = "okay";
 386 +       dflash0: n25q512a {
 387 +               #address-cells = <1>;
 388 +               #size-cells = <1>;
 389 +               compatible = "st,m25p80";
 390 +               spi-max-frequency = <3000000>;
 391 +               reg = <0>;
 392 +       };
 393 +};
 394 +
 395 +&qspi {
 396 +       status = "disabled";
 397 +};
 398 +
 399 +&sata0 {
 400 +       status = "okay";
 401 +};
 402 +
 403 +&sata1 {
 404 +       status = "okay";
 405 +};
 406 +
 407 +&usb0 {
 408 +       status = "okay";
 409 +};
 410 +
 411 +&usb1 {
 412 +       status = "okay";
 413 +};
 414 +
 415 +&emdio1 {
 416 +       /* CS4340 PHYs */
 417 +       mdio1_phy1: emdio1_phy@1 {
 418 +               reg = <0x10>;
 419 +               phy-connection-type = "xfi";
 420 +       };
 421 +       mdio1_phy2: emdio1_phy@2 {
 422 +               reg = <0x11>;
 423 +               phy-connection-type = "xfi";
 424 +       };
 425 +       mdio1_phy3: emdio1_phy@3 {
 426 +               reg = <0x12>;
 427 +               phy-connection-type = "xfi";
 428 +       };
 429 +       mdio1_phy4: emdio1_phy@4 {
 430 +               reg = <0x13>;
 431 +               phy-connection-type = "xfi";
 432 +       };
 433 +};
 434 +
 435 +&emdio2 {
 436 +       /* AQR405 PHYs */
 437 +       mdio2_phy1: emdio2_phy@1 {
 438 +               compatible = "ethernet-phy-ieee802.3-c45";
 439 +               interrupts = <0 1 0x4>; /* Level high type */
 440 +               reg = <0x0>;
 441 +               phy-connection-type = "xfi";
 442 +       };
 443 +       mdio2_phy2: emdio2_phy@2 {
 444 +               compatible = "ethernet-phy-ieee802.3-c45";
 445 +               interrupts = <0 2 0x4>; /* Level high type */
 446 +               reg = <0x1>;
 447 +               phy-connection-type = "xfi";
 448 +       };
 449 +       mdio2_phy3: emdio2_phy@3 {
 450 +               compatible = "ethernet-phy-ieee802.3-c45";
 451 +               interrupts = <0 4 0x4>; /* Level high type */
 452 +               reg = <0x2>;
 453 +               phy-connection-type = "xfi";
 454 +       };
 455 +       mdio2_phy4: emdio2_phy@4 {
 456 +               compatible = "ethernet-phy-ieee802.3-c45";
 457 +               interrupts = <0 5 0x4>; /* Level high type */
 458 +               reg = <0x3>;
 459 +               phy-connection-type = "xfi";
 460 +       };
 461 +};
 462 +
 463 +/* Update DPMAC connections to external PHYs, under the assumption of
 464 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
 465 + */
 466 +&dpmac1 {
 467 +       phy-handle = <&mdio1_phy1>;
 468 +};
 469 +&dpmac2 {
 470 +       phy-handle = <&mdio1_phy2>;
 471 +};
 472 +&dpmac3 {
 473 +       phy-handle = <&mdio1_phy3>;
 474 +};
 475 +&dpmac4 {
 476 +       phy-handle = <&mdio1_phy4>;
 477 +};
 478 +&dpmac5 {
 479 +       phy-handle = <&mdio2_phy1>;
 480 +};
 481 +&dpmac6 {
 482 +       phy-handle = <&mdio2_phy2>;
 483 +};
 484 +&dpmac7 {
 485 +       phy-handle = <&mdio2_phy3>;
 486 +};
 487 +&dpmac8 {
 488 +       phy-handle = <&mdio2_phy4>;
 489 +};
 490 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
 491 new file mode 100644
 492 index 0000000..bd69942
 493 --- /dev/null
 494 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
 495 @@ -0,0 +1,854 @@
 496 +/*
 497 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
 498 + *
 499 + * Copyright (C) 2016, Freescale Semiconductor
 500 + *
 501 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 502 + *
 503 + * This file is dual-licensed: you can use it either under the terms
 504 + * of the GPLv2 or the X11 license, at your option. Note that this dual
 505 + * licensing only applies to this file, and not this project as a
 506 + * whole.
 507 + *
 508 + *  a) This library is free software; you can redistribute it and/or
 509 + *     modify it under the terms of the GNU General Public License as
 510 + *     published by the Free Software Foundation; either version 2 of the
 511 + *     License, or (at your option) any later version.
 512 + *
 513 + *     This library is distributed in the hope that it will be useful,
 514 + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 515 + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 516 + *     GNU General Public License for more details.
 517 + *
 518 + * Or, alternatively,
 519 + *
 520 + *  b) Permission is hereby granted, free of charge, to any person
 521 + *     obtaining a copy of this software and associated documentation
 522 + *     files (the "Software"), to deal in the Software without
 523 + *     restriction, including without limitation the rights to use,
 524 + *     copy, modify, merge, publish, distribute, sublicense, and/or
 525 + *     sell copies of the Software, and to permit persons to whom the
 526 + *     Software is furnished to do so, subject to the following
 527 + *     conditions:
 528 + *
 529 + *     The above copyright notice and this permission notice shall be
 530 + *     included in all copies or substantial portions of the Software.
 531 + *
 532 + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 533 + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 534 + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 535 + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 536 + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 537 + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 538 + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 539 + *     OTHER DEALINGS IN THE SOFTWARE.
 540 + */
 541 +
 542 +#include <dt-bindings/thermal/thermal.h>
 543 +
 544 +/memreserve/ 0x80000000 0x00010000;
 545 +
 546 +/ {
 547 +       compatible = "fsl,ls2088a";
 548 +       interrupt-parent = <&gic>;
 549 +       #address-cells = <2>;
 550 +       #size-cells = <2>;
 551 +
 552 +       cpus {
 553 +               #address-cells = <2>;
 554 +               #size-cells = <0>;
 555 +
 556 +               cpu0: cpu@0 {
 557 +                       device_type = "cpu";
 558 +                       compatible = "arm,cortex-a72";
 559 +                       reg = <0x0 0x0>;
 560 +                       clocks = <&clockgen 1 0>;
 561 +                       #cooling-cells = <2>;
 562 +                       cpu-idle-states = <&CPU_PW20>;
 563 +               };
 564 +
 565 +               cpu1: cpu@1 {
 566 +                       device_type = "cpu";
 567 +                       compatible = "arm,cortex-a72";
 568 +                       reg = <0x0 0x1>;
 569 +                       clocks = <&clockgen 1 0>;
 570 +                       cpu-idle-states = <&CPU_PW20>;
 571 +               };
 572 +
 573 +               cpu2: cpu@100 {
 574 +                       device_type = "cpu";
 575 +                       compatible = "arm,cortex-a72";
 576 +                       reg = <0x0 0x100>;
 577 +                       clocks = <&clockgen 1 1>;
 578 +                       #cooling-cells = <2>;
 579 +                       cpu-idle-states = <&CPU_PW20>;
 580 +               };
 581 +
 582 +               cpu3: cpu@101 {
 583 +                       device_type = "cpu";
 584 +                       compatible = "arm,cortex-a72";
 585 +                       reg = <0x0 0x101>;
 586 +                       clocks = <&clockgen 1 1>;
 587 +                       cpu-idle-states = <&CPU_PW20>;
 588 +               };
 589 +
 590 +               cpu4: cpu@200 {
 591 +                       device_type = "cpu";
 592 +                       compatible = "arm,cortex-a72";
 593 +                       reg = <0x0 0x200>;
 594 +                       clocks = <&clockgen 1 2>;
 595 +                       #cooling-cells = <2>;
 596 +                       cpu-idle-states = <&CPU_PW20>;
 597 +               };
 598 +
 599 +               cpu5: cpu@201 {
 600 +                       device_type = "cpu";
 601 +                       compatible = "arm,cortex-a72";
 602 +                       reg = <0x0 0x201>;
 603 +                       clocks = <&clockgen 1 2>;
 604 +                       cpu-idle-states = <&CPU_PW20>;
 605 +               };
 606 +
 607 +               cpu6: cpu@300 {
 608 +                       device_type = "cpu";
 609 +                       compatible = "arm,cortex-a72";
 610 +                       reg = <0x0 0x300>;
 611 +                       clocks = <&clockgen 1 3>;
 612 +                       #cooling-cells = <2>;
 613 +                       cpu-idle-states = <&CPU_PW20>;
 614 +               };
 615 +
 616 +               cpu7: cpu@301 {
 617 +                       device_type = "cpu";
 618 +                       compatible = "arm,cortex-a72";
 619 +                       reg = <0x0 0x301>;
 620 +                       clocks = <&clockgen 1 3>;
 621 +                       cpu-idle-states = <&CPU_PW20>;
 622 +               };
 623 +       };
 624 +
 625 +       pmu {
 626 +               compatible = "arm,armv8-pmuv3";
 627 +               interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
 628 +       };
 629 +
 630 +       idle-states {
 631 +               entry-method = "arm,psci";
 632 +
 633 +               CPU_PW20: cpu-pw20 {
 634 +                       compatible = "arm,idle-state";
 635 +                       idle-state-name = "PW20";
 636 +                       arm,psci-suspend-param = <0x00010000>;
 637 +                       entry-latency-us = <2000>;
 638 +                       exit-latency-us = <2000>;
 639 +                       min-residency-us = <6000>;
 640 +               };
 641 +       };
 642 +
 643 +       gic: interrupt-controller@6000000 {
 644 +               compatible = "arm,gic-v3";
 645 +               reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 646 +                     <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
 647 +                     <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 648 +                     <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 649 +                     <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 650 +               #interrupt-cells = <3>;
 651 +               #address-cells = <2>;
 652 +               #size-cells = <2>;
 653 +               ranges;
 654 +               interrupt-controller;
 655 +               interrupts = <1 9 0x4>;
 656 +
 657 +               its: gic-its@6020000 {
 658 +                       compatible = "arm,gic-v3-its";
 659 +                       msi-controller;
 660 +                       reg = <0x0 0x6020000 0 0x20000>;
 661 +               };
 662 +       };
 663 +
 664 +       sysclk: sysclk {
 665 +               compatible = "fixed-clock";
 666 +               #clock-cells = <0>;
 667 +               clock-frequency = <100000000>;
 668 +               clock-output-names = "sysclk";
 669 +       };
 670 +
 671 +       clockgen: clocking@1300000 {
 672 +               compatible = "fsl,ls2088a-clockgen";
 673 +               reg = <0 0x1300000 0 0xa0000>;
 674 +               #clock-cells = <2>;
 675 +               clocks = <&sysclk>;
 676 +       };
 677 +
 678 +       tmu: tmu@1f80000 {
 679 +               compatible = "fsl,qoriq-tmu", "fsl,ls2080a-tmu", "fsl,ls2088a-tmu";
 680 +               reg = <0x0 0x1f80000 0x0 0x10000>;
 681 +               interrupts = <0 23 0x4>;
 682 +               fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 683 +               fsl,tmu-calibration = <0x00000000 0x00000026
 684 +                                      0x00000001 0x0000002d
 685 +                                      0x00000002 0x00000032
 686 +                                      0x00000003 0x00000039
 687 +                                      0x00000004 0x0000003f
 688 +                                      0x00000005 0x00000046
 689 +                                      0x00000006 0x0000004d
 690 +                                      0x00000007 0x00000054
 691 +                                      0x00000008 0x0000005a
 692 +                                      0x00000009 0x00000061
 693 +                                      0x0000000a 0x0000006a
 694 +                                      0x0000000b 0x00000071
 695 +
 696 +                                      0x00010000 0x00000025
 697 +                                      0x00010001 0x0000002c
 698 +                                      0x00010002 0x00000035
 699 +                                      0x00010003 0x0000003d
 700 +                                      0x00010004 0x00000045
 701 +                                      0x00010005 0x0000004e
 702 +                                      0x00010006 0x00000057
 703 +                                      0x00010007 0x00000061
 704 +                                      0x00010008 0x0000006b
 705 +                                      0x00010009 0x00000076
 706 +
 707 +                                      0x00020000 0x00000029
 708 +                                      0x00020001 0x00000033
 709 +                                      0x00020002 0x0000003d
 710 +                                      0x00020003 0x00000049
 711 +                                      0x00020004 0x00000056
 712 +                                      0x00020005 0x00000061
 713 +                                      0x00020006 0x0000006d
 714 +
 715 +                                      0x00030000 0x00000021
 716 +                                      0x00030001 0x0000002a
 717 +                                      0x00030002 0x0000003c
 718 +                                      0x00030003 0x0000004e>;
 719 +               little-endian;
 720 +               #thermal-sensor-cells = <1>;
 721 +       };
 722 +
 723 +       thermal-zones {
 724 +               cpu_thermal: cpu-thermal {
 725 +                       polling-delay-passive = <1000>;
 726 +                       polling-delay = <5000>;
 727 +
 728 +                       thermal-sensors = <&tmu 4>;
 729 +
 730 +                       trips {
 731 +                               cpu_alert: cpu-alert {
 732 +                                       temperature = <75000>;
 733 +                                       hysteresis = <2000>;
 734 +                                       type = "passive";
 735 +                               };
 736 +                               cpu_crit: cpu-crit {
 737 +                                       temperature = <85000>;
 738 +                                       hysteresis = <2000>;
 739 +                                       type = "critical";
 740 +                               };
 741 +                       };
 742 +
 743 +                       cooling-maps {
 744 +                               map0 {
 745 +                                       trip = <&cpu_alert>;
 746 +                                       cooling-device =
 747 +                                               <&cpu0 THERMAL_NO_LIMIT
 748 +                                               THERMAL_NO_LIMIT>;
 749 +                               };
 750 +                               map1 {
 751 +                                       trip = <&cpu_alert>;
 752 +                                       cooling-device =
 753 +                                               <&cpu2 THERMAL_NO_LIMIT
 754 +                                               THERMAL_NO_LIMIT>;
 755 +                               };
 756 +                               map2 {
 757 +                                       trip = <&cpu_alert>;
 758 +                                       cooling-device =
 759 +                                               <&cpu4 THERMAL_NO_LIMIT
 760 +                                               THERMAL_NO_LIMIT>;
 761 +                               };
 762 +                               map3 {
 763 +                                       trip = <&cpu_alert>;
 764 +                                       cooling-device =
 765 +                                               <&cpu6 THERMAL_NO_LIMIT
 766 +                                               THERMAL_NO_LIMIT>;
 767 +                               };
 768 +                       };
 769 +               };
 770 +       };
 771 +
 772 +       serial0: serial@21c0500 {
 773 +               device_type = "serial";
 774 +               compatible = "fsl,ns16550", "ns16550a";
 775 +               reg = <0x0 0x21c0500 0x0 0x100>;
 776 +               clocks = <&clockgen 4 3>;
 777 +               interrupts = <0 32 0x4>; /* Level high type */
 778 +       };
 779 +
 780 +       serial1: serial@21c0600 {
 781 +               device_type = "serial";
 782 +               compatible = "fsl,ns16550", "ns16550a";
 783 +               reg = <0x0 0x21c0600 0x0 0x100>;
 784 +               clocks = <&clockgen 4 3>;
 785 +               interrupts = <0 32 0x4>; /* Level high type */
 786 +       };
 787 +               cluster1_core0_watchdog: wdt@c000000 {
 788 +                       compatible = "arm,sp805-wdt", "arm,primecell";
 789 +                       reg = <0x0 0xc000000 0x0 0x1000>;
 790 +                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 791 +                       clock-names = "apb_pclk", "wdog_clk";
 792 +               };
 793 +
 794 +               cluster1_core1_watchdog: wdt@c010000 {
 795 +                       compatible = "arm,sp805-wdt", "arm,primecell";
 796 +                       reg = <0x0 0xc010000 0x0 0x1000>;
 797 +                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 798 +                       clock-names = "apb_pclk", "wdog_clk";
 799 +               };
 800 +
 801 +               cluster2_core0_watchdog: wdt@c100000 {
 802 +                       compatible = "arm,sp805-wdt", "arm,primecell";
 803 +                       reg = <0x0 0xc100000 0x0 0x1000>;
 804 +                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 805 +                       clock-names = "apb_pclk", "wdog_clk";
 806 +               };
 807 +
 808 +               cluster2_core1_watchdog: wdt@c110000 {
 809 +                       compatible = "arm,sp805-wdt", "arm,primecell";
 810 +                       reg = <0x0 0xc110000 0x0 0x1000>;
 811 +                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 812 +                       clock-names = "apb_pclk", "wdog_clk";
 813 +               };
 814 +
 815 +               cluster3_core0_watchdog: wdt@c200000 {
 816 +                       compatible = "arm,sp805-wdt", "arm,primecell";
 817 +                       reg = <0x0 0xc200000 0x0 0x1000>;
 818 +                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 819 +                       clock-names = "apb_pclk", "wdog_clk";
 820 +               };
 821 +
 822 +               cluster3_core1_watchdog: wdt@c210000 {
 823 +                       compatible = "arm,sp805-wdt", "arm,primecell";
 824 +                       reg = <0x0 0xc210000 0x0 0x1000>;
 825 +                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 826 +                       clock-names = "apb_pclk", "wdog_clk";
 827 +               };
 828 +
 829 +               cluster4_core0_watchdog: wdt@c300000 {
 830 +                       compatible = "arm,sp805-wdt", "arm,primecell";
 831 +                       reg = <0x0 0xc300000 0x0 0x1000>;
 832 +                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 833 +                       clock-names = "apb_pclk", "wdog_clk";
 834 +               };
 835 +
 836 +               cluster4_core1_watchdog: wdt@c310000 {
 837 +                       compatible = "arm,sp805-wdt", "arm,primecell";
 838 +                       reg = <0x0 0xc310000 0x0 0x1000>;
 839 +                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 840 +                       clock-names = "apb_pclk", "wdog_clk";
 841 +               };
 842 +
 843 +       gpio0: gpio@2300000 {
 844 +               compatible = "fsl,qoriq-gpio";
 845 +               reg = <0x0 0x2300000 0x0 0x10000>;
 846 +               interrupts = <0 36 0x4>; /* Level high type */
 847 +               gpio-controller;
 848 +               little-endian;
 849 +               #gpio-cells = <2>;
 850 +               interrupt-controller;
 851 +               #interrupt-cells = <2>;
 852 +       };
 853 +
 854 +       gpio1: gpio@2310000 {
 855 +               compatible = "fsl,qoriq-gpio";
 856 +               reg = <0x0 0x2310000 0x0 0x10000>;
 857 +               interrupts = <0 36 0x4>; /* Level high type */
 858 +               gpio-controller;
 859 +               little-endian;
 860 +               #gpio-cells = <2>;
 861 +               interrupt-controller;
 862 +               #interrupt-cells = <2>;
 863 +       };
 864 +
 865 +       gpio2: gpio@2320000 {
 866 +               compatible = "fsl,qoriq-gpio";
 867 +               reg = <0x0 0x2320000 0x0 0x10000>;
 868 +               interrupts = <0 37 0x4>; /* Level high type */
 869 +               gpio-controller;
 870 +               little-endian;
 871 +               #gpio-cells = <2>;
 872 +               interrupt-controller;
 873 +               #interrupt-cells = <2>;
 874 +       };
 875 +
 876 +       gpio3: gpio@2330000 {
 877 +               compatible = "fsl,qoriq-gpio";
 878 +               reg = <0x0 0x2330000 0x0 0x10000>;
 879 +               interrupts = <0 37 0x4>; /* Level high type */
 880 +               gpio-controller;
 881 +               little-endian;
 882 +               #gpio-cells = <2>;
 883 +               interrupt-controller;
 884 +               #interrupt-cells = <2>;
 885 +       };
 886 +
 887 +       /* TODO: WRIOP (CCSR?) */
 888 +       emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
 889 +               compatible = "fsl,fman-memac-mdio";
 890 +               reg = <0x0 0x8B96000 0x0 0x1000>;
 891 +               device_type = "mdio";                   /* TODO: is this necessary? */
 892 +               little-endian;  /* force the driver in LE mode */
 893 +
 894 +               /* Not necessary on the QDS, but needed on the RDB */
 895 +               #address-cells = <1>;
 896 +               #size-cells = <0>;
 897 +       };
 898 +
 899 +       emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
 900 +               compatible = "fsl,fman-memac-mdio";
 901 +               reg = <0x0 0x8B97000 0x0 0x1000>;
 902 +               device_type = "mdio";                   /* TODO: is this necessary? */
 903 +               little-endian;  /* force the driver in LE mode */
 904 +
 905 +               #address-cells = <1>;
 906 +               #size-cells = <0>;
 907 +       };
 908 +
 909 +       ifc: ifc@2240000 {
 910 +               compatible = "fsl,ifc", "simple-bus";
 911 +               reg = <0x0 0x2240000 0x0 0x20000>;
 912 +               interrupts = <0 21 0x4>; /* Level high type */
 913 +               little-endian;
 914 +               #address-cells = <2>;
 915 +               #size-cells = <1>;
 916 +
 917 +               ranges = <0 0 0x5 0x80000000 0x08000000
 918 +                         2 0 0x5 0x30000000 0x00010000
 919 +                         3 0 0x5 0x20000000 0x00010000>;
 920 +       };
 921 +
 922 +       esdhc: esdhc@2140000 {
 923 +               compatible = "fsl,ls2088a-esdhc", "fsl,ls2080a-esdhc",
 924 +                            "fsl,esdhc";
 925 +               reg = <0x0 0x2140000 0x0 0x10000>;
 926 +               interrupts = <0 28 0x4>; /* Level high type */
 927 +               clock-frequency = <0>;
 928 +               voltage-ranges = <1800 1800 3300 3300>;
 929 +               sdhci,auto-cmd12;
 930 +               little-endian;
 931 +               bus-width = <4>;
 932 +       };
 933 +
 934 +       ftm0: ftm0@2800000 {
 935 +               compatible = "fsl,ftm-alarm";
 936 +               reg = <0x0 0x2800000 0x0 0x10000>;
 937 +               interrupts = <0 44 4>;
 938 +       };
 939 +
 940 +       reset: reset@1E60000 {
 941 +               compatible = "fsl,ls-reset";
 942 +               reg = <0x0 0x1E60000 0x0 0x10000>;
 943 +       };
 944 +
 945 +       dspi: dspi@2100000 {
 946 +               compatible = "fsl,ls2088a-dspi", "fsl,ls2085a-dspi",
 947 +                            "fsl,ls2080a-dspi";
 948 +               #address-cells = <1>;
 949 +               #size-cells = <0>;
 950 +               reg = <0x0 0x2100000 0x0 0x10000>;
 951 +               interrupts = <0 26 0x4>; /* Level high type */
 952 +               clocks = <&clockgen 4 3>;
 953 +               clock-names = "dspi";
 954 +               spi-num-chipselects = <5>;
 955 +               bus-num = <0>;
 956 +       };
 957 +
 958 +       i2c0: i2c@2000000 {
 959 +               compatible = "fsl,vf610-i2c";
 960 +               #address-cells = <1>;
 961 +               #size-cells = <0>;
 962 +               reg = <0x0 0x2000000 0x0 0x10000>;
 963 +               interrupts = <0 34 0x4>; /* Level high type */
 964 +               clock-names = "i2c";
 965 +               clocks = <&clockgen 4 3>;
 966 +       };
 967 +
 968 +       i2c1: i2c@2010000 {
 969 +               compatible = "fsl,vf610-i2c";
 970 +               #address-cells = <1>;
 971 +               #size-cells = <0>;
 972 +               reg = <0x0 0x2010000 0x0 0x10000>;
 973 +               interrupts = <0 34 0x4>; /* Level high type */
 974 +               clock-names = "i2c";
 975 +               clocks = <&clockgen 4 3>;
 976 +       };
 977 +
 978 +       i2c2: i2c@2020000 {
 979 +               compatible = "fsl,vf610-i2c";
 980 +               #address-cells = <1>;
 981 +               #size-cells = <0>;
 982 +               reg = <0x0 0x2020000 0x0 0x10000>;
 983 +               interrupts = <0 35 0x4>; /* Level high type */
 984 +               clock-names = "i2c";
 985 +               clocks = <&clockgen 4 3>;
 986 +       };
 987 +
 988 +       i2c3: i2c@2030000 {
 989 +               compatible = "fsl,vf610-i2c";
 990 +               #address-cells = <1>;
 991 +               #size-cells = <0>;
 992 +               reg = <0x0 0x2030000 0x0 0x10000>;
 993 +               interrupts = <0 35 0x4>; /* Level high type */
 994 +               clock-names = "i2c";
 995 +               clocks = <&clockgen 4 3>;
 996 +       };
 997 +
 998 +       qspi: quadspi@20c0000 {
 999 +               compatible = "fsl,ls2088a-qspi", "fsl,ls2080a-qspi";
1000 +               #address-cells = <1>;
1001 +               #size-cells = <0>;
1002 +               reg = <0x0 0x20c0000 0x0 0x10000>,
1003 +                     <0x0 0x20000000 0x0 0x10000000>;
1004 +               reg-names = "QuadSPI", "QuadSPI-memory";
1005 +               interrupts = <0 25 0x4>; /* Level high type */
1006 +               clocks = <&clockgen 4 3>, <&clockgen 4 3>;
1007 +               clock-names = "qspi_en", "qspi";
1008 +       };
1009 +
1010 +       pcie1: pcie@3400000 {
1011 +               compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
1012 +                            "fsl,ls2085a-pcie", "snps,dw-pcie";
1013 +               reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
1014 +                      0x20 0x00000000 0x0 0x00002000>; /* configuration space */
1015 +               reg-names = "regs", "config";
1016 +               interrupts = <0 108 0x4>; /* Level high type */
1017 +               interrupt-names = "aer";
1018 +               #address-cells = <3>;
1019 +               #size-cells = <2>;
1020 +               device_type = "pci";
1021 +               dma-coherent;
1022 +               fsl,lut_diff;
1023 +               num-lanes = <4>;
1024 +               bus-range = <0x0 0xff>;
1025 +               ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
1026 +                         0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1027 +               msi-parent = <&its>;
1028 +               #interrupt-cells = <1>;
1029 +               interrupt-map-mask = <0 0 0 7>;
1030 +               interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1031 +                               <0000 0 0 2 &gic 0 0 0 110 4>,
1032 +                               <0000 0 0 3 &gic 0 0 0 111 4>,
1033 +                               <0000 0 0 4 &gic 0 0 0 112 4>;
1034 +       };
1035 +
1036 +       pcie2: pcie@3500000 {
1037 +               compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
1038 +                            "fsl,ls2085a-pcie", "snps,dw-pcie";
1039 +               reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
1040 +                      0x28 0x00000000 0x0 0x00002000>; /* configuration space */
1041 +               reg-names = "regs", "config";
1042 +               interrupts = <0 113 0x4>; /* Level high type */
1043 +               interrupt-names = "aer";
1044 +               #address-cells = <3>;
1045 +               #size-cells = <2>;
1046 +               device_type = "pci";
1047 +               dma-coherent;
1048 +               fsl,lut_diff;
1049 +               num-lanes = <4>;
1050 +               bus-range = <0x0 0xff>;
1051 +               ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
1052 +                         0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1053 +               msi-parent = <&its>;
1054 +               #interrupt-cells = <1>;
1055 +               interrupt-map-mask = <0 0 0 7>;
1056 +               interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1057 +                               <0000 0 0 2 &gic 0 0 0 115 4>,
1058 +                               <0000 0 0 3 &gic 0 0 0 116 4>,
1059 +                               <0000 0 0 4 &gic 0 0 0 117 4>;
1060 +       };
1061 +
1062 +       pcie3: pcie@3600000 {
1063 +               compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
1064 +                            "fsl,ls2085a-pcie", "snps,dw-pcie";
1065 +               reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
1066 +                      0x30 0x00000000 0x0 0x00002000>; /* configuration space */
1067 +               reg-names = "regs", "config";
1068 +               interrupts = <0 118 0x4>; /* Level high type */
1069 +               interrupt-names = "aer";
1070 +               #address-cells = <3>;
1071 +               #size-cells = <2>;
1072 +               device_type = "pci";
1073 +               dma-coherent;
1074 +               fsl,lut_diff;
1075 +               num-lanes = <8>;
1076 +               bus-range = <0x0 0xff>;
1077 +               ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
1078 +                         0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1079 +               msi-parent = <&its>;
1080 +               #interrupt-cells = <1>;
1081 +               interrupt-map-mask = <0 0 0 7>;
1082 +               interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1083 +                               <0000 0 0 2 &gic 0 0 0 120 4>,
1084 +                               <0000 0 0 3 &gic 0 0 0 121 4>,
1085 +                               <0000 0 0 4 &gic 0 0 0 122 4>;
1086 +       };
1087 +
1088 +       pcie4: pcie@3700000 {
1089 +               compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
1090 +                            "fsl,ls2085a-pcie", "snps,dw-pcie";
1091 +               reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
1092 +                      0x38 0x00000000 0x0 0x00002000>; /* configuration space */
1093 +               reg-names = "regs", "config";
1094 +               interrupts = <0 123 0x4>; /* Level high type */
1095 +               interrupt-names = "aer";
1096 +               #address-cells = <3>;
1097 +               #size-cells = <2>;
1098 +               device_type = "pci";
1099 +               dma-coherent;
1100 +               fsl,lut_diff;
1101 +               num-lanes = <4>;
1102 +               bus-range = <0x0 0xff>;
1103 +               ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000   /* downstream I/O */
1104 +                         0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1105 +               msi-parent = <&its>;
1106 +               #interrupt-cells = <1>;
1107 +               interrupt-map-mask = <0 0 0 7>;
1108 +               interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1109 +                               <0000 0 0 2 &gic 0 0 0 125 4>,
1110 +                               <0000 0 0 3 &gic 0 0 0 126 4>,
1111 +                               <0000 0 0 4 &gic 0 0 0 127 4>;
1112 +       };
1113 +
1114 +       sata0: sata@3200000 {
1115 +               status = "disabled";
1116 +               compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
1117 +               reg = <0x0 0x3200000 0x0 0x10000>;
1118 +               interrupts = <0 133 0x4>; /* Level high type */
1119 +               clocks = <&clockgen 4 3>;
1120 +       };
1121 +
1122 +       sata1: sata@3210000 {
1123 +               status = "disabled";
1124 +               compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
1125 +               reg = <0x0 0x3210000 0x0 0x10000>;
1126 +               interrupts = <0 136 0x4>; /* Level high type */
1127 +               clocks = <&clockgen 4 3>;
1128 +       };
1129 +
1130 +       usb0: usb3@3100000 {
1131 +               status = "disabled";
1132 +               compatible = "snps,dwc3";
1133 +               reg = <0x0 0x3100000 0x0 0x10000>;
1134 +               interrupts = <0 80 0x4>; /* Level high type */
1135 +               dr_mode = "host";
1136 +               configure-gfladj;
1137 +               snps,dis_rxdet_inp3_quirk;
1138 +       };
1139 +
1140 +       usb1: usb3@3110000 {
1141 +               status = "disabled";
1142 +               compatible = "snps,dwc3";
1143 +               reg = <0x0 0x3110000 0x0 0x10000>;
1144 +               interrupts = <0 81 0x4>; /* Level high type */
1145 +               dr_mode = "host";
1146 +               configure-gfladj;
1147 +               snps,dis_rxdet_inp3_quirk;
1148 +       };
1149 +
1150 +       smmu: iommu@5000000 {
1151 +               compatible = "arm,mmu-500";
1152 +               reg = <0 0x5000000 0 0x800000>;
1153 +               #global-interrupts = <12>;
1154 +               interrupts = <0 13 4>, /* global secure fault */
1155 +                            <0 14 4>, /* combined secure interrupt */
1156 +                            <0 15 4>, /* global non-secure fault */
1157 +                            <0 16 4>, /* combined non-secure interrupt */
1158 +                       /* performance counter interrupts 0-7 */
1159 +                            <0 211 4>,
1160 +                            <0 212 4>,
1161 +                            <0 213 4>,
1162 +                            <0 214 4>,
1163 +                            <0 215 4>,
1164 +                            <0 216 4>,
1165 +                            <0 217 4>,
1166 +                            <0 218 4>,
1167 +                       /* per context interrupt, 64 interrupts */
1168 +                            <0 146 4>,
1169 +                            <0 147 4>,
1170 +                            <0 148 4>,
1171 +                            <0 149 4>,
1172 +                            <0 150 4>,
1173 +                            <0 151 4>,
1174 +                            <0 152 4>,
1175 +                            <0 153 4>,
1176 +                            <0 154 4>,
1177 +                            <0 155 4>,
1178 +                            <0 156 4>,
1179 +                            <0 157 4>,
1180 +                            <0 158 4>,
1181 +                            <0 159 4>,
1182 +                            <0 160 4>,
1183 +                            <0 161 4>,
1184 +                            <0 162 4>,
1185 +                            <0 163 4>,
1186 +                            <0 164 4>,
1187 +                            <0 165 4>,
1188 +                            <0 166 4>,
1189 +                            <0 167 4>,
1190 +                            <0 168 4>,
1191 +                            <0 169 4>,
1192 +                            <0 170 4>,
1193 +                            <0 171 4>,
1194 +                            <0 172 4>,
1195 +                            <0 173 4>,
1196 +                            <0 174 4>,
1197 +                            <0 175 4>,
1198 +                            <0 176 4>,
1199 +                            <0 177 4>,
1200 +                            <0 178 4>,
1201 +                            <0 179 4>,
1202 +                            <0 180 4>,
1203 +                            <0 181 4>,
1204 +                            <0 182 4>,
1205 +                            <0 183 4>,
1206 +                            <0 184 4>,
1207 +                            <0 185 4>,
1208 +                            <0 186 4>,
1209 +                            <0 187 4>,
1210 +                            <0 188 4>,
1211 +                            <0 189 4>,
1212 +                            <0 190 4>,
1213 +                            <0 191 4>,
1214 +                            <0 192 4>,
1215 +                            <0 193 4>,
1216 +                            <0 194 4>,
1217 +                            <0 195 4>,
1218 +                            <0 196 4>,
1219 +                            <0 197 4>,
1220 +                            <0 198 4>,
1221 +                            <0 199 4>,
1222 +                            <0 200 4>,
1223 +                            <0 201 4>,
1224 +                            <0 202 4>,
1225 +                            <0 203 4>,
1226 +                            <0 204 4>,
1227 +                            <0 205 4>,
1228 +                            <0 206 4>,
1229 +                            <0 207 4>,
1230 +                            <0 208 4>,
1231 +                            <0 209 4>;
1232 +               mmu-masters = <&fsl_mc 0x300 0>;
1233 +       };
1234 +
1235 +       timer {
1236 +               compatible = "arm,armv8-timer";
1237 +               interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */
1238 +                            <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */
1239 +                            <1 11 0x1>, /* Virtual PPI, edge triggered */
1240 +                            <1 10 0x1>; /* Hypervisor PPI, edge triggered */
1241 +               arm,reread-timer;
1242 +               fsl,erratum-a008585;
1243 +       };
1244 +
1245 +       fsl_mc: fsl-mc@80c000000 {
1246 +               compatible = "fsl,qoriq-mc";
1247 +               #stream-id-cells = <2>;
1248 +               reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
1249 +                     <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
1250 +               msi-parent = <&its>;
1251 +               #address-cells = <3>;
1252 +               #size-cells = <1>;
1253 +
1254 +               /*
1255 +                * Region type 0x0 - MC portals
1256 +                * Region type 0x1 - QBMAN portals
1257 +                */
1258 +               ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1259 +                         0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1260 +
1261 +               /*
1262 +                * Define the maximum number of MACs present on the SoC.
1263 +                * They won't necessarily be all probed, since the
1264 +                * Data Path Layout file and the MC firmware can put fewer
1265 +                * actual DPMAC objects on the MC bus.
1266 +                */
1267 +               dpmacs {
1268 +                       #address-cells = <1>;
1269 +                       #size-cells = <0>;
1270 +
1271 +                       dpmac1: dpmac@1 {
1272 +                               compatible = "fsl,qoriq-mc-dpmac";
1273 +                               reg = <1>;
1274 +                       };
1275 +                       dpmac2: dpmac@2 {
1276 +                               compatible = "fsl,qoriq-mc-dpmac";
1277 +                               reg = <2>;
1278 +                       };
1279 +                       dpmac3: dpmac@3 {
1280 +                               compatible = "fsl,qoriq-mc-dpmac";
1281 +                               reg = <3>;
1282 +                       };
1283 +                       dpmac4: dpmac@4 {
1284 +                               compatible = "fsl,qoriq-mc-dpmac";
1285 +                               reg = <4>;
1286 +                       };
1287 +                       dpmac5: dpmac@5 {
1288 +                               compatible = "fsl,qoriq-mc-dpmac";
1289 +                               reg = <5>;
1290 +                       };
1291 +                       dpmac6: dpmac@6 {
1292 +                               compatible = "fsl,qoriq-mc-dpmac";
1293 +                               reg = <6>;
1294 +                       };
1295 +                       dpmac7: dpmac@7 {
1296 +                               compatible = "fsl,qoriq-mc-dpmac";
1297 +                               reg = <7>;
1298 +                       };
1299 +                       dpmac8: dpmac@8 {
1300 +                               compatible = "fsl,qoriq-mc-dpmac";
1301 +                               reg = <8>;
1302 +                       };
1303 +                       dpmac9: dpmac@9 {
1304 +                               compatible = "fsl,qoriq-mc-dpmac";
1305 +                               reg = <9>;
1306 +                       };
1307 +                       dpmac10: dpmac@10 {
1308 +                               compatible = "fsl,qoriq-mc-dpmac";
1309 +                               reg = <0xa>;
1310 +                       };
1311 +                       dpmac11: dpmac@11 {
1312 +                               compatible = "fsl,qoriq-mc-dpmac";
1313 +                               reg = <0xb>;
1314 +                       };
1315 +                       dpmac12: dpmac@12 {
1316 +                               compatible = "fsl,qoriq-mc-dpmac";
1317 +                               reg = <0xc>;
1318 +                       };
1319 +                       dpmac13: dpmac@13 {
1320 +                               compatible = "fsl,qoriq-mc-dpmac";
1321 +                               reg = <0xd>;
1322 +                       };
1323 +                       dpmac14: dpmac@14 {
1324 +                               compatible = "fsl,qoriq-mc-dpmac";
1325 +                               reg = <0xe>;
1326 +                       };
1327 +                       dpmac15: dpmac@15 {
1328 +                               compatible = "fsl,qoriq-mc-dpmac";
1329 +                               reg = <0xf>;
1330 +                       };
1331 +                       dpmac16: dpmac@16 {
1332 +                               compatible = "fsl,qoriq-mc-dpmac";
1333 +                               reg = <0x10>;
1334 +                       };
1335 +               };
1336 +       };
1337 +
1338 +       ccn@4000000 {
1339 +               compatible = "arm,ccn-504";
1340 +               reg = <0x0 0x04000000 0x0 0x01000000>;
1341 +               interrupts = <0 12 4>;
1342 +       };
1343 +
1344 +       memory@80000000 {
1345 +               device_type = "memory";
1346 +               reg = <0x00000000 0x80000000 0 0x80000000>;
1347 +                     /* DRAM space 1 - 2 GB DRAM */
1348 +       };
1349 +};
1350 --
1351 1.7.9.5
1352