target/linux/layerscape/patches-4.4/3132-dts-ls1046a-add-LS1046ARDB-board-support.patch

   1 From feb12cb699adbac2d4619401c7ff4fcc2fc97b6c Mon Sep 17 00:00:00 2001
   2 From: Mingkai Hu <mingkai.hu@nxp.com>
   3 Date: Mon, 26 Sep 2016 12:33:42 +0800
   4 Subject: [PATCH 132/141] dts/ls1046a: add LS1046ARDB board support
   5
   6 commit e95a28cfd9a392fe5dc189a9ae097bbaaccd1228
   7 [context adjustment]
   8
   9 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
  10 Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
  11 ---
  12  arch/arm64/boot/dts/freescale/Makefile            |    1 +
  13  arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts |  198 +++++++++++++++++++++
  14  arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi    |  178 +++++++++++++-----
  15  3 files changed, 328 insertions(+), 49 deletions(-)
  16  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
  17
  18 --- a/arch/arm64/boot/dts/freescale/Makefile
  19 +++ b/arch/arm64/boot/dts/freescale/Makefile
  20 @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
  21  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
  22  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
  23  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
  24 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
  25
  26  always         := $(dtb-y)
  27  subdir-y       := $(dts-dirs)
  28 --- /dev/null
  29 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
  30 @@ -0,0 +1,198 @@
  31 +/*
  32 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  33 + *
  34 + * Copyright 2016, Freescale Semiconductor
  35 + *
  36 + * Mingkai Hu <mingkai.hu@nxp.com>
  37 + *
  38 + * This file is dual-licensed: you can use it either under the terms
  39 + * of the GPLv2 or the X11 license, at your option. Note that this dual
  40 + * licensing only applies to this file, and not this project as a
  41 + * whole.
  42 + *
  43 + *  a) This library is free software; you can redistribute it and/or
  44 + *     modify it under the terms of the GNU General Public License as
  45 + *     published by the Free Software Foundation; either version 2 of the
  46 + *     License, or (at your option) any later version.
  47 + *
  48 + *     This library is distributed in the hope that it will be useful,
  49 + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  50 + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  51 + *     GNU General Public License for more details.
  52 + *
  53 + * Or, alternatively,
  54 + *
  55 + *  b) Permission is hereby granted, free of charge, to any person
  56 + *     obtaining a copy of this software and associated documentation
  57 + *     files (the "Software"), to deal in the Software without
  58 + *     restriction, including without limitation the rights to use,
  59 + *     copy, modify, merge, publish, distribute, sublicense, and/or
  60 + *     sell copies of the Software, and to permit persons to whom the
  61 + *     Software is furnished to do so, subject to the following
  62 + *     conditions:
  63 + *
  64 + *     The above copyright notice and this permission notice shall be
  65 + *     included in all copies or substantial portions of the Software.
  66 + *
  67 + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  68 + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  69 + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  70 + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  71 + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  72 + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  73 + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  74 + *     OTHER DEALINGS IN THE SOFTWARE.
  75 + */
  76 +
  77 +/dts-v1/;
  78 +#include "fsl-ls1046a.dtsi"
  79 +
  80 +/ {
  81 +       model = "LS1046A RDB Board";
  82 +       compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
  83 +
  84 +       aliases {
  85 +               ethernet0 = &fm1mac3;
  86 +               ethernet1 = &fm1mac4;
  87 +               ethernet2 = &fm1mac5;
  88 +               ethernet3 = &fm1mac6;
  89 +               ethernet4 = &fm1mac9;
  90 +               ethernet5 = &fm1mac10;
  91 +       };
  92 +};
  93 +
  94 +&i2c0 {
  95 +       status = "okay";
  96 +       ina220@40 {
  97 +               compatible = "ti,ina220";
  98 +               reg = <0x40>;
  99 +               shunt-resistor = <1000>;
 100 +       };
 101 +       adt7461a@4c {
 102 +               compatible = "adi,adt7461";
 103 +               reg = <0x4c>;
 104 +       };
 105 +       eeprom@56 {
 106 +               compatible = "at24,24c512";
 107 +               reg = <0x52>;
 108 +       };
 109 +       eeprom@57 {
 110 +               compatible = "at24,24c512";
 111 +               reg = <0x53>;
 112 +       };
 113 +};
 114 +
 115 +&i2c3 {
 116 +       status = "okay";
 117 +       rtc@51 {
 118 +               compatible = "nxp,pcf2129";
 119 +               reg = <0x51>;
 120 +       };
 121 +};
 122 +
 123 +&ifc {
 124 +       status = "okay";
 125 +       #address-cells = <2>;
 126 +       #size-cells = <1>;
 127 +       /* NAND Flashe and CPLD on board */
 128 +       ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
 129 +                 0x2 0x0 0x0 0x7fb00000 0x00000100>;
 130 +
 131 +               nand@0,0 {
 132 +                       compatible = "fsl,ifc-nand";
 133 +                       #address-cells = <1>;
 134 +                       #size-cells = <1>;
 135 +                       reg = <0x0 0x0 0x10000>;
 136 +               };
 137 +
 138 +               cpld: board-control@2,0 {
 139 +                       compatible = "fsl,ls1046ardb-cpld";
 140 +                       reg = <0x2 0x0 0x0000100>;
 141 +               };
 142 +};
 143 +
 144 +&qspi {
 145 +       num-cs = <2>;
 146 +       bus-num = <0>;
 147 +       status = "okay";
 148 +
 149 +       qflash0: s25fs128s@0 {
 150 +               compatible = "spansion,m25p80";
 151 +               #address-cells = <1>;
 152 +               #size-cells = <1>;
 153 +               spi-max-frequency = <20000000>;
 154 +               reg = <0>;
 155 +       };
 156 +
 157 +       qflash1: s25fs128s@1 {
 158 +               compatible = "spansion,m25p80";
 159 +               #address-cells = <1>;
 160 +               #size-cells = <1>;
 161 +               spi-max-frequency = <20000000>;
 162 +               reg = <1>;
 163 +       };
 164 +
 165 +};
 166 +
 167 +&duart0 {
 168 +       status = "okay";
 169 +};
 170 +
 171 +&duart1 {
 172 +       status = "okay";
 173 +};
 174 +
 175 +&fman0 {
 176 +       ethernet@e4000 {
 177 +               phy-handle = <&rgmii_phy1>;
 178 +               phy-connection-type = "rgmii";
 179 +       };
 180 +
 181 +       ethernet@e6000 {
 182 +               phy-handle = <&rgmii_phy2>;
 183 +               phy-connection-type = "rgmii";
 184 +       };
 185 +
 186 +       ethernet@e8000 {
 187 +               phy-handle = <&sgmii_phy1>;
 188 +               phy-connection-type = "sgmii";
 189 +       };
 190 +
 191 +       ethernet@ea000 {
 192 +               phy-handle = <&sgmii_phy2>;
 193 +               phy-connection-type = "sgmii";
 194 +       };
 195 +
 196 +       ethernet@f0000 { /* 10GEC1 */
 197 +               phy-handle = <&aqr106_phy>;
 198 +               phy-connection-type = "xgmii";
 199 +       };
 200 +
 201 +       ethernet@f2000 { /* 10GEC2 */
 202 +               fixed-link = <0 1 10000 0 0>;
 203 +               phy-connection-type = "xgmii";
 204 +       };
 205 +
 206 +       mdio@fc000 {
 207 +               rgmii_phy1: ethernet-phy@1 {
 208 +                       reg = <0x1>;
 209 +               };
 210 +               rgmii_phy2: ethernet-phy@2 {
 211 +                       reg = <0x2>;
 212 +               };
 213 +               sgmii_phy1: ethernet-phy@3 {
 214 +                       reg = <0x3>;
 215 +               };
 216 +               sgmii_phy2: ethernet-phy@4 {
 217 +                       reg = <0x4>;
 218 +               };
 219 +       };
 220 +
 221 +       mdio@fd000 {
 222 +               aqr106_phy: ethernet-phy@1 {
 223 +                       compatible = "ethernet-phy-ieee802.3-c45";
 224 +                       interrupts = <0 131 4>;
 225 +                       reg = <0x0>;
 226 +               };
 227 +       };
 228 +};
 229 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
 230 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
 231 @@ -51,13 +51,7 @@
 232         #size-cells = <2>;
 233
 234         aliases {
 235 -               ethernet0 = &fm1mac1;
 236 -               ethernet1 = &fm1mac2;
 237 -               ethernet2 = &fm1mac3;
 238 -               ethernet3 = &fm1mac4;
 239 -               ethernet4 = &fm1mac5;
 240 -               ethernet5 = &fm1mac6;
 241 -               ethernet6 = &fm1mac9;
 242 +               crypto = &crypto;
 243         };
 244
 245         cpus {
 246 @@ -70,6 +64,7 @@
 247                         reg = <0x0>;
 248                         clocks = <&clockgen 1 0>;
 249                         next-level-cache = <&l2>;
 250 +                       cpu-idle-states = <&CPU_PH20>;
 251                 };
 252
 253                 cpu1: cpu@1 {
 254 @@ -78,6 +73,7 @@
 255                         reg = <0x1>;
 256                         clocks = <&clockgen 1 0>;
 257                         next-level-cache = <&l2>;
 258 +                       cpu-idle-states = <&CPU_PH20>;
 259                 };
 260
 261                 cpu2: cpu@2 {
 262 @@ -86,6 +82,7 @@
 263                         reg = <0x2>;
 264                         clocks = <&clockgen 1 0>;
 265                         next-level-cache = <&l2>;
 266 +                       cpu-idle-states = <&CPU_PH20>;
 267                 };
 268
 269                 cpu3: cpu@3 {
 270 @@ -94,6 +91,7 @@
 271                         reg = <0x3>;
 272                         clocks = <&clockgen 1 0>;
 273                         next-level-cache = <&l2>;
 274 +                       cpu-idle-states = <&CPU_PH20>;
 275                 };
 276
 277                 l2: l2-cache {
 278 @@ -101,6 +99,19 @@
 279                 };
 280         };
 281
 282 +       idle-states {
 283 +               entry-method = "arm,psci";
 284 +
 285 +               CPU_PH20: cpu-ph20 {
 286 +                       compatible = "arm,idle-state";
 287 +                       idle-state-name = "PH20";
 288 +                       arm,psci-suspend-param = <0x00010000>;
 289 +                       entry-latency-us = <1000>;
 290 +                       exit-latency-us = <1000>;
 291 +                       min-residency-us = <3000>;
 292 +               };
 293 +       };
 294 +
 295         memory@80000000 {
 296                 device_type = "memory";
 297                 reg = <0x0 0x80000000 0 0x80000000>;
 298 @@ -193,6 +204,49 @@
 299                         bus-width = <4>;
 300                 };
 301
 302 +               crypto: crypto@1700000 {
 303 +                       compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 304 +                                    "fsl,sec-v4.0";
 305 +                       fsl,sec-era = <8>;
 306 +                       #address-cells = <1>;
 307 +                       #size-cells = <1>;
 308 +                       ranges = <0x0 0x00 0x1700000 0x100000>;
 309 +                       reg = <0x00 0x1700000 0x0 0x100000>;
 310 +                       interrupts = <0 75 0x4>;
 311 +
 312 +                       sec_jr0: jr@10000 {
 313 +                               compatible = "fsl,sec-v5.4-job-ring",
 314 +                                            "fsl,sec-v5.0-job-ring",
 315 +                                            "fsl,sec-v4.0-job-ring";
 316 +                               reg        = <0x10000 0x10000>;
 317 +                               interrupts = <0 71 0x4>;
 318 +                       };
 319 +
 320 +                       sec_jr1: jr@20000 {
 321 +                               compatible = "fsl,sec-v5.4-job-ring",
 322 +                                            "fsl,sec-v5.0-job-ring",
 323 +                                            "fsl,sec-v4.0-job-ring";
 324 +                               reg        = <0x20000 0x10000>;
 325 +                               interrupts = <0 72 0x4>;
 326 +                       };
 327 +
 328 +                       sec_jr2: jr@30000 {
 329 +                               compatible = "fsl,sec-v5.4-job-ring",
 330 +                                            "fsl,sec-v5.0-job-ring",
 331 +                                            "fsl,sec-v4.0-job-ring";
 332 +                               reg        = <0x30000 0x10000>;
 333 +                               interrupts = <0 73 0x4>;
 334 +                       };
 335 +
 336 +                       sec_jr3: jr@40000 {
 337 +                               compatible = "fsl,sec-v5.4-job-ring",
 338 +                                            "fsl,sec-v5.0-job-ring",
 339 +                                            "fsl,sec-v4.0-job-ring";
 340 +                               reg        = <0x40000 0x10000>;
 341 +                               interrupts = <0 74 0x4>;
 342 +                       };
 343 +               };
 344 +
 345                 qman: qman@1880000 {
 346                         compatible = "fsl,qman";
 347                         reg = <0x00 0x1880000 0x0 0x10000>;
 348 @@ -490,6 +544,19 @@
 349                                 fsl,qman-channel-id = <0x800>;
 350                         };
 351
 352 +                       fman0_10g_rx1: port@91000 {
 353 +                               cell-index = <1>;
 354 +                               compatible = "fsl,fman-port-10g-rx";
 355 +                               reg = <0x91000 0x1000>;
 356 +                       };
 357 +
 358 +                       fman0_10g_tx1: port@b1000 {
 359 +                               cell-index = <1>;
 360 +                               compatible = "fsl,fman-port-10g-tx";
 361 +                               reg = <0xb1000 0x1000>;
 362 +                               fsl,qman-channel-id = <0x801>;
 363 +                       };
 364 +
 365                         fm1mac9: ethernet@f0000 {
 366                                 cell-index = <0>;
 367                                 compatible = "fsl,fman-memac";
 368 @@ -497,6 +564,13 @@
 369                                 fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>;
 370                         };
 371
 372 +                       fm1mac10: ethernet@f2000 {
 373 +                               cell-index = <1>;
 374 +                               compatible = "fsl,fman-memac";
 375 +                               reg = <0xf2000 0x1000>;
 376 +                               fsl,port-handles = <&fman0_10g_rx1 &fman0_10g_tx1>;
 377 +                       };
 378 +
 379                         mdio@f1000 {
 380                                 #address-cells = <1>;
 381                                 #size-cells = <0>;
 382 @@ -504,6 +578,13 @@
 383                                 reg = <0xf1000 0x1000>;
 384                         };
 385
 386 +                       mdio@f3000 {
 387 +                               #address-cells = <1>;
 388 +                               #size-cells = <0>;
 389 +                               compatible = "fsl,fman-memac-mdio";
 390 +                               reg = <0xf3000 0x1000>;
 391 +                       };
 392 +
 393                         ptp_timer0: rtc@fe000 {
 394                                 compatible = "fsl,fman-rtc";
 395                                 reg = <0xfe000 0x1000>;
 396 @@ -657,7 +738,7 @@
 397                         compatible = "fsl,ls1021a-lpuart";
 398                         reg = <0x0 0x2950000 0x0 0x1000>;
 399                         interrupts = <0 48 0x4>;
 400 -                       clocks = <&clockgen 0 0>;
 401 +                       clocks = <&clockgen 4 0>;
 402                         clock-names = "ipg";
 403                         status = "disabled";
 404                 };
 405 @@ -712,7 +793,7 @@
 406                         reg = <0x0 0x29d0000 0x0 0x10000>;
 407                         interrupts = <0 86 0x4>;
 408                         big-endian;
 409 -                       rcpm-wakeup = <&rcpm 0x0 0x20000000>;
 410 +                       rcpm-wakeup = <&rcpm 0x00020000 0x0>;
 411                         status = "okay";
 412                 };
 413
 414 @@ -789,34 +870,34 @@
 415                         big-endian;
 416                 };
 417
 418 -               msi1: msi-controller@1580000 {
 419 -                       compatible = "fsl,1s1046a-msi";
 420 -                       reg = <0x0 0x1580000 0x0 0x10000>;
 421 +               msi: msi-controller@1580000 {
 422 +                       compatible = "fsl,ls1046a-msi";
 423 +                       #address-cells = <2>;
 424 +                       #size-cells = <2>;
 425 +                       ranges;
 426                         msi-controller;
 427 -                       interrupts = <0 116 0x4>,
 428 -                                    <0 111 0x4>,
 429 -                                    <0 112 0x4>,
 430 -                                    <0 113 0x4>;
 431 -               };
 432
 433 -               msi2: msi-controller@1590000 {
 434 -                       compatible = "fsl,1s1046a-msi";
 435 -                       reg = <0x0 0x1590000 0x0 0x10000>;
 436 -                       msi-controller;
 437 -                       interrupts = <0 126 0x4>,
 438 -                                    <0 121 0x4>,
 439 -                                    <0 122 0x4>,
 440 -                                    <0 123 0x4>;
 441 -               };
 442 -
 443 -               msi3: msi-controller@15a0000 {
 444 -                       compatible = "fsl,1s1046a-msi";
 445 -                       reg = <0x0 0x15a0000 0x0 0x10000>;
 446 -                       msi-controller;
 447 -                       interrupts = <0 160 0x4>,
 448 -                                    <0 155 0x4>,
 449 -                                    <0 156 0x4>,
 450 -                                    <0 157 0x4>;
 451 +                       msi-bank@1580000 {
 452 +                               reg = <0x0 0x1580000 0x0 0x10000>;
 453 +                               interrupts = <0 116 0x4>,
 454 +                                            <0 111 0x4>,
 455 +                                            <0 112 0x4>,
 456 +                                            <0 113 0x4>;
 457 +                       };
 458 +                       msi-bank@1590000 {
 459 +                               reg = <0x0 0x1590000 0x0 0x10000>;
 460 +                               interrupts = <0 126 0x4>,
 461 +                                            <0 121 0x4>,
 462 +                                            <0 122 0x4>,
 463 +                                            <0 123 0x4>;
 464 +                       };
 465 +                       msi-bank@15a0000 {
 466 +                               reg = <0x0 0x15a0000 0x0 0x10000>;
 467 +                               interrupts = <0 160 0x4>,
 468 +                                            <0 155 0x4>,
 469 +                                            <0 156 0x4>,
 470 +                                            <0 157 0x4>;
 471 +                       };
 472                 };
 473
 474                 pcie@3400000 {
 475 @@ -826,15 +907,16 @@
 476                         reg-names = "regs", "config";
 477                         interrupts = <0 118 0x4>, /* controller interrupt */
 478                                      <0 117 0x4>; /* PME interrupt */
 479 -                       interrupt-names = "intr", "pme";
 480 +                       interrupt-names = "aer";
 481                         #address-cells = <3>;
 482                         #size-cells = <2>;
 483                         device_type = "pci";
 484 +                       dma-coherent;
 485                         num-lanes = <4>;
 486                         bus-range = <0x0 0xff>;
 487                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 488                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 489 -                       msi-parent = <&msi1>;
 490 +                       msi-parent = <&msi>;
 491                         #interrupt-cells = <1>;
 492                         interrupt-map-mask = <0 0 0 7>;
 493                         interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
 494 @@ -850,15 +932,16 @@
 495                         reg-names = "regs", "config";
 496                         interrupts = <0 128 0x4>,
 497                                      <0 127 0x4>;
 498 -                       interrupt-names = "intr", "pme";
 499 +                       interrupt-names = "aer";
 500                         #address-cells = <3>;
 501                         #size-cells = <2>;
 502                         device_type = "pci";
 503 +                       dma-coherent;
 504                         num-lanes = <2>;
 505                         bus-range = <0x0 0xff>;
 506                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 507                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 508 -                       msi-parent = <&msi2>;
 509 +                       msi-parent = <&msi>;
 510                         #interrupt-cells = <1>;
 511                         interrupt-map-mask = <0 0 0 7>;
 512                         interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
 513 @@ -874,15 +957,16 @@
 514                         reg-names = "regs", "config";
 515                         interrupts = <0 162 0x4>,
 516                                      <0 161 0x4>;
 517 -                       interrupt-names = "intr", "pme";
 518 +                       interrupt-names = "aer";
 519                         #address-cells = <3>;
 520                         #size-cells = <2>;
 521                         device_type = "pci";
 522 +                       dma-coherent;
 523                         num-lanes = <2>;
 524                         bus-range = <0x0 0xff>;
 525                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 526                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 527 -                       msi-parent = <&msi3>;
 528 +                       msi-parent = <&msi>;
 529                         #interrupt-cells = <1>;
 530                         interrupt-map-mask = <0 0 0 7>;
 531                         interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
 532 @@ -894,14 +978,6 @@
 533
 534         fsl,dpaa {
 535                 compatible = "fsl,ls1046a-dpaa", "simple-bus", "fsl,dpaa";
 536 -               ethernet@0 {
 537 -                       compatible = "fsl,dpa-ethernet";
 538 -                       fsl,fman-mac = <&fm1mac1>;
 539 -               };
 540 -               ethernet@1 {
 541 -                       compatible = "fsl,dpa-ethernet";
 542 -                       fsl,fman-mac = <&fm1mac2>;
 543 -               };
 544                 ethernet@2 {
 545                         compatible = "fsl,dpa-ethernet";
 546                         fsl,fman-mac = <&fm1mac3>;
 547 @@ -922,6 +998,10 @@
 548                         compatible = "fsl,dpa-ethernet";
 549                         fsl,fman-mac = <&fm1mac9>;
 550                 };
 551 +               ethernet@9 {
 552 +                       compatible = "fsl,dpa-ethernet";
 553 +                       fsl,fman-mac = <&fm1mac10>;
 554 +               };
 555         };
 556
 557         qportals: qman-portals@500000000 {