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layerscape: add 64b/32b target for ls1046ardb device
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.4 / 3131-arm64-ls1046a-add-DTS-for-Freescale-LS1046A-SoC.patch
1 From 80ca93f1a5590529e39560099a71edb03897050e Mon Sep 17 00:00:00 2001
2 From: Mingkai Hu <mingkai.hu@nxp.com>
3 Date: Wed, 11 May 2016 11:29:51 +0800
4 Subject: [PATCH 131/141] arm64/ls1046a: add DTS for Freescale LS1046A SoC
5
6 LS1046a is an SoC with 4 ARMv8 A72 cores and most other IP blocks
7 similar to LS1043a which complies to Chassis 2.1 spec.
8
9 Following levels of DTSI/DTS files have been created for the
10 LS1046A SoC family:
11
12 - fsl-ls1046a.dtsi:
13 DTS-Include file for FSL LS1046A SoC.
14
15 Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
18 Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
19 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
20 ---
21 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1029 ++++++++++++++++++++++++
22 1 file changed, 1029 insertions(+)
23 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
24
25 --- /dev/null
26 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
27 @@ -0,0 +1,1029 @@
28 +/*
29 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
30 + *
31 + * Copyright 2016, Freescale Semiconductor
32 + *
33 + * Mingkai Hu <mingkai.hu@nxp.com>
34 + *
35 + * This file is dual-licensed: you can use it either under the terms
36 + * of the GPLv2 or the X11 license, at your option. Note that this dual
37 + * licensing only applies to this file, and not this project as a
38 + * whole.
39 + *
40 + * a) This library is free software; you can redistribute it and/or
41 + * modify it under the terms of the GNU General Public License as
42 + * published by the Free Software Foundation; either version 2 of the
43 + * License, or (at your option) any later version.
44 + *
45 + * This library is distributed in the hope that it will be useful,
46 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
47 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48 + * GNU General Public License for more details.
49 + *
50 + * Or, alternatively,
51 + *
52 + * b) Permission is hereby granted, free of charge, to any person
53 + * obtaining a copy of this software and associated documentation
54 + * files (the "Software"), to deal in the Software without
55 + * restriction, including without limitation the rights to use,
56 + * copy, modify, merge, publish, distribute, sublicense, and/or
57 + * sell copies of the Software, and to permit persons to whom the
58 + * Software is furnished to do so, subject to the following
59 + * conditions:
60 + *
61 + * The above copyright notice and this permission notice shall be
62 + * included in all copies or substantial portions of the Software.
63 + *
64 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
65 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
66 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
67 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
68 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
69 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
70 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
71 + * OTHER DEALINGS IN THE SOFTWARE.
72 + */
73 +
74 +/ {
75 + compatible = "fsl,ls1046a";
76 + interrupt-parent = <&gic>;
77 + #address-cells = <2>;
78 + #size-cells = <2>;
79 +
80 + aliases {
81 + ethernet0 = &fm1mac1;
82 + ethernet1 = &fm1mac2;
83 + ethernet2 = &fm1mac3;
84 + ethernet3 = &fm1mac4;
85 + ethernet4 = &fm1mac5;
86 + ethernet5 = &fm1mac6;
87 + ethernet6 = &fm1mac9;
88 + };
89 +
90 + cpus {
91 + #address-cells = <1>;
92 + #size-cells = <0>;
93 +
94 + cpu0: cpu@0 {
95 + device_type = "cpu";
96 + compatible = "arm,cortex-a72";
97 + reg = <0x0>;
98 + clocks = <&clockgen 1 0>;
99 + next-level-cache = <&l2>;
100 + };
101 +
102 + cpu1: cpu@1 {
103 + device_type = "cpu";
104 + compatible = "arm,cortex-a72";
105 + reg = <0x1>;
106 + clocks = <&clockgen 1 0>;
107 + next-level-cache = <&l2>;
108 + };
109 +
110 + cpu2: cpu@2 {
111 + device_type = "cpu";
112 + compatible = "arm,cortex-a72";
113 + reg = <0x2>;
114 + clocks = <&clockgen 1 0>;
115 + next-level-cache = <&l2>;
116 + };
117 +
118 + cpu3: cpu@3 {
119 + device_type = "cpu";
120 + compatible = "arm,cortex-a72";
121 + reg = <0x3>;
122 + clocks = <&clockgen 1 0>;
123 + next-level-cache = <&l2>;
124 + };
125 +
126 + l2: l2-cache {
127 + compatible = "cache";
128 + };
129 + };
130 +
131 + memory@80000000 {
132 + device_type = "memory";
133 + reg = <0x0 0x80000000 0 0x80000000>;
134 + /* DRAM space 1, size: 2GiB DRAM */
135 + };
136 +
137 + sysclk: sysclk {
138 + compatible = "fixed-clock";
139 + #clock-cells = <0>;
140 + clock-frequency = <100000000>;
141 + clock-output-names = "sysclk";
142 + };
143 +
144 + timer {
145 + compatible = "arm,armv8-timer";
146 + interrupts = <1 13 0x1>, /* Physical Secure PPI */
147 + <1 14 0x1>, /* Physical Non-Secure PPI */
148 + <1 11 0x1>, /* Virtual PPI */
149 + <1 10 0x1>; /* Hypervisor PPI */
150 + arm,reread-timer;
151 + };
152 +
153 + pmu {
154 + compatible = "arm,armv8-pmuv3";
155 + interrupts = <0 106 0x4>,
156 + <0 107 0x4>,
157 + <0 95 0x4>,
158 + <0 97 0x4>;
159 + interrupt-affinity = <&cpu0>,
160 + <&cpu1>,
161 + <&cpu2>,
162 + <&cpu3>;
163 + };
164 +
165 + gic: interrupt-controller@1400000 {
166 + compatible = "arm,gic-400";
167 + #interrupt-cells = <3>;
168 + interrupt-controller;
169 + reg = <0x0 0x1410000 0 0x10000>, /* GICD */
170 + <0x0 0x1420000 0 0x20000>, /* GICC */
171 + <0x0 0x1440000 0 0x20000>, /* GICH */
172 + <0x0 0x1460000 0 0x20000>; /* GICV */
173 + interrupts = <1 9 0xf08>;
174 + };
175 +
176 + soc {
177 + compatible = "simple-bus";
178 + #address-cells = <2>;
179 + #size-cells = <2>;
180 + ranges;
181 +
182 + clockgen: clocking@1ee1000 {
183 + compatible = "fsl,ls1046a-clockgen";
184 + reg = <0x0 0x1ee1000 0x0 0x1000>;
185 + #clock-cells = <2>;
186 + clocks = <&sysclk>;
187 + };
188 +
189 + scfg: scfg@1570000 {
190 + compatible = "fsl,ls1046a-scfg", "syscon";
191 + reg = <0x0 0x1570000 0x0 0x10000>;
192 + big-endian;
193 + };
194 +
195 + reset: reset@1ee00b0 {
196 + compatible = "fsl,ls-reset";
197 + reg = <0x0 0x1ee00b0 0x0 0x4>;
198 + big-endian;
199 + };
200 +
201 + rcpm: rcpm@1ee2000 {
202 + compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1";
203 + reg = <0x0 0x1ee2000 0x0 0x10000>;
204 + };
205 +
206 + ifc: ifc@1530000 {
207 + compatible = "fsl,ifc", "simple-bus";
208 + reg = <0x0 0x1530000 0x0 0x10000>;
209 + interrupts = <0 43 0x4>;
210 + };
211 +
212 + esdhc: esdhc@1560000 {
213 + compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
214 + reg = <0x0 0x1560000 0x0 0x10000>;
215 + interrupts = <0 62 0x4>;
216 + clock-frequency = <0>;
217 + voltage-ranges = <1800 1800 3300 3300>;
218 + sdhci,auto-cmd12;
219 + big-endian;
220 + bus-width = <4>;
221 + };
222 +
223 + qman: qman@1880000 {
224 + compatible = "fsl,qman";
225 + reg = <0x00 0x1880000 0x0 0x10000>;
226 + interrupts = <0 45 0x4>;
227 + };
228 +
229 + bman: bman@1890000 {
230 + compatible = "fsl,bman";
231 + reg = <0x00 0x1890000 0x0 0x10000>;
232 + interrupts = <0 45 0x4>;
233 + };
234 +
235 + fman0: fman@1a00000 {
236 + #address-cells = <1>;
237 + #size-cells = <1>;
238 + cell-index = <0>;
239 + compatible = "fsl,fman", "simple-bus";
240 + ranges = <0x0 0x00 0x1a00000 0x100000>;
241 + reg = <0x00 0x1a00000 0x0 0x100000>;
242 + interrupts = <0 44 0x4>, <0 45 0x4>;
243 + clocks = <&clockgen 3 0>;
244 + clock-names = "fmanclk";
245 +
246 + cc {
247 + compatible = "fsl,fman-cc";
248 + };
249 +
250 + muram@0 {
251 + compatible = "fsl,fman-muram";
252 + reg = <0x0 0x60000>;
253 + };
254 +
255 + bmi@80000 {
256 + compatible = "fsl,fman-bmi";
257 + reg = <0x80000 0x400>;
258 + };
259 +
260 + qmi@80400 {
261 + compatible = "fsl,fman-qmi";
262 + reg = <0x80400 0x400>;
263 + };
264 +
265 + fman0_oh1: port@82000 {
266 + cell-index = <0>;
267 + compatible = "fsl,fman-port-oh";
268 + reg = <0x82000 0x1000>;
269 + };
270 +
271 + fman0_oh2: port@83000 {
272 + cell-index = <1>;
273 + compatible = "fsl,fman-port-oh";
274 + reg = <0x83000 0x1000>;
275 + };
276 +
277 + fman0_oh3: port@84000 {
278 + cell-index = <2>;
279 + compatible = "fsl,fman-port-oh";
280 + reg = <0x84000 0x1000>;
281 + };
282 +
283 + fman0_oh4: port@85000 {
284 + cell-index = <3>;
285 + compatible = "fsl,fman-port-oh";
286 + reg = <0x85000 0x1000>;
287 + };
288 +
289 + fman0_oh5: port@86000 {
290 + cell-index = <4>;
291 + compatible = "fsl,fman-port-oh";
292 + reg = <0x86000 0x1000>;
293 + };
294 +
295 + fman0_oh6: port@87000 {
296 + cell-index = <5>;
297 + compatible = "fsl,fman-port-oh";
298 + reg = <0x87000 0x1000>;
299 + };
300 +
301 + policer@c0000 {
302 + compatible = "fsl,fman-policer";
303 + reg = <0xc0000 0x1000>;
304 + };
305 +
306 + keygen@c1000 {
307 + compatible = "fsl,fman-keygen";
308 + reg = <0xc1000 0x1000>;
309 + };
310 +
311 + dma@c2000 {
312 + compatible = "fsl,fman-dma";
313 + reg = <0xc2000 0x1000>;
314 + };
315 +
316 + fpm@c3000 {
317 + compatible = "fsl,fman-fpm";
318 + reg = <0xc3000 0x1000>;
319 + };
320 +
321 + parser@c7000 {
322 + compatible = "fsl,fman-parser";
323 + reg = <0xc7000 0x1000>;
324 + };
325 +
326 + vsps@dc000 {
327 + compatible = "fsl,fman-vsps";
328 + reg = <0xdc000 0x1000>;
329 + };
330 +
331 + mdio0: mdio@fc000 {
332 + #address-cells = <1>;
333 + #size-cells = <0>;
334 + compatible = "fsl,fman-memac-mdio";
335 + reg = <0xfc000 0x1000>;
336 + };
337 +
338 + xmdio0: mdio@fd000 {
339 + #address-cells = <1>;
340 + #size-cells = <0>;
341 + compatible = "fsl,fman-memac-mdio";
342 + reg = <0xfd000 0x1000>;
343 + };
344 +
345 + fman0_rx0: port@88000 {
346 + cell-index = <0>;
347 + compatible = "fsl,fman-port-1g-rx";
348 + reg = <0x88000 0x1000>;
349 + };
350 +
351 + fman0_tx0: port@a8000 {
352 + cell-index = <0>;
353 + compatible = "fsl,fman-port-1g-tx";
354 + reg = <0xa8000 0x1000>;
355 + };
356 +
357 + fm1mac1: ethernet@e0000 {
358 + cell-index = <0>;
359 + compatible = "fsl,fman-memac";
360 + reg = <0xe0000 0x1000>;
361 + fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
362 + ptimer-handle = <&ptp_timer0>;
363 + };
364 +
365 + mdio@e1000 {
366 + #address-cells = <1>;
367 + #size-cells = <0>;
368 + compatible = "fsl,fman-memac-mdio";
369 + reg = <0xe1000 0x1000>;
370 + };
371 +
372 + fman0_rx1: port@89000 {
373 + cell-index = <1>;
374 + compatible = "fsl,fman-port-1g-rx";
375 + reg = <0x89000 0x1000>;
376 + };
377 +
378 + fman0_tx1: port@a9000 {
379 + cell-index = <1>;
380 + compatible = "fsl,fman-port-1g-tx";
381 + reg = <0xa9000 0x1000>;
382 + };
383 +
384 + fm1mac2: ethernet@e2000 {
385 + cell-index = <1>;
386 + compatible = "fsl,fman-memac";
387 + reg = <0xe2000 0x1000>;
388 + fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
389 + ptimer-handle = <&ptp_timer0>;
390 + };
391 +
392 + mdio@e3000 {
393 + #address-cells = <1>;
394 + #size-cells = <0>;
395 + compatible = "fsl,fman-memac-mdio";
396 + reg = <0xe3000 0x1000>;
397 + };
398 +
399 + fman0_rx2: port@8a000 {
400 + cell-index = <2>;
401 + compatible = "fsl,fman-port-1g-rx";
402 + reg = <0x8a000 0x1000>;
403 + };
404 +
405 + fman0_tx2: port@aa000 {
406 + cell-index = <2>;
407 + compatible = "fsl,fman-port-1g-tx";
408 + reg = <0xaa000 0x1000>;
409 + };
410 +
411 + fm1mac3: ethernet@e4000 {
412 + cell-index = <2>;
413 + compatible = "fsl,fman-memac";
414 + reg = <0xe4000 0x1000>;
415 + fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
416 + ptimer-handle = <&ptp_timer0>;
417 + };
418 +
419 + mdio@e5000 {
420 + #address-cells = <1>;
421 + #size-cells = <0>;
422 + compatible = "fsl,fman-memac-mdio";
423 + reg = <0xe5000 0x1000>;
424 + };
425 +
426 + fman0_rx3: port@8b000 {
427 + cell-index = <3>;
428 + compatible = "fsl,fman-port-1g-rx";
429 + reg = <0x8b000 0x1000>;
430 + };
431 +
432 + fman0_tx3: port@ab000 {
433 + cell-index = <3>;
434 + compatible = "fsl,fman-port-1g-tx";
435 + reg = <0xab000 0x1000>;
436 + };
437 +
438 + fm1mac4: ethernet@e6000 {
439 + cell-index = <3>;
440 + compatible = "fsl,fman-memac";
441 + reg = <0xe6000 0x1000>;
442 + fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
443 + ptimer-handle = <&ptp_timer0>;
444 + };
445 +
446 + mdio@e7000 {
447 + #address-cells = <1>;
448 + #size-cells = <0>;
449 + compatible = "fsl,fman-memac-mdio";
450 + reg = <0xe7000 0x1000>;
451 + };
452 +
453 + fman0_rx4: port@8c000 {
454 + cell-index = <4>;
455 + compatible = "fsl,fman-port-1g-rx";
456 + reg = <0x8c000 0x1000>;
457 + };
458 +
459 + fman0_tx4: port@ac000 {
460 + cell-index = <4>;
461 + compatible = "fsl,fman-port-1g-tx";
462 + reg = <0xac000 0x1000>;
463 + };
464 +
465 + fm1mac5: ethernet@e8000 {
466 + cell-index = <4>;
467 + compatible = "fsl,fman-memac";
468 + reg = <0xe8000 0x1000>;
469 + fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
470 + ptimer-handle = <&ptp_timer0>;
471 + };
472 +
473 + mdio@e9000 {
474 + #address-cells = <1>;
475 + #size-cells = <0>;
476 + compatible = "fsl,fman-memac-mdio";
477 + reg = <0xe9000 0x1000>;
478 + };
479 +
480 + fman0_rx5: port@8d000 {
481 + cell-index = <5>;
482 + compatible = "fsl,fman-port-1g-rx";
483 + reg = <0x8d000 0x1000>;
484 + };
485 +
486 + fman0_tx5: port@ad000 {
487 + cell-index = <5>;
488 + compatible = "fsl,fman-port-1g-tx";
489 + reg = <0xad000 0x1000>;
490 + };
491 +
492 + fm1mac6: ethernet@ea000 {
493 + cell-index = <5>;
494 + compatible = "fsl,fman-memac";
495 + reg = <0xea000 0x1000>;
496 + fsl,port-handles = <&fman0_rx5 &fman0_tx5>;
497 + ptimer-handle = <&ptp_timer0>;
498 + };
499 +
500 + mdio@eb000 {
501 + #address-cells = <1>;
502 + #size-cells = <0>;
503 + compatible = "fsl,fman-memac-mdio";
504 + reg = <0xeb000 0x1000>;
505 + };
506 +
507 + fman0_10g_rx0: port@90000 {
508 + cell-index = <0>;
509 + compatible = "fsl,fman-port-10g-rx";
510 + reg = <0x90000 0x1000>;
511 + };
512 +
513 + fman0_10g_tx0: port@b0000 {
514 + cell-index = <0>;
515 + compatible = "fsl,fman-port-10g-tx";
516 + reg = <0xb0000 0x1000>;
517 + fsl,qman-channel-id = <0x800>;
518 + };
519 +
520 + fm1mac9: ethernet@f0000 {
521 + cell-index = <0>;
522 + compatible = "fsl,fman-memac";
523 + reg = <0xf0000 0x1000>;
524 + fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>;
525 + };
526 +
527 + mdio@f1000 {
528 + #address-cells = <1>;
529 + #size-cells = <0>;
530 + compatible = "fsl,fman-memac-mdio";
531 + reg = <0xf1000 0x1000>;
532 + };
533 +
534 + ptp_timer0: rtc@fe000 {
535 + compatible = "fsl,fman-rtc";
536 + reg = <0xfe000 0x1000>;
537 + };
538 + };
539 +
540 + dspi: dspi@2100000 {
541 + compatible = "fsl,ls1046a-dspi", "fsl,ls1021a-v1.0-dspi";
542 + #address-cells = <1>;
543 + #size-cells = <0>;
544 + reg = <0x0 0x2100000 0x0 0x10000>;
545 + interrupts = <0 64 0x4>;
546 + clock-names = "dspi";
547 + clocks = <&clockgen 4 1>;
548 + spi-num-chipselects = <5>;
549 + big-endian;
550 + status = "disabled";
551 + };
552 +
553 + qspi: quadspi@1550000 {
554 + compatible = "fsl,ls1046a-qspi", "fsl,ls1021a-qspi";
555 + #address-cells = <1>;
556 + #size-cells = <0>;
557 + reg = <0x0 0x1550000 0x0 0x10000>,
558 + <0x0 0x40000000 0x0 0x10000000>;
559 + reg-names = "QuadSPI", "QuadSPI-memory";
560 + interrupts = <0 99 0x4>;
561 + clock-names = "qspi_en", "qspi";
562 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
563 + big-endian;
564 + fsl,qspi-has-second-chip;
565 + status = "disabled";
566 + };
567 +
568 + i2c0: i2c@2180000 {
569 + compatible = "fsl,vf610-i2c";
570 + #address-cells = <1>;
571 + #size-cells = <0>;
572 + reg = <0x0 0x2180000 0x0 0x10000>;
573 + interrupts = <0 56 0x4>;
574 + clock-names = "i2c";
575 + clocks = <&clockgen 4 1>;
576 + dmas = <&edma0 1 39>,
577 + <&edma0 1 38>;
578 + dma-names = "tx", "rx";
579 + status = "disabled";
580 + };
581 +
582 + i2c1: i2c@2190000 {
583 + compatible = "fsl,vf610-i2c";
584 + #address-cells = <1>;
585 + #size-cells = <0>;
586 + reg = <0x0 0x2190000 0x0 0x10000>;
587 + interrupts = <0 57 0x4>;
588 + clock-names = "i2c";
589 + clocks = <&clockgen 4 1>;
590 + status = "disabled";
591 + };
592 +
593 + i2c2: i2c@21a0000 {
594 + compatible = "fsl,vf610-i2c";
595 + #address-cells = <1>;
596 + #size-cells = <0>;
597 + reg = <0x0 0x21a0000 0x0 0x10000>;
598 + interrupts = <0 58 0x4>;
599 + clock-names = "i2c";
600 + clocks = <&clockgen 4 1>;
601 + status = "disabled";
602 + };
603 +
604 + i2c3: i2c@21b0000 {
605 + compatible = "fsl,vf610-i2c";
606 + #address-cells = <1>;
607 + #size-cells = <0>;
608 + reg = <0x0 0x21b0000 0x0 0x10000>;
609 + interrupts = <0 59 0x4>;
610 + clock-names = "i2c";
611 + clocks = <&clockgen 4 1>;
612 + status = "disabled";
613 + };
614 +
615 + duart0: serial@21c0500 {
616 + compatible = "fsl,ns16550", "ns16550a";
617 + reg = <0x00 0x21c0500 0x0 0x100>;
618 + interrupts = <0 54 0x4>;
619 + clocks = <&clockgen 4 1>;
620 + };
621 +
622 + duart1: serial@21c0600 {
623 + compatible = "fsl,ns16550", "ns16550a";
624 + reg = <0x00 0x21c0600 0x0 0x100>;
625 + interrupts = <0 54 0x4>;
626 + clocks = <&clockgen 4 1>;
627 + };
628 +
629 + duart2: serial@21d0500 {
630 + compatible = "fsl,ns16550", "ns16550a";
631 + reg = <0x0 0x21d0500 0x0 0x100>;
632 + interrupts = <0 55 0x4>;
633 + clocks = <&clockgen 4 1>;
634 + };
635 +
636 + duart3: serial@21d0600 {
637 + compatible = "fsl,ns16550", "ns16550a";
638 + reg = <0x0 0x21d0600 0x0 0x100>;
639 + interrupts = <0 55 0x4>;
640 + clocks = <&clockgen 4 1>;
641 + };
642 +
643 + gpio0: gpio@2300000 {
644 + compatible = "fsl,qoriq-gpio";
645 + reg = <0x0 0x2300000 0x0 0x10000>;
646 + interrupts = <0 66 0x4>;
647 + gpio-controller;
648 + #gpio-cells = <2>;
649 + interrupt-controller;
650 + #interrupt-cells = <2>;
651 + };
652 +
653 + gpio1: gpio@2310000 {
654 + compatible = "fsl,qoriq-gpio";
655 + reg = <0x0 0x2310000 0x0 0x10000>;
656 + interrupts = <0 67 0x4>;
657 + gpio-controller;
658 + #gpio-cells = <2>;
659 + interrupt-controller;
660 + #interrupt-cells = <2>;
661 + };
662 +
663 + gpio2: gpio@2320000 {
664 + compatible = "fsl,qoriq-gpio";
665 + reg = <0x0 0x2320000 0x0 0x10000>;
666 + interrupts = <0 68 0x4>;
667 + gpio-controller;
668 + #gpio-cells = <2>;
669 + interrupt-controller;
670 + #interrupt-cells = <2>;
671 + };
672 +
673 + gpio3: gpio@2330000 {
674 + compatible = "fsl,qoriq-gpio";
675 + reg = <0x0 0x2330000 0x0 0x10000>;
676 + interrupts = <0 134 0x4>;
677 + gpio-controller;
678 + #gpio-cells = <2>;
679 + interrupt-controller;
680 + #interrupt-cells = <2>;
681 + };
682 +
683 + lpuart0: serial@2950000 {
684 + compatible = "fsl,ls1021a-lpuart";
685 + reg = <0x0 0x2950000 0x0 0x1000>;
686 + interrupts = <0 48 0x4>;
687 + clocks = <&clockgen 0 0>;
688 + clock-names = "ipg";
689 + status = "disabled";
690 + };
691 +
692 + lpuart1: serial@2960000 {
693 + compatible = "fsl,ls1021a-lpuart";
694 + reg = <0x0 0x2960000 0x0 0x1000>;
695 + interrupts = <0 49 0x4>;
696 + clocks = <&clockgen 4 1>;
697 + clock-names = "ipg";
698 + status = "disabled";
699 + };
700 +
701 + lpuart2: serial@2970000 {
702 + compatible = "fsl,ls1021a-lpuart";
703 + reg = <0x0 0x2970000 0x0 0x1000>;
704 + interrupts = <0 50 0x4>;
705 + clocks = <&clockgen 4 1>;
706 + clock-names = "ipg";
707 + status = "disabled";
708 + };
709 +
710 + lpuart3: serial@2980000 {
711 + compatible = "fsl,ls1021a-lpuart";
712 + reg = <0x0 0x2980000 0x0 0x1000>;
713 + interrupts = <0 51 0x4>;
714 + clocks = <&clockgen 4 1>;
715 + clock-names = "ipg";
716 + status = "disabled";
717 + };
718 +
719 + lpuart4: serial@2990000 {
720 + compatible = "fsl,ls1021a-lpuart";
721 + reg = <0x0 0x2990000 0x0 0x1000>;
722 + interrupts = <0 52 0x4>;
723 + clocks = <&clockgen 4 1>;
724 + clock-names = "ipg";
725 + status = "disabled";
726 + };
727 +
728 + lpuart5: serial@29a0000 {
729 + compatible = "fsl,ls1021a-lpuart";
730 + reg = <0x0 0x29a0000 0x0 0x1000>;
731 + interrupts = <0 53 0x4>;
732 + clocks = <&clockgen 4 1>;
733 + clock-names = "ipg";
734 + status = "disabled";
735 + };
736 +
737 + ftm0: ftm0@29d0000 {
738 + compatible = "fsl,ftm-alarm";
739 + reg = <0x0 0x29d0000 0x0 0x10000>;
740 + interrupts = <0 86 0x4>;
741 + big-endian;
742 + rcpm-wakeup = <&rcpm 0x0 0x20000000>;
743 + status = "okay";
744 + };
745 +
746 + wdog0: wdog@2ad0000 {
747 + compatible = "fsl,ls1046a-wdt", "fsl,imx21-wdt";
748 + reg = <0x0 0x2ad0000 0x0 0x10000>;
749 + interrupts = <0 83 0x4>;
750 + clocks = <&clockgen 4 1>;
751 + clock-names = "wdog";
752 + big-endian;
753 + };
754 +
755 + edma0: edma@2c00000 {
756 + #dma-cells = <2>;
757 + compatible = "fsl,vf610-edma";
758 + reg = <0x0 0x2c00000 0x0 0x10000>,
759 + <0x0 0x2c10000 0x0 0x10000>,
760 + <0x0 0x2c20000 0x0 0x10000>;
761 + interrupts = <0 103 0x4>,
762 + <0 103 0x4>;
763 + interrupt-names = "edma-tx", "edma-err";
764 + dma-channels = <32>;
765 + big-endian;
766 + clock-names = "dmamux0", "dmamux1";
767 + clocks = <&clockgen 4 1>,
768 + <&clockgen 4 1>;
769 + };
770 +
771 + usb0: usb3@2f00000 {
772 + compatible = "snps,dwc3";
773 + reg = <0x0 0x2f00000 0x0 0x10000>;
774 + interrupts = <0 60 0x4>;
775 + dr_mode = "host";
776 + configure-gfladj;
777 + snps,dis_rxdet_inp3_quirk;
778 + };
779 +
780 + usb1: usb3@3000000 {
781 + compatible = "snps,dwc3";
782 + reg = <0x0 0x3000000 0x0 0x10000>;
783 + interrupts = <0 61 0x4>;
784 + dr_mode = "host";
785 + configure-gfladj;
786 + snps,dis_rxdet_inp3_quirk;
787 + };
788 +
789 + usb2: usb3@3100000 {
790 + compatible = "snps,dwc3";
791 + reg = <0x0 0x3100000 0x0 0x10000>;
792 + interrupts = <0 63 0x4>;
793 + dr_mode = "host";
794 + configure-gfladj;
795 + snps,dis_rxdet_inp3_quirk;
796 + };
797 +
798 + sata: sata@3200000 {
799 + compatible = "fsl,ls1046a-ahci";
800 + reg = <0x0 0x3200000 0x0 0x10000>;
801 + interrupts = <0 69 0x4>;
802 + clocks = <&clockgen 4 1>;
803 + };
804 +
805 + qdma: qdma@8380000 {
806 + compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
807 + reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */
808 + 0x0 0x83a0000 0x0 0x40000>; /* Block regs */
809 + interrupts = <0 152 0x4>,
810 + <0 39 0x4>;
811 + interrupt-names = "qdma-error", "qdma-queue";
812 + channels = <8>;
813 + queues = <2>;
814 + status-sizes = <64>;
815 + queue-sizes = <64 64>;
816 + big-endian;
817 + };
818 +
819 + msi1: msi-controller@1580000 {
820 + compatible = "fsl,1s1046a-msi";
821 + reg = <0x0 0x1580000 0x0 0x10000>;
822 + msi-controller;
823 + interrupts = <0 116 0x4>,
824 + <0 111 0x4>,
825 + <0 112 0x4>,
826 + <0 113 0x4>;
827 + };
828 +
829 + msi2: msi-controller@1590000 {
830 + compatible = "fsl,1s1046a-msi";
831 + reg = <0x0 0x1590000 0x0 0x10000>;
832 + msi-controller;
833 + interrupts = <0 126 0x4>,
834 + <0 121 0x4>,
835 + <0 122 0x4>,
836 + <0 123 0x4>;
837 + };
838 +
839 + msi3: msi-controller@15a0000 {
840 + compatible = "fsl,1s1046a-msi";
841 + reg = <0x0 0x15a0000 0x0 0x10000>;
842 + msi-controller;
843 + interrupts = <0 160 0x4>,
844 + <0 155 0x4>,
845 + <0 156 0x4>,
846 + <0 157 0x4>;
847 + };
848 +
849 + pcie@3400000 {
850 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
851 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
852 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
853 + reg-names = "regs", "config";
854 + interrupts = <0 118 0x4>, /* controller interrupt */
855 + <0 117 0x4>; /* PME interrupt */
856 + interrupt-names = "intr", "pme";
857 + #address-cells = <3>;
858 + #size-cells = <2>;
859 + device_type = "pci";
860 + num-lanes = <4>;
861 + bus-range = <0x0 0xff>;
862 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
863 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
864 + msi-parent = <&msi1>;
865 + #interrupt-cells = <1>;
866 + interrupt-map-mask = <0 0 0 7>;
867 + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
868 + <0000 0 0 2 &gic 0 110 0x4>,
869 + <0000 0 0 3 &gic 0 110 0x4>,
870 + <0000 0 0 4 &gic 0 110 0x4>;
871 + };
872 +
873 + pcie@3500000 {
874 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
875 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
876 + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
877 + reg-names = "regs", "config";
878 + interrupts = <0 128 0x4>,
879 + <0 127 0x4>;
880 + interrupt-names = "intr", "pme";
881 + #address-cells = <3>;
882 + #size-cells = <2>;
883 + device_type = "pci";
884 + num-lanes = <2>;
885 + bus-range = <0x0 0xff>;
886 + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
887 + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
888 + msi-parent = <&msi2>;
889 + #interrupt-cells = <1>;
890 + interrupt-map-mask = <0 0 0 7>;
891 + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
892 + <0000 0 0 2 &gic 0 120 0x4>,
893 + <0000 0 0 3 &gic 0 120 0x4>,
894 + <0000 0 0 4 &gic 0 120 0x4>;
895 + };
896 +
897 + pcie@3600000 {
898 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
899 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
900 + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
901 + reg-names = "regs", "config";
902 + interrupts = <0 162 0x4>,
903 + <0 161 0x4>;
904 + interrupt-names = "intr", "pme";
905 + #address-cells = <3>;
906 + #size-cells = <2>;
907 + device_type = "pci";
908 + num-lanes = <2>;
909 + bus-range = <0x0 0xff>;
910 + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
911 + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
912 + msi-parent = <&msi3>;
913 + #interrupt-cells = <1>;
914 + interrupt-map-mask = <0 0 0 7>;
915 + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
916 + <0000 0 0 2 &gic 0 154 0x4>,
917 + <0000 0 0 3 &gic 0 154 0x4>,
918 + <0000 0 0 4 &gic 0 154 0x4>;
919 + };
920 + };
921 +
922 + fsl,dpaa {
923 + compatible = "fsl,ls1046a-dpaa", "simple-bus", "fsl,dpaa";
924 + ethernet@0 {
925 + compatible = "fsl,dpa-ethernet";
926 + fsl,fman-mac = <&fm1mac1>;
927 + };
928 + ethernet@1 {
929 + compatible = "fsl,dpa-ethernet";
930 + fsl,fman-mac = <&fm1mac2>;
931 + };
932 + ethernet@2 {
933 + compatible = "fsl,dpa-ethernet";
934 + fsl,fman-mac = <&fm1mac3>;
935 + };
936 + ethernet@3 {
937 + compatible = "fsl,dpa-ethernet";
938 + fsl,fman-mac = <&fm1mac4>;
939 + };
940 + ethernet@4 {
941 + compatible = "fsl,dpa-ethernet";
942 + fsl,fman-mac = <&fm1mac5>;
943 + };
944 + ethernet@5 {
945 + compatible = "fsl,dpa-ethernet";
946 + fsl,fman-mac = <&fm1mac6>;
947 + };
948 + ethernet@8 {
949 + compatible = "fsl,dpa-ethernet";
950 + fsl,fman-mac = <&fm1mac9>;
951 + };
952 + };
953 +
954 + qportals: qman-portals@500000000 {
955 + ranges = <0x0 0x5 0x00000000 0x8000000>;
956 + };
957 + bportals: bman-portals@508000000 {
958 + ranges = <0x0 0x5 0x08000000 0x8000000>;
959 + };
960 + reserved-memory {
961 + #address-cells = <2>;
962 + #size-cells = <2>;
963 + ranges;
964 +
965 + bman_fbpr: bman-fbpr {
966 + size = <0 0x1000000>;
967 + alignment = <0 0x1000000>;
968 + };
969 + qman_fqd: qman-fqd {
970 + size = <0 0x800000>;
971 + alignment = <0 0x800000>;
972 + };
973 + qman_pfdr: qman-pfdr {
974 + size = <0 0x2000000>;
975 + alignment = <0 0x2000000>;
976 + };
977 + };
978 +};
979 +
980 +&fman0 {
981 + /* offline - 1 */
982 + port@82000 {
983 + fsl,qman-channel-id = <0x809>;
984 + };
985 +
986 + /* tx - 10g - 2 */
987 + port@a8000 {
988 + fsl,qman-channel-id = <0x802>;
989 + };
990 + /* tx - 10g - 3 */
991 + port@a9000 {
992 + fsl,qman-channel-id = <0x803>;
993 + };
994 + /* tx - 1g - 2 */
995 + port@aa000 {
996 + fsl,qman-channel-id = <0x804>;
997 + };
998 + /* tx - 1g - 3 */
999 + port@ab000 {
1000 + fsl,qman-channel-id = <0x805>;
1001 + };
1002 + /* tx - 1g - 4 */
1003 + port@ac000 {
1004 + fsl,qman-channel-id = <0x806>;
1005 + };
1006 + /* tx - 1g - 5 */
1007 + port@ad000 {
1008 + fsl,qman-channel-id = <0x807>;
1009 + };
1010 + /* tx - 10g - 0 */
1011 + port@b0000 {
1012 + fsl,qman-channel-id = <0x800>;
1013 + };
1014 + /* tx - 10g - 1 */
1015 + port@b1000 {
1016 + fsl,qman-channel-id = <0x801>;
1017 + };
1018 + /* offline - 2 */
1019 + port@83000 {
1020 + fsl,qman-channel-id = <0x80a>;
1021 + };
1022 + /* offline - 3 */
1023 + port@84000 {
1024 + fsl,qman-channel-id = <0x80b>;
1025 + };
1026 + /* offline - 4 */
1027 + port@85000 {
1028 + fsl,qman-channel-id = <0x80c>;
1029 + };
1030 + /* offline - 5 */
1031 + port@86000 {
1032 + fsl,qman-channel-id = <0x80d>;
1033 + };
1034 + /* offline - 6 */
1035 + port@87000 {
1036 + fsl,qman-channel-id = <0x80e>;
1037 + };
1038 +};
1039 +
1040 +&bman_fbpr {
1041 + compatible = "fsl,bman-fbpr";
1042 + alloc-ranges = <0 0 0x10000 0>;
1043 +};
1044 +
1045 +&qman_fqd {
1046 + compatible = "fsl,qman-fqd";
1047 + alloc-ranges = <0 0 0x10000 0>;
1048 +};
1049 +
1050 +&qman_pfdr {
1051 + compatible = "fsl,qman-pfdr";
1052 + alloc-ranges = <0 0 0x10000 0>;
1053 +};
1054 +
1055 +/include/ "qoriq-qman1-portals.dtsi"
1056 +/include/ "qoriq-bman1-portals.dtsi"
OpenWrt Source Repository