layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.4 / 1107-mtd-fsl-quadspi-disable-AHB-buffer-prefetch.patch
1 From 50aac689d5be0a086f076cd4bc8b14ee0b9ab995 Mon Sep 17 00:00:00 2001
2 From: Yunhui Cui <yunhui.cui@nxp.com>
3 Date: Tue, 8 Mar 2016 14:38:52 +0800
4 Subject: [PATCH 107/113] mtd: fsl-quadspi: disable AHB buffer prefetch
5
6 A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
7 Affects: QuadSPI
8 Description: With AHB buffer prefetch enabled, the QuadSPI may return
9 incorrect data on the AHB
10 interface. The buffer pre-fetch is enabled if the fetch size as
11 configured either in the LUT or in
12 the BUFxCR register is greater than 8 bytes.
13 Impact: Only 64 bit read allowed.
14 Workaround: Keep the read data size to 64 bits (8 Bytes), which disables
15 the prefetch on the AHB buffer,
16 and prevents this issue from occurring.
17
18 Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
19 ---
20 drivers/mtd/spi-nor/fsl-quadspi.c | 29 +++++++++++++++++++++++------
21 1 file changed, 23 insertions(+), 6 deletions(-)
22
23 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
24 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
25 @@ -794,19 +794,36 @@ static void fsl_qspi_init_abh_read(struc
26 {
27 void __iomem *base = q->iobase;
28 int seqid;
29 + const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
30
31 /* AHB configuration for access buffer 0/1/2 .*/
32 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
33 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
34 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
35 +
36 /*
37 - * Set ADATSZ with the maximum AHB buffer size to improve the
38 - * read performance.
39 + * Errata: A-009282: QuadSPI data prefetch may result in incorrect data
40 + * Workaround: Keep the read data size to 64 bits (8 bytes).
41 + * This disables the prefetch on the AHB buffer and
42 + * prevents this issue from occurring.
43 */
44 - qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
45 - ((q->devtype_data->ahb_buf_size / 8)
46 - << QUADSPI_BUF3CR_ADATSZ_SHIFT),
47 - base + QUADSPI_BUF3CR);
48 + if (devtype_data->devtype == FSL_QUADSPI_LS2080A ||
49 + devtype_data->devtype == FSL_QUADSPI_LS1021A) {
50 +
51 + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
52 + (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
53 + base + QUADSPI_BUF3CR);
54 +
55 + } else {
56 + /*
57 + * Set ADATSZ with the maximum AHB buffer size to improve the
58 + * read performance.
59 + */
60 + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
61 + ((q->devtype_data->ahb_buf_size / 8)
62 + << QUADSPI_BUF3CR_ADATSZ_SHIFT),
63 + base + QUADSPI_BUF3CR);
64 + }
65
66 /* We only use the buffer3 */
67 qspi_writel(q, 0, base + QUADSPI_BUF0IND);