target/linux/layerscape/patches-4.4/1102-mtd-spi-nor-fsl-quadspi-Support-qspi-for-ls2080a.patch

   1 From d2d88e3432d68b11b0add84bd15a3aadaf44f1c1 Mon Sep 17 00:00:00 2001
   2 From: Yunhui Cui <B56489@freescale.com>
   3 Date: Mon, 28 Dec 2015 18:25:56 +0800
   4 Subject: [PATCH 102/113] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a
   5
   6 There is a hardware feature that qspi_amba_base is added
   7 internally by SOC design on ls2080a. So as to software, the driver
   8 need support to the feature.
   9
  10 Signed-off-by: Yunhui Cui <B56489@freescale.com>
  11 Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
  12 ---
  13  drivers/mtd/spi-nor/fsl-quadspi.c |   24 ++++++++++++++++++++++--
  14  1 file changed, 22 insertions(+), 2 deletions(-)
  15
  16 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
  17 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
  18 @@ -41,6 +41,8 @@
  19  #define QUADSPI_QUIRK_TKT253890                (1 << 2)
  20  /* Controller cannot wake up from wait mode, TKT245618 */
  21  #define QUADSPI_QUIRK_TKT245618         (1 << 3)
  22 +/* QSPI_AMBA_BASE is internally added by SOC design */
  23 +#define QUADSPI_AMBA_BASE_INTERNAL     (0x10000)
  24
  25  /* The registers */
  26  #define QUADSPI_MCR                    0x00
  27 @@ -217,6 +219,7 @@ enum fsl_qspi_devtype {
  28         FSL_QUADSPI_IMX7D,
  29         FSL_QUADSPI_IMX6UL,
  30         FSL_QUADSPI_LS1021A,
  31 +       FSL_QUADSPI_LS2080A,
  32  };
  33
  34  struct fsl_qspi_devtype_data {
  35 @@ -270,6 +273,14 @@ static struct fsl_qspi_devtype_data ls10
  36         .driver_data = 0,
  37  };
  38
  39 +static struct fsl_qspi_devtype_data ls2080a_data = {
  40 +       .devtype = FSL_QUADSPI_LS2080A,
  41 +       .rxfifo = 128,
  42 +       .txfifo = 64,
  43 +       .ahb_buf_size = 1024,
  44 +       .driver_data = QUADSPI_AMBA_BASE_INTERNAL,
  45 +};
  46 +
  47  #define FSL_QSPI_MAX_CHIP      4
  48  struct fsl_qspi {
  49         struct spi_nor nor[FSL_QSPI_MAX_CHIP];
  50 @@ -312,6 +323,11 @@ static inline int needs_wakeup_wait_mode
  51         return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
  52  }
  53
  54 +static inline int has_added_amba_base_internal(struct fsl_qspi *q)
  55 +{
  56 +       return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
  57 +}
  58 +
  59  /*
  60   * R/W functions for big- or little-endian registers:
  61   * The qSPI controller's endian is independent of the CPU core's endian.
  62 @@ -558,8 +574,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
  63         /* save the reg */
  64         reg = qspi_readl(q, base + QUADSPI_MCR);
  65
  66 -       qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
  67 -                       base + QUADSPI_SFAR);
  68 +       if (has_added_amba_base_internal(q))
  69 +               qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR);
  70 +       else
  71 +               qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
  72 +                           base + QUADSPI_SFAR);
  73         qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
  74                         base + QUADSPI_RBCT);
  75         qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
  76 @@ -849,6 +868,7 @@ static const struct of_device_id fsl_qsp
  77         { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
  78         { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
  79         { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
  80 +       { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
  81         { /* sentinel */ }
  82  };
  83  MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);