target/linux/layerscape/patches-4.4/0058-PCI-designware-Move-Root-Complex-setup-code-to-dw_pc.patch

   1 From 892a427f8a2b25b561298941cf1fc0373a98b269 Mon Sep 17 00:00:00 2001
   2 From: Jisheng Zhang <jszhang@marvell.com>
   3 Date: Wed, 16 Mar 2016 19:40:33 +0800
   4 Subject: [PATCH 58/70] PCI: designware: Move Root Complex setup code to
   5  dw_pcie_setup_rc()
   6
   7 dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates
   8 IRQ domains, and enumerates devices below the bridge.  dw_pcie_setup_rc()
   9 programs the Root Complex registers.  The Root Complex may lose power
  10 during suspend-to-RAM, and when we resume, we want to redo the latter but
  11 not the former.
  12
  13 Move some Root Complex programming from dw_pcie_host_init() to
  14 dw_pcie_setup_rc() where it belongs.  DesignWare-based drivers can call
  15 dw_pcie_setup_rc() in their resume paths.
  16
  17 [Niklas Cassel <niklas.cassel@axis.com>:  This change moves outbound ATU
  18 programming, which uses pp->mem_base, to dw_pcie_setup_rc().  Apply the
  19 dra7xx pp->mem_base update before calling dw_pcie_setup_rc().]
  20
  21 [bhelgaas: changelog, fold in dra7xx fix from Niklas]
  22 Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
  23 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  24 Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
  25 ---
  26  drivers/pci/host/pci-dra7xx.c      |    4 ++--
  27  drivers/pci/host/pcie-designware.c |   39 ++++++++++++++++++------------------
  28  2 files changed, 21 insertions(+), 22 deletions(-)
  29
  30 --- a/drivers/pci/host/pci-dra7xx.c
  31 +++ b/drivers/pci/host/pci-dra7xx.c
  32 @@ -142,13 +142,13 @@ static void dra7xx_pcie_enable_interrupt
  33
  34  static void dra7xx_pcie_host_init(struct pcie_port *pp)
  35  {
  36 -       dw_pcie_setup_rc(pp);
  37 -
  38         pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
  39         pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
  40         pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
  41         pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
  42
  43 +       dw_pcie_setup_rc(pp);
  44 +
  45         dra7xx_pcie_establish_link(pp);
  46         if (IS_ENABLED(CONFIG_PCI_MSI))
  47                 dw_pcie_msi_init(pp);
  48 --- a/drivers/pci/host/pcie-designware.c
  49 +++ b/drivers/pci/host/pcie-designware.c
  50 @@ -434,7 +434,6 @@ int dw_pcie_host_init(struct pcie_port *
  51         struct platform_device *pdev = to_platform_device(pp->dev);
  52         struct pci_bus *bus, *child;
  53         struct resource *cfg_res;
  54 -       u32 val;
  55         int i, ret;
  56         LIST_HEAD(res);
  57         struct resource_entry *win;
  58 @@ -544,25 +543,6 @@ int dw_pcie_host_init(struct pcie_port *
  59         if (pp->ops->host_init)
  60                 pp->ops->host_init(pp);
  61
  62 -       /*
  63 -        * If the platform provides ->rd_other_conf, it means the platform
  64 -        * uses its own address translation component rather than ATU, so
  65 -        * we should not program the ATU here.
  66 -        */
  67 -       if (!pp->ops->rd_other_conf)
  68 -               dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
  69 -                                         PCIE_ATU_TYPE_MEM, pp->mem_base,
  70 -                                         pp->mem_bus_addr, pp->mem_size);
  71 -
  72 -       dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
  73 -
  74 -       /* program correct class for RC */
  75 -       dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
  76 -
  77 -       dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
  78 -       val |= PORT_LOGIC_SPEED_CHANGE;
  79 -       dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
  80 -
  81         pp->root_bus_nr = pp->busn->start;
  82         if (IS_ENABLED(CONFIG_PCI_MSI)) {
  83                 bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
  84 @@ -800,6 +780,25 @@ void dw_pcie_setup_rc(struct pcie_port *
  85         val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  86                 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
  87         dw_pcie_writel_rc(pp, val, PCI_COMMAND);
  88 +
  89 +       /*
  90 +        * If the platform provides ->rd_other_conf, it means the platform
  91 +        * uses its own address translation component rather than ATU, so
  92 +        * we should not program the ATU here.
  93 +        */
  94 +       if (!pp->ops->rd_other_conf)
  95 +               dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
  96 +                                         PCIE_ATU_TYPE_MEM, pp->mem_base,
  97 +                                         pp->mem_bus_addr, pp->mem_size);
  98 +
  99 +       dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 100 +
 101 +       /* program correct class for RC */
 102 +       dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
 103 +
 104 +       dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
 105 +       val |= PORT_LOGIC_SPEED_CHANGE;
 106 +       dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
 107  }
 108
 109  MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");