target/linux/ipq807x/patches-5.15/0077-v6.0-PCI-qcom-Add-IPQ60xx-support.patch

   1 From a7d96ca20847ade9f29cff4521f43b8ae968b3df Mon Sep 17 00:00:00 2001
   2 From: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
   3 Date: Tue, 21 Jun 2022 11:54:54 +0300
   4 Subject: [PATCH] PCI: qcom: Add IPQ60xx support
   5
   6 IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that
   7 platform.
   8
   9 The code is based on downstream[1] Codeaurora kernel v5.4 (branch
  10 win.linuxopenwrt.2.0).
  11
  12 Split out the DBI registers access part from .init into .post_init. DBI
  13 registers are only accessible after phy_power_on().
  14
  15 [1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/
  16
  17 Link: https://lore.kernel.org/r/f7f848653c99abbf9a0f877949a44e52329543ae.1655799816.git.baruch@tkos.co.il
  18 Tested-by: Robert Marko <robert.marko@sartura.hr>
  19 Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
  20 Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
  21 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  22 Reviewed-by: Rob Herring <robh@kernel.org>
  23 Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
  24 Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  25 ---
  26  drivers/pci/controller/dwc/pcie-designware.h |   1 +
  27  drivers/pci/controller/dwc/pcie-qcom.c       | 130 +++++++++++++++++++
  28  2 files changed, 131 insertions(+)
  29
  30 --- a/drivers/pci/controller/dwc/pcie-designware.h
  31 +++ b/drivers/pci/controller/dwc/pcie-designware.h
  32 @@ -76,6 +76,7 @@
  33
  34  #define GEN3_RELATED_OFF                       0x890
  35  #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL   BIT(0)
  36 +#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS    BIT(13)
  37  #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE       BIT(16)
  38  #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
  39  #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK  GENMASK(25, 24)
  40 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  41 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  42 @@ -52,6 +52,10 @@
  43  #define PCIE20_PARF_DBI_BASE_ADDR              0x168
  44  #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE                0x16C
  45  #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL       0x174
  46 +#define AHB_CLK_EN                             BIT(0)
  47 +#define MSTR_AXI_CLK_EN                                BIT(1)
  48 +#define BYPASS                                 BIT(4)
  49 +
  50  #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT      0x178
  51  #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2   0x1A8
  52  #define PCIE20_PARF_LTSSM                      0x1B0
  53 @@ -181,6 +185,11 @@ struct qcom_pcie_resources_2_7_0 {
  54         struct clk *pipe_clk;
  55  };
  56
  57 +struct qcom_pcie_resources_2_9_0 {
  58 +       struct clk_bulk_data clks[5];
  59 +       struct reset_control *rst;
  60 +};
  61 +
  62  union qcom_pcie_resources {
  63         struct qcom_pcie_resources_1_0_0 v1_0_0;
  64         struct qcom_pcie_resources_2_1_0 v2_1_0;
  65 @@ -188,6 +197,7 @@ union qcom_pcie_resources {
  66         struct qcom_pcie_resources_2_3_3 v2_3_3;
  67         struct qcom_pcie_resources_2_4_0 v2_4_0;
  68         struct qcom_pcie_resources_2_7_0 v2_7_0;
  69 +       struct qcom_pcie_resources_2_9_0 v2_9_0;
  70  };
  71
  72  struct qcom_pcie;
  73 @@ -1282,6 +1292,112 @@ static void qcom_pcie_post_deinit_2_7_0(
  74         clk_disable_unprepare(res->pipe_clk);
  75  }
  76
  77 +static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
  78 +{
  79 +       struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
  80 +       struct dw_pcie *pci = pcie->pci;
  81 +       struct device *dev = pci->dev;
  82 +       int ret;
  83 +
  84 +       res->clks[0].id = "iface";
  85 +       res->clks[1].id = "axi_m";
  86 +       res->clks[2].id = "axi_s";
  87 +       res->clks[3].id = "axi_bridge";
  88 +       res->clks[4].id = "rchng";
  89 +
  90 +       ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
  91 +       if (ret < 0)
  92 +               return ret;
  93 +
  94 +       res->rst = devm_reset_control_array_get_exclusive(dev);
  95 +       if (IS_ERR(res->rst))
  96 +               return PTR_ERR(res->rst);
  97 +
  98 +       return 0;
  99 +}
 100 +
 101 +static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
 102 +{
 103 +       struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
 104 +
 105 +       clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
 106 +}
 107 +
 108 +static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
 109 +{
 110 +       struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
 111 +       struct device *dev = pcie->pci->dev;
 112 +       int ret;
 113 +
 114 +       ret = reset_control_assert(res->rst);
 115 +       if (ret) {
 116 +               dev_err(dev, "reset assert failed (%d)\n", ret);
 117 +               return ret;
 118 +       }
 119 +
 120 +       /*
 121 +        * Delay periods before and after reset deassert are working values
 122 +        * from downstream Codeaurora kernel
 123 +        */
 124 +       usleep_range(2000, 2500);
 125 +
 126 +       ret = reset_control_deassert(res->rst);
 127 +       if (ret) {
 128 +               dev_err(dev, "reset deassert failed (%d)\n", ret);
 129 +               return ret;
 130 +       }
 131 +
 132 +       usleep_range(2000, 2500);
 133 +
 134 +       return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
 135 +}
 136 +
 137 +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
 138 +{
 139 +       struct dw_pcie *pci = pcie->pci;
 140 +       u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 141 +       u32 val;
 142 +       int i;
 143 +
 144 +       writel(SLV_ADDR_SPACE_SZ,
 145 +               pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
 146 +
 147 +       val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
 148 +       val &= ~BIT(0);
 149 +       writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
 150 +
 151 +       writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
 152 +
 153 +       writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
 154 +       writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
 155 +               pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
 156 +       writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
 157 +               GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
 158 +               pci->dbi_base + GEN3_RELATED_OFF);
 159 +
 160 +       writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
 161 +               SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
 162 +               AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
 163 +               pcie->parf + PCIE20_PARF_SYS_CTRL);
 164 +
 165 +       writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
 166 +
 167 +       dw_pcie_dbi_ro_wr_en(pci);
 168 +       writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
 169 +
 170 +       val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
 171 +       val &= ~PCI_EXP_LNKCAP_ASPMS;
 172 +       writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
 173 +
 174 +       writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
 175 +                       PCI_EXP_DEVCTL2);
 176 +
 177 +       for (i = 0; i < 256; i++)
 178 +               writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
 179 +
 180 +       return 0;
 181 +}
 182 +
 183  static int qcom_pcie_link_up(struct dw_pcie *pci)
 184  {
 185         u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 186 @@ -1473,6 +1589,15 @@ static const struct qcom_pcie_ops ops_1_
 187         .config_sid = qcom_pcie_config_sid_sm8250,
 188  };
 189
 190 +/* Qcom IP rev.: 2.9.0  Synopsys IP rev.: 5.00a */
 191 +static const struct qcom_pcie_ops ops_2_9_0 = {
 192 +       .get_resources = qcom_pcie_get_resources_2_9_0,
 193 +       .init = qcom_pcie_init_2_9_0,
 194 +       .post_init = qcom_pcie_post_init_2_9_0,
 195 +       .deinit = qcom_pcie_deinit_2_9_0,
 196 +       .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
 197 +};
 198 +
 199  static const struct qcom_pcie_cfg apq8084_cfg = {
 200         .ops = &ops_1_0_0,
 201  };
 202 @@ -1505,6 +1630,10 @@ static const struct qcom_pcie_cfg sc7280
 203         .ops = &ops_1_9_0,
 204  };
 205
 206 +static const struct qcom_pcie_cfg ipq6018_cfg = {
 207 +       .ops = &ops_2_9_0,
 208 +};
 209 +
 210  static const struct dw_pcie_ops dw_pcie_ops = {
 211         .link_up = qcom_pcie_link_up,
 212         .start_link = qcom_pcie_start_link,
 213 @@ -1611,6 +1740,7 @@ static const struct of_device_id qcom_pc
 214         { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
 215         { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
 216         { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
 217 +       { .compatible = "qcom,pcie-ipq6018", .data = &ipq6018_cfg },
 218         { }
 219  };
 220