target/linux/ipq806x/patches-6.6/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch

   1 From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Tue, 18 Jan 2022 00:07:57 +0100
   4 Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu
   5  and l2 for ipq8064
   6
   7 Add multiple binding for cpu node, l2 node and add idle-states
   8 definition for ipq8064 dtsi.
   9
  10 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  11 Tested-by: Jonathan McDowell <noodles@earth.li>
  12 ---
  13  arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
  14  1 file changed, 36 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
  17 +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
  18 @@ -30,6 +30,15 @@
  19                         next-level-cache = <&L2>;
  20                         qcom,acc = <&acc0>;
  21                         qcom,saw = <&saw0>;
  22 +                       clocks = <&kraitcc 0>, <&kraitcc 4>;
  23 +                       clock-names = "cpu", "l2";
  24 +                       clock-latency = <100000>;
  25 +                       operating-points-v2 = <&opp_table0>;
  26 +                       voltage-tolerance = <5>;
  27 +                       cooling-min-state = <0>;
  28 +                       cooling-max-state = <10>;
  29 +                       #cooling-cells = <2>;
  30 +                       cpu-idle-states = <&CPU_SPC>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34 @@ -40,12 +49,36 @@
  35                         next-level-cache = <&L2>;
  36                         qcom,acc = <&acc1>;
  37                         qcom,saw = <&saw1>;
  38 +                       clocks = <&kraitcc 1>, <&kraitcc 4>;
  39 +                       clock-names = "cpu", "l2";
  40 +                       clock-latency = <100000>;
  41 +                       operating-points-v2 = <&opp_table0>;
  42 +                       voltage-tolerance = <5>;
  43 +                       cooling-min-state = <0>;
  44 +                       cooling-max-state = <10>;
  45 +                       #cooling-cells = <2>;
  46 +                       cpu-idle-states = <&CPU_SPC>;
  47 +               };
  48 +
  49 +               idle-states {
  50 +                       CPU_SPC: spc {
  51 +                               compatible = "qcom,idle-state-spc";
  52 +                               status = "disabled";
  53 +                               entry-latency-us = <400>;
  54 +                               exit-latency-us = <900>;
  55 +                               min-residency-us = <3000>;
  56 +                       };
  57                 };
  58
  59                 L2: l2-cache {
  60                         compatible = "cache";
  61                         cache-level = <2>;
  62                         cache-unified;
  63 +                       qcom,saw = <&saw_l2>;
  64 +
  65 +                       clocks = <&kraitcc 4>;
  66 +                       clock-names = "l2";
  67 +                       operating-points-v2 = <&opp_table_l2>;
  68                 };
  69         };
  70
  71 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi
  72 +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi
  73 @@ -2,6 +2,18 @@
  74
  75  #include "qcom-ipq8064.dtsi"
  76
  77 +&cpu0 {
  78 +       cpu-supply = <&smb208_s2a>;
  79 +};
  80 +
  81 +&cpu1 {
  82 +       cpu-supply = <&smb208_s2b>;
  83 +};
  84 +
  85 +&L2 {
  86 +       l2-supply = <&smb208_s1a>;
  87 +};
  88 +
  89  &rpm {
  90         smb208_regulators: regulators {
  91                 compatible = "qcom,rpm-smb208-regulators";
  92 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi
  93 +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi
  94 @@ -2,6 +2,18 @@
  95
  96  #include "qcom-ipq8064-v2.0.dtsi"
  97
  98 +&cpu0 {
  99 +       cpu-supply = <&smb208_s2a>;
 100 +};
 101 +
 102 +&cpu1 {
 103 +       cpu-supply = <&smb208_s2b>;
 104 +};
 105 +
 106 +&L2 {
 107 +       l2-supply = <&smb208_s1a>;
 108 +};
 109 +
 110  &rpm {
 111         smb208_regulators: regulators {
 112                 compatible = "qcom,rpm-smb208-regulators";
 113 --- a/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi
 114 +++ b/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi
 115 @@ -2,6 +2,18 @@
 116
 117  #include "qcom-ipq8062.dtsi"
 118
 119 +&cpu0 {
 120 +       cpu-supply = <&smb208_s2a>;
 121 +};
 122 +
 123 +&cpu1 {
 124 +       cpu-supply = <&smb208_s2b>;
 125 +};
 126 +
 127 +&L2 {
 128 +       l2-supply = <&smb208_s1a>;
 129 +};
 130 +
 131  &rpm {
 132         smb208_regulators: regulators {
 133                 compatible = "qcom,rpm-smb208-regulators";
 134 --- a/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi
 135 +++ b/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi
 136 @@ -2,6 +2,18 @@
 137
 138  #include "qcom-ipq8065.dtsi"
 139
 140 +&cpu0 {
 141 +       cpu-supply = <&smb208_s2a>;
 142 +};
 143 +
 144 +&cpu1 {
 145 +       cpu-supply = <&smb208_s2b>;
 146 +};
 147 +
 148 +&L2 {
 149 +       l2-supply = <&smb208_s1a>;
 150 +};
 151 +
 152  &rpm {
 153         smb208_regulators: regulators {
 154                 compatible = "qcom,rpm-smb208-regulators";