target/linux/ipq806x/patches-6.1/109-v6.1-03-clk-qcom-lcc-ipq806x-convert-to-parent-data.patch

   1 From 92ef900a4a53b62e0dc32554eb088a422657606c Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Wed, 15 Jun 2022 17:35:13 +0200
   4 Subject: [PATCH v5 3/3] clk: qcom: lcc-ipq806x: convert to parent data
   5
   6 Convert lcc-ipq806x driver to parent_data API.
   7
   8 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
   9 ---
  10 v5:
  11 - Fix the same compilation error (don't know what the hell happen
  12   to my buildroot)
  13 v4:
  14 - Fix compilation error
  15 v3:
  16  - Inline pxo pll4 parent
  17  - Change .name from pxo to pxo_board
  18
  19  drivers/clk/qcom/lcc-ipq806x.c | 77 ++++++++++++++++++----------------
  20  1 file changed, 42 insertions(+), 35 deletions(-)
  21
  22 --- a/drivers/clk/qcom/lcc-ipq806x.c
  23 +++ b/drivers/clk/qcom/lcc-ipq806x.c
  24 @@ -34,7 +34,9 @@ static struct clk_pll pll4 = {
  25         .status_bit = 16,
  26         .clkr.hw.init = &(struct clk_init_data){
  27                 .name = "pll4",
  28 -               .parent_names = (const char *[]){ "pxo" },
  29 +               .parent_data = &(const struct clk_parent_data) {
  30 +                       .fw_name = "pxo", .name = "pxo_board",
  31 +               },
  32                 .num_parents = 1,
  33                 .ops = &clk_pll_ops,
  34         },
  35 @@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_p
  36         { P_PLL4, 2 }
  37  };
  38
  39 -static const char * const lcc_pxo_pll4[] = {
  40 -       "pxo",
  41 -       "pll4_vote",
  42 +static const struct clk_parent_data lcc_pxo_pll4[] = {
  43 +       { .fw_name = "pxo", .name = "pxo" },
  44 +       { .fw_name = "pll4_vote", .name = "pll4_vote" },
  45  };
  46
  47  static struct freq_tbl clk_tbl_aif_mi2s[] = {
  48 @@ -131,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = {
  49                 .enable_mask = BIT(9),
  50                 .hw.init = &(struct clk_init_data){
  51                         .name = "mi2s_osr_src",
  52 -                       .parent_names = lcc_pxo_pll4,
  53 -                       .num_parents = 2,
  54 +                       .parent_data = lcc_pxo_pll4,
  55 +                       .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
  56                         .ops = &clk_rcg_ops,
  57                         .flags = CLK_SET_RATE_GATE,
  58                 },
  59         },
  60  };
  61
  62 -static const char * const lcc_mi2s_parents[] = {
  63 -       "mi2s_osr_src",
  64 -};
  65 -
  66  static struct clk_branch mi2s_osr_clk = {
  67         .halt_reg = 0x50,
  68         .halt_bit = 1,
  69 @@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk =
  70                 .enable_mask = BIT(17),
  71                 .hw.init = &(struct clk_init_data){
  72                         .name = "mi2s_osr_clk",
  73 -                       .parent_names = lcc_mi2s_parents,
  74 +                       .parent_hws = (const struct clk_hw*[]){
  75 +                               &mi2s_osr_src.clkr.hw,
  76 +                       },
  77                         .num_parents = 1,
  78                         .ops = &clk_branch_ops,
  79                         .flags = CLK_SET_RATE_PARENT,
  80 @@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_cl
  81         .clkr = {
  82                 .hw.init = &(struct clk_init_data){
  83                         .name = "mi2s_div_clk",
  84 -                       .parent_names = lcc_mi2s_parents,
  85 +                       .parent_hws = (const struct clk_hw*[]){
  86 +                               &mi2s_osr_src.clkr.hw,
  87 +                       },
  88                         .num_parents = 1,
  89                         .ops = &clk_regmap_div_ops,
  90                 },
  91 @@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_cl
  92                 .enable_mask = BIT(15),
  93                 .hw.init = &(struct clk_init_data){
  94                         .name = "mi2s_bit_div_clk",
  95 -                       .parent_names = (const char *[]){ "mi2s_div_clk" },
  96 +                       .parent_hws = (const struct clk_hw*[]){
  97 +                               &mi2s_div_clk.clkr.hw,
  98 +                       },
  99                         .num_parents = 1,
 100                         .ops = &clk_branch_ops,
 101                         .flags = CLK_SET_RATE_PARENT,
 102 @@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_cl
 103         },
 104  };
 105
 106 +static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
 107 +       { .hw = &mi2s_bit_div_clk.clkr.hw, },
 108 +       { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" },
 109 +};
 110
 111  static struct clk_regmap_mux mi2s_bit_clk = {
 112         .reg = 0x48,
 113 @@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_cl
 114         .clkr = {
 115                 .hw.init = &(struct clk_init_data){
 116                         .name = "mi2s_bit_clk",
 117 -                       .parent_names = (const char *[]){
 118 -                               "mi2s_bit_div_clk",
 119 -                               "mi2s_codec_clk",
 120 -                       },
 121 -                       .num_parents = 2,
 122 +                       .parent_data = lcc_mi2s_bit_div_codec_clk,
 123 +                       .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
 124                         .ops = &clk_regmap_mux_closest_ops,
 125                         .flags = CLK_SET_RATE_PARENT,
 126                 },
 127 @@ -245,8 +250,8 @@ static struct clk_rcg pcm_src = {
 128                 .enable_mask = BIT(9),
 129                 .hw.init = &(struct clk_init_data){
 130                         .name = "pcm_src",
 131 -                       .parent_names = lcc_pxo_pll4,
 132 -                       .num_parents = 2,
 133 +                       .parent_data = lcc_pxo_pll4,
 134 +                       .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
 135                         .ops = &clk_rcg_ops,
 136                         .flags = CLK_SET_RATE_GATE,
 137                 },
 138 @@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = {
 139                 .enable_mask = BIT(11),
 140                 .hw.init = &(struct clk_init_data){
 141                         .name = "pcm_clk_out",
 142 -                       .parent_names = (const char *[]){ "pcm_src" },
 143 +                       .parent_hws = (const struct clk_hw*[]){
 144 +                               &pcm_src.clkr.hw,
 145 +                       },
 146                         .num_parents = 1,
 147                         .ops = &clk_branch_ops,
 148                         .flags = CLK_SET_RATE_PARENT,
 149 @@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = {
 150         },
 151  };
 152
 153 +static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
 154 +       { .hw = &pcm_clk_out.clkr.hw, },
 155 +       { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
 156 +};
 157 +
 158  static struct clk_regmap_mux pcm_clk = {
 159         .reg = 0x54,
 160         .shift = 10,
 161 @@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = {
 162         .clkr = {
 163                 .hw.init = &(struct clk_init_data){
 164                         .name = "pcm_clk",
 165 -                       .parent_names = (const char *[]){
 166 -                               "pcm_clk_out",
 167 -                               "pcm_codec_clk",
 168 -                       },
 169 -                       .num_parents = 2,
 170 +                       .parent_data = lcc_pcm_clk_out_codec_clk,
 171 +                       .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
 172                         .ops = &clk_regmap_mux_closest_ops,
 173                         .flags = CLK_SET_RATE_PARENT,
 174                 },
 175 @@ -325,18 +334,14 @@ static struct clk_rcg spdif_src = {
 176                 .enable_mask = BIT(9),
 177                 .hw.init = &(struct clk_init_data){
 178                         .name = "spdif_src",
 179 -                       .parent_names = lcc_pxo_pll4,
 180 -                       .num_parents = 2,
 181 +                       .parent_data = lcc_pxo_pll4,
 182 +                       .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
 183                         .ops = &clk_rcg_ops,
 184                         .flags = CLK_SET_RATE_GATE,
 185                 },
 186         },
 187  };
 188
 189 -static const char * const lcc_spdif_parents[] = {
 190 -       "spdif_src",
 191 -};
 192 -
 193  static struct clk_branch spdif_clk = {
 194         .halt_reg = 0xd4,
 195         .halt_bit = 1,
 196 @@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = {
 197                 .enable_mask = BIT(12),
 198                 .hw.init = &(struct clk_init_data){
 199                         .name = "spdif_clk",
 200 -                       .parent_names = lcc_spdif_parents,
 201 +                       .parent_hws = (const struct clk_hw*[]){
 202 +                               &spdif_src.clkr.hw,
 203 +                       },
 204                         .num_parents = 1,
 205                         .ops = &clk_branch_ops,
 206                         .flags = CLK_SET_RATE_PARENT,
 207 @@ -384,8 +391,8 @@ static struct clk_rcg ahbix_clk = {
 208                 .enable_mask = BIT(11),
 209                 .hw.init = &(struct clk_init_data){
 210                         .name = "ahbix",
 211 -                       .parent_names = lcc_pxo_pll4,
 212 -                       .num_parents = 2,
 213 +                       .parent_data = lcc_pxo_pll4,
 214 +                       .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
 215                         .ops = &clk_rcg_lcc_ops,
 216                 },
 217         },