target/linux/ipq806x/patches-6.1/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch

   1 From e95e825333eda345d812b461301dad50021d5487 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Sat, 26 Feb 2022 14:52:24 +0100
   4 Subject: [PATCH 04/14] clk: qcom: gcc-ipq806x: fix wrong naming for
   5  gcc_pxo_pll8_pll0
   6
   7 Parent gcc_pxo_pll8_pll0 had the parent definition and parent map
   8 swapped. Fix this naming error.
   9
  10 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  11 Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  12 Reviewed-by: Stephen Boyd <sboyd@kernel.org>
  13 Tested-by: Jonathan McDowell <noodles@earth.li>
  14 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  15 Link: https://lore.kernel.org/r/20220226135235.10051-5-ansuelsmth@gmail.com
  16 ---
  17  drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++----------
  18  1 file changed, 10 insertions(+), 10 deletions(-)
  19
  20 --- a/drivers/clk/qcom/gcc-ipq806x.c
  21 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  22 @@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[]
  23         "pll3",
  24  };
  25
  26 -static const struct parent_map gcc_pxo_pll8_pll0[] = {
  27 +static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
  28         { P_PXO, 0 },
  29         { P_PLL8, 3 },
  30         { P_PLL0, 2 }
  31  };
  32
  33 -static const char * const gcc_pxo_pll8_pll0_map[] = {
  34 +static const char * const gcc_pxo_pll8_pll0[] = {
  35         "pxo",
  36         "pll8_vote",
  37         "pll0_vote",
  38 @@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_s
  39         },
  40         .s = {
  41                 .src_sel_shift = 0,
  42 -               .parent_map = gcc_pxo_pll8_pll0,
  43 +               .parent_map = gcc_pxo_pll8_pll0_map,
  44         },
  45         .freq_tbl = clk_tbl_usb30_master,
  46         .clkr = {
  47 @@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_s
  48                 .enable_mask = BIT(11),
  49                 .hw.init = &(struct clk_init_data){
  50                         .name = "usb30_master_ref_src",
  51 -                       .parent_names = gcc_pxo_pll8_pll0_map,
  52 +                       .parent_names = gcc_pxo_pll8_pll0,
  53                         .num_parents = 3,
  54                         .ops = &clk_rcg_ops,
  55                         .flags = CLK_SET_RATE_GATE,
  56 @@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = {
  57         },
  58         .s = {
  59                 .src_sel_shift = 0,
  60 -               .parent_map = gcc_pxo_pll8_pll0,
  61 +               .parent_map = gcc_pxo_pll8_pll0_map,
  62         },
  63         .freq_tbl = clk_tbl_usb30_utmi,
  64         .clkr = {
  65 @@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = {
  66                 .enable_mask = BIT(11),
  67                 .hw.init = &(struct clk_init_data){
  68                         .name = "usb30_utmi_clk",
  69 -                       .parent_names = gcc_pxo_pll8_pll0_map,
  70 +                       .parent_names = gcc_pxo_pll8_pll0,
  71                         .num_parents = 3,
  72                         .ops = &clk_rcg_ops,
  73                         .flags = CLK_SET_RATE_GATE,
  74 @@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
  75         },
  76         .s = {
  77                 .src_sel_shift = 0,
  78 -               .parent_map = gcc_pxo_pll8_pll0,
  79 +               .parent_map = gcc_pxo_pll8_pll0_map,
  80         },
  81         .freq_tbl = clk_tbl_usb,
  82         .clkr = {
  83 @@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
  84                 .enable_mask = BIT(11),
  85                 .hw.init = &(struct clk_init_data){
  86                         .name = "usb_hs1_xcvr_src",
  87 -                       .parent_names = gcc_pxo_pll8_pll0_map,
  88 +                       .parent_names = gcc_pxo_pll8_pll0,
  89                         .num_parents = 3,
  90                         .ops = &clk_rcg_ops,
  91                         .flags = CLK_SET_RATE_GATE,
  92 @@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
  93         },
  94         .s = {
  95                 .src_sel_shift = 0,
  96 -               .parent_map = gcc_pxo_pll8_pll0,
  97 +               .parent_map = gcc_pxo_pll8_pll0_map,
  98         },
  99         .freq_tbl = clk_tbl_usb,
 100         .clkr = {
 101 @@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
 102                 .enable_mask = BIT(11),
 103                 .hw.init = &(struct clk_init_data){
 104                         .name = "usb_fs1_xcvr_src",
 105 -                       .parent_names = gcc_pxo_pll8_pll0_map,
 106 +                       .parent_names = gcc_pxo_pll8_pll0,
 107                         .num_parents = 3,
 108                         .ops = &clk_rcg_ops,
 109                         .flags = CLK_SET_RATE_GATE,