target/linux/ipq806x/patches-5.15/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch

   1 From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Mon, 17 Jan 2022 23:39:34 +0100
   4 Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
   5  ipq8064
   6
   7 Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
   8 Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
   9 for the secondary mux.
  10
  11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  12 Tested-by: Jonathan McDowell <noodles@earth.li>
  13 ---
  14  arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
  15  1 file changed, 32 insertions(+), 2 deletions(-)
  16
  17 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  18 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  19 @@ -301,6 +301,12 @@
  20         };
  21
  22         clocks {
  23 +               qsb: qsb {
  24 +                       compatible = "fixed-clock";
  25 +                       clock-frequency = <225000000>;
  26 +                       #clock-cells = <0>;
  27 +               };
  28 +
  29                 cxo_board: cxo_board {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32 @@ -503,11 +509,19 @@
  33                 acc0: clock-controller@2088000 {
  34                         compatible = "qcom,kpss-acc-v1";
  35                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  36 +                       clock-output-names = "acpu0_aux";
  37 +                       clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
  38 +                       clock-names = "pll8_vote", "pxo";
  39 +                       #clock-cells = <0>;
  40                 };
  41
  42                 acc1: clock-controller@2098000 {
  43                         compatible = "qcom,kpss-acc-v1";
  44                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  45 +                       clock-output-names = "acpu1_aux";
  46 +                       clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
  47 +                       clock-names = "pll8_vote", "pxo";
  48 +                       #clock-cells = <0>;
  49                 };
  50
  51                 adm_dma: dma-controller@18300000 {
  52 @@ -531,17 +545,23 @@
  53                 };
  54
  55                 saw0: regulator@2089000 {
  56 -                       compatible = "qcom,saw2";
  57 +                       compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  58                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
  59                         regulator;
  60                 };
  61
  62                 saw1: regulator@2099000 {
  63 -                       compatible = "qcom,saw2";
  64 +                       compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  65                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
  66                         regulator;
  67                 };
  68
  69 +               saw_l2: regulator@02012000 {
  70 +                       compatible = "qcom,saw2", "syscon";
  71 +                       reg = <0x02012000 0x1000>;
  72 +                       regulator;
  73 +               };
  74 +
  75                 gsbi1: gsbi@12440000 {
  76                         compatible = "qcom,gsbi-v1.0.0";
  77                         reg = <0x12440000 0x100>;
  78 @@ -920,6 +940,17 @@
  79                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
  80                         clock-names = "pll8_vote", "pxo";
  81                         clock-output-names = "acpu_l2_aux";
  82 +                       #clock-cells = <0>;
  83 +               };
  84 +
  85 +               kraitcc: clock-controller {
  86 +                       compatible = "qcom,krait-cc-v1";
  87 +                       clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
  88 +                                <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
  89 +                       clock-names = "hfpll0", "hfpll1", "hfpll_l2",
  90 +                                     "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
  91 +                                     "qsb", "pxo";
  92 +                       #clock-cells = <1>;
  93                 };
  94
  95                 lcc: clock-controller@28000000 {