target/linux/ipq806x/patches-5.15/106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch

   1 From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Mon, 18 Jul 2022 18:05:16 +0200
   4 Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant
   5
   6 Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for
   7 some additional pcie, sata and usb configuration values, additional
   8 reserved memory and serial output.
   9
  10 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  11 ---
  12  .../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi    | 37 ++++++++++
  13  arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi      | 69 +++++++++++++++++++
  14  2 files changed, 106 insertions(+)
  15  create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
  16  create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
  17
  18 --- /dev/null
  19 +++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
  20 @@ -0,0 +1,37 @@
  21 +// SPDX-License-Identifier: GPL-2.0
  22 +
  23 +#include "qcom-ipq8064-v2.0.dtsi"
  24 +
  25 +&rpm {
  26 +       smb208_regulators: regulators {
  27 +               compatible = "qcom,rpm-smb208-regulators";
  28 +
  29 +               smb208_s1a: s1a {
  30 +                       regulator-min-microvolt = <1050000>;
  31 +                       regulator-max-microvolt = <1150000>;
  32 +
  33 +                       qcom,switch-mode-frequency = <1200000>;
  34 +               };
  35 +
  36 +               smb208_s1b: s1b {
  37 +                       regulator-min-microvolt = <1050000>;
  38 +                       regulator-max-microvolt = <1150000>;
  39 +
  40 +                       qcom,switch-mode-frequency = <1200000>;
  41 +               };
  42 +
  43 +               smb208_s2a: s2a {
  44 +                       regulator-min-microvolt = < 800000>;
  45 +                       regulator-max-microvolt = <1250000>;
  46 +
  47 +                       qcom,switch-mode-frequency = <1200000>;
  48 +               };
  49 +
  50 +               smb208_s2b: s2b {
  51 +                       regulator-min-microvolt = < 800000>;
  52 +                       regulator-max-microvolt = <1250000>;
  53 +
  54 +                       qcom,switch-mode-frequency = <1200000>;
  55 +               };
  56 +       };
  57 +};
  58 --- /dev/null
  59 +++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
  60 @@ -0,0 +1,69 @@
  61 +// SPDX-License-Identifier: GPL-2.0
  62 +
  63 +#include "qcom-ipq8064.dtsi"
  64 +
  65 +/ {
  66 +       model = "Qualcomm Technologies, Inc. IPQ8064-v2.0";
  67 +
  68 +       aliases {
  69 +               serial0 = &gsbi4_serial;
  70 +       };
  71 +
  72 +       chosen {
  73 +               stdout-path = "serial0:115200n8";
  74 +       };
  75 +
  76 +       reserved-memory {
  77 +               #address-cells = <1>;
  78 +               #size-cells = <1>;
  79 +               ranges;
  80 +
  81 +               rsvd@41200000 {
  82 +                       reg = <0x41200000 0x300000>;
  83 +                       no-map;
  84 +               };
  85 +       };
  86 +};
  87 +
  88 +&gsbi4 {
  89 +       qcom,mode = <GSBI_PROT_I2C_UART>;
  90 +       status = "okay";
  91 +
  92 +       serial@16340000 {
  93 +               status = "okay";
  94 +       };
  95 +       /*
  96 +        * The i2c device on gsbi4 should not be enabled.
  97 +        * On ipq806x designs gsbi4 i2c is meant for exclusive
  98 +        * RPM usage. Turning this on in kernel manifests as
  99 +        * i2c failure for the RPM.
 100 +        */
 101 +};
 102 +
 103 +&pcie0 {
 104 +       compatible = "qcom,pcie-ipq8064-v2";
 105 +};
 106 +
 107 +&pcie1 {
 108 +       compatible = "qcom,pcie-ipq8064-v2";
 109 +};
 110 +
 111 +&pcie2 {
 112 +       compatible = "qcom,pcie-ipq8064-v2";
 113 +};
 114 +
 115 +&sata {
 116 +       ports-implemented = <0x1>;
 117 +};
 118 +
 119 +&ss_phy_0 {
 120 +       qcom,rx-eq = <2>;
 121 +       qcom,tx-deamp_3_5db = <32>;
 122 +       qcom,mpll = <5>;
 123 +};
 124 +
 125 +&ss_phy_1 {
 126 +       qcom,rx-eq = <2>;
 127 +       qcom,tx-deamp_3_5db = <32>;
 128 +       qcom,mpll = <5>;
 129 +};