target/linux/ipq806x/patches-4.9/0005-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platf.patch

   1 From f8d0939eca47f56449ec583810a6ff41a1caaa91 Mon Sep 17 00:00:00 2001
   2 From: Thomas Pedersen <twp@codeaurora.org>
   3 Date: Mon, 16 May 2016 17:58:54 -0700
   4 Subject: [PATCH 05/37] arm: qcom: dts: Enable NAND node on IPQ8064 AP148
   5  platform
   6
   7 Original patch by Archit Taneja.
   8
   9 Enable the NAND controller node on the AP148 platform. Provide pinmux
  10 information.
  11
  12 Signed-off-by: Archit Taneja <architt@codeaurora.org>
  13 Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
  14 ---
  15  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   42 ++++++++++++++++++++++++++++++
  16  1 file changed, 42 insertions(+)
  17
  18 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  19 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  20 @@ -38,6 +38,28 @@
  21                                         bias-none;
  22                                 };
  23                         };
  24 +                       nand_pins: nand_pins {
  25 +                               mux {
  26 +                                       pins = "gpio34", "gpio35", "gpio36",
  27 +                                              "gpio37", "gpio38", "gpio39",
  28 +                                              "gpio40", "gpio41", "gpio42",
  29 +                                              "gpio43", "gpio44", "gpio45",
  30 +                                              "gpio46", "gpio47";
  31 +                                       function = "nand";
  32 +                                       drive-strength = <10>;
  33 +                                       bias-disable;
  34 +                               };
  35 +                               pullups {
  36 +                                       pins = "gpio39";
  37 +                                       bias-pull-up;
  38 +                               };
  39 +                               hold {
  40 +                                       pins = "gpio40", "gpio41", "gpio42",
  41 +                                              "gpio43", "gpio44", "gpio45",
  42 +                                              "gpio46", "gpio47";
  43 +                                       bias-bus-hold;
  44 +                               };
  45 +                       };
  46                 };
  47
  48                 gsbi@16300000 {
  49 @@ -98,5 +120,25 @@
  50                         ports-implemented = <0x1>;
  51                         status = "ok";
  52                 };
  53 +
  54 +               nand@1ac00000 {
  55 +                       status = "ok";
  56 +
  57 +                       pinctrl-0 = <&nand_pins>;
  58 +                       pinctrl-names = "default";
  59 +
  60 +                       nandcs@0 {
  61 +                               compatible = "qcom,nandcs";
  62 +                               reg = <0>;
  63 +
  64 +                               nand-ecc-strength = <4>;
  65 +                               nand-ecc-step-size = <512>;
  66 +                               nand-bus-width = <8>;
  67 +                       };
  68 +               };
  69         };
  70  };
  71 +
  72 +&adm_dma {
  73 +       status = "ok";
  74 +};