target/linux/ipq806x/patches-4.4/135-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch

   1 From 39d42ce5031d2a4f92fa203b87acfbab340b15a2 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 20 Mar 2015 23:45:22 -0700
   4 Subject: [PATCH 2/2] clk: Avoid sending high rates to downstream clocks during
   5  set_rate
   6
   7 If a clock is on and we call clk_set_rate() on it we may get into
   8 a situation where the clock temporarily increases in rate
   9 dramatically while we walk the tree and call .set_rate() ops. For
  10 example, consider a case where a PLL feeds into a divider.
  11 Initially the divider is set to divide by 1 and the PLL is
  12 running fairly slow (100MHz). The downstream consumer of the
  13 divider output can only handle rates =< 400 MHz, but the divider
  14 can only choose between divisors of 1 and 4.
  15
  16  +-----+   +----------------+
  17  | PLL |-->| div 1 or div 4 |---> consumer device
  18  +-----+   +----------------+
  19
  20 To achieve a rate of 400MHz on the output of the divider, we
  21 would have to set the rate of the PLL to 1.6 GHz and then divide
  22 it by 4. The current code would set the PLL to 1.6GHz first while
  23 the divider is still set to 1, thus causing the downstream
  24 consumer of the clock to receive a few clock cycles of 1.6GHz
  25 clock (far beyond it's maximum acceptable rate). We should be
  26 changing the divider first before increasing the PLL rate to
  27 avoid this problem.
  28
  29 Therefore, set the rate of any child clocks that are increasing
  30 in rate from their current rate so that they can increase their
  31 dividers if necessary. We assume that there isn't such a thing as
  32 minimum rate requirements.
  33
  34 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  35 Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
  36 ---
  37  drivers/clk/clk.c | 34 ++++++++++++++++++++++------------
  38  1 file changed, 22 insertions(+), 12 deletions(-)
  39
  40 --- a/drivers/clk/clk.c
  41 +++ b/drivers/clk/clk.c
  42 @@ -1427,21 +1427,24 @@ static struct clk_core *clk_propagate_ra
  43   * walk down a subtree and set the new rates notifying the rate
  44   * change on the way
  45   */
  46 -static void clk_change_rate(struct clk_core *core)
  47 +static void
  48 +clk_change_rate(struct clk_core *core, unsigned long best_parent_rate)
  49  {
  50         struct clk_core *child;
  51         struct hlist_node *tmp;
  52         unsigned long old_rate;
  53 -       unsigned long best_parent_rate = 0;
  54         bool skip_set_rate = false;
  55         struct clk_core *old_parent;
  56
  57 -       old_rate = core->rate;
  58 +       hlist_for_each_entry(child, &core->children, child_node) {
  59 +               /* Skip children who will be reparented to another clock */
  60 +               if (child->new_parent && child->new_parent != core)
  61 +                       continue;
  62 +               if (child->new_rate > child->rate)
  63 +                       clk_change_rate(child, core->new_rate);
  64 +       }
  65
  66 -       if (core->new_parent)
  67 -               best_parent_rate = core->new_parent->rate;
  68 -       else if (core->parent)
  69 -               best_parent_rate = core->parent->rate;
  70 +       old_rate = core->rate;
  71
  72         if (core->new_parent && core->new_parent != core->parent) {
  73                 old_parent = __clk_set_parent_before(core, core->new_parent);
  74 @@ -1467,7 +1470,7 @@ static void clk_change_rate(struct clk_c
  75
  76         trace_clk_set_rate_complete(core, core->new_rate);
  77
  78 -       core->rate = clk_recalc(core, best_parent_rate);
  79 +       core->rate = core->new_rate;
  80
  81         if (core->notifier_count && old_rate != core->rate)
  82                 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
  83 @@ -1483,12 +1486,13 @@ static void clk_change_rate(struct clk_c
  84                 /* Skip children who will be reparented to another clock */
  85                 if (child->new_parent && child->new_parent != core)
  86                         continue;
  87 -               clk_change_rate(child);
  88 +               if (child->new_rate != child->rate)
  89 +                       clk_change_rate(child, core->new_rate);
  90         }
  91
  92         /* handle the new child who might not be in core->children yet */
  93 -       if (core->new_child)
  94 -               clk_change_rate(core->new_child);
  95 +       if (core->new_child && core->new_child->new_rate != core->new_child->rate)
  96 +               clk_change_rate(core->new_child, core->new_rate);
  97  }
  98
  99  static int clk_core_set_rate_nolock(struct clk_core *core,
 100 @@ -1497,6 +1501,7 @@ static int clk_core_set_rate_nolock(stru
 101         struct clk_core *top, *fail_clk;
 102         unsigned long rate = req_rate;
 103         int ret = 0;
 104 +       unsigned long parent_rate;
 105
 106         if (!core)
 107                 return 0;
 108 @@ -1522,8 +1527,13 @@ static int clk_core_set_rate_nolock(stru
 109                 return -EBUSY;
 110         }
 111
 112 +       if (top->parent)
 113 +               parent_rate = top->parent->rate;
 114 +       else
 115 +               parent_rate = 0;
 116 +
 117         /* change the rates */
 118 -       clk_change_rate(top);
 119 +       clk_change_rate(top, parent_rate);
 120
 121         core->req_rate = req_rate;
 122