ipq806x: set v4.9 as default
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.4 / 010-5-watchdog-qcom-add-option-for-standalone-watchdog-not-in-timer-block.patch
1 From f0d9d0f4b44ae5503ea368e7f066b20f12ca1d37 Mon Sep 17 00:00:00 2001
2 From: Matthew McClintock <mmcclint@codeaurora.org>
3 Date: Wed, 29 Jun 2016 10:50:01 -0700
4 Subject: watchdog: qcom: add option for standalone watchdog not in timer block
5
6 Commit 0dfd582e026a ("watchdog: qcom: use timer devicetree
7 binding") moved to use the watchdog as a subset timer
8 register block. Some devices have the watchdog completely
9 standalone with slightly different register offsets as
10 well so let's account for the differences here.
11
12 The existing "kpss-standalone" compatible string doesn't
13 make it entirely clear exactly what the device is so
14 rename to "kpss-wdt" to reflect watchdog timer
15 functionality. Also update ipq4019 DTS with an SoC
16 specific compatible.
17
18 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
19 Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
20 Reviewed-by: Guenter Roeck <linux@roeck-us.net>
21 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
22 Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
23 ---
24 .../devicetree/bindings/watchdog/qcom-wdt.txt | 2 +
25 arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
26 drivers/watchdog/qcom-wdt.c | 64 ++++++++++++++++------
27 3 files changed, 51 insertions(+), 17 deletions(-)
28
29 --- a/drivers/watchdog/qcom-wdt.c
30 +++ b/drivers/watchdog/qcom-wdt.c
31 @@ -18,19 +18,42 @@
32 #include <linux/of.h>
33 #include <linux/platform_device.h>
34 #include <linux/watchdog.h>
35 +#include <linux/of_device.h>
36
37 -#define WDT_RST 0x38
38 -#define WDT_EN 0x40
39 -#define WDT_STS 0x44
40 -#define WDT_BITE_TIME 0x5C
41 +enum wdt_reg {
42 + WDT_RST,
43 + WDT_EN,
44 + WDT_STS,
45 + WDT_BITE_TIME,
46 +};
47 +
48 +static const u32 reg_offset_data_apcs_tmr[] = {
49 + [WDT_RST] = 0x38,
50 + [WDT_EN] = 0x40,
51 + [WDT_STS] = 0x44,
52 + [WDT_BITE_TIME] = 0x5C,
53 +};
54 +
55 +static const u32 reg_offset_data_kpss[] = {
56 + [WDT_RST] = 0x4,
57 + [WDT_EN] = 0x8,
58 + [WDT_STS] = 0xC,
59 + [WDT_BITE_TIME] = 0x14,
60 +};
61
62 struct qcom_wdt {
63 struct watchdog_device wdd;
64 struct clk *clk;
65 unsigned long rate;
66 void __iomem *base;
67 + const u32 *layout;
68 };
69
70 +static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
71 +{
72 + return wdt->base + wdt->layout[reg];
73 +}
74 +
75 static inline
76 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
77 {
78 @@ -41,10 +64,10 @@ static int qcom_wdt_start(struct watchdo
79 {
80 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
81
82 - writel(0, wdt->base + WDT_EN);
83 - writel(1, wdt->base + WDT_RST);
84 - writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME);
85 - writel(1, wdt->base + WDT_EN);
86 + writel(0, wdt_addr(wdt, WDT_EN));
87 + writel(1, wdt_addr(wdt, WDT_RST));
88 + writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
89 + writel(1, wdt_addr(wdt, WDT_EN));
90 return 0;
91 }
92
93 @@ -52,7 +75,7 @@ static int qcom_wdt_stop(struct watchdog
94 {
95 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
96
97 - writel(0, wdt->base + WDT_EN);
98 + writel(0, wdt_addr(wdt, WDT_EN));
99 return 0;
100 }
101
102 @@ -60,7 +83,7 @@ static int qcom_wdt_ping(struct watchdog
103 {
104 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
105
106 - writel(1, wdt->base + WDT_RST);
107 + writel(1, wdt_addr(wdt, WDT_RST));
108 return 0;
109 }
110
111 @@ -83,10 +106,10 @@ static int qcom_wdt_restart(struct watch
112 */
113 timeout = 128 * wdt->rate / 1000;
114
115 - writel(0, wdt->base + WDT_EN);
116 - writel(1, wdt->base + WDT_RST);
117 - writel(timeout, wdt->base + WDT_BITE_TIME);
118 - writel(1, wdt->base + WDT_EN);
119 + writel(0, wdt_addr(wdt, WDT_EN));
120 + writel(1, wdt_addr(wdt, WDT_RST));
121 + writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
122 + writel(1, wdt_addr(wdt, WDT_EN));
123
124 /*
125 * Actually make sure the above sequence hits hardware before sleeping.
126 @@ -119,9 +142,16 @@ static int qcom_wdt_probe(struct platfor
127 struct qcom_wdt *wdt;
128 struct resource *res;
129 struct device_node *np = pdev->dev.of_node;
130 + const u32 *regs;
131 u32 percpu_offset;
132 int ret;
133
134 + regs = of_device_get_match_data(&pdev->dev);
135 + if (!regs) {
136 + dev_err(&pdev->dev, "Unsupported QCOM WDT module\n");
137 + return -ENODEV;
138 + }
139 +
140 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
141 if (!wdt)
142 return -ENOMEM;
143 @@ -172,6 +202,7 @@ static int qcom_wdt_probe(struct platfor
144 wdt->wdd.min_timeout = 1;
145 wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
146 wdt->wdd.parent = &pdev->dev;
147 + wdt->layout = regs;
148
149 if (readl(wdt->base + WDT_STS) & 1)
150 wdt->wdd.bootstatus = WDIOF_CARDRESET;
151 @@ -208,8 +239,9 @@ static int qcom_wdt_remove(struct platfo
152 }
153
154 static const struct of_device_id qcom_wdt_of_table[] = {
155 - { .compatible = "qcom,kpss-timer" },
156 - { .compatible = "qcom,scss-timer" },
157 + { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
158 + { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
159 + { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
160 { },
161 };
162 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);