ipq806x: convert to new LED color/function format where possible
[openwrt/openwrt.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065-tr4400-v2.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include "qcom-ipq8065-smb208.dtsi"
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6
7 / {
8 model = "Arris TR4400 v2";
9 compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
10
11 memory@0 {
12 reg = <0x42000000 0x1e000000>;
13 device_type = "memory";
14 };
15
16 aliases {
17 led-boot = &led_status_blue;
18 led-failsafe = &led_status_red;
19 led-running = &led_status_blue;
20 led-upgrade = &led_status_red;
21 };
22
23 chosen {
24 bootargs = "rootfstype=squashfs noinitrd";
25 };
26
27 keys {
28 compatible = "gpio-keys";
29 pinctrl-0 = <&button_pins>;
30 pinctrl-names = "default";
31
32 reset {
33 label = "reset";
34 gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_RESTART>;
36 debounce-interval = <60>;
37 wakeup-source;
38 };
39
40 wps {
41 label = "wps";
42 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
43 linux,code = <KEY_WPS_BUTTON>;
44 debounce-interval = <60>;
45 wakeup-source;
46 };
47 };
48
49 leds {
50 compatible = "gpio-leds";
51 pinctrl-0 = <&led_pins>;
52 pinctrl-names = "default";
53
54 led_status_red: status_red {
55 function = LED_FUNCTION_STATUS;
56 color = <LED_COLOR_ID_RED>;
57 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
58 };
59
60 led_status_blue: status_blue {
61 function = LED_FUNCTION_STATUS;
62 color = <LED_COLOR_ID_BLUE>;
63 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
64 };
65 };
66 };
67
68 &qcom_pinmux {
69 button_pins: button_pins {
70 mux {
71 pins = "gpio6", "gpio54";
72 function = "gpio";
73 drive-strength = <2>;
74 bias-pull-up;
75 };
76 };
77
78 led_pins: led_pins {
79 mux {
80 pins = "gpio7", "gpio8";
81 function = "gpio";
82 drive-strength = <2>;
83 bias-pull-down;
84 };
85 };
86
87 rgmii2_pins: rgmii2-pins {
88 tx {
89 pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
90 input-disable;
91 };
92 };
93
94 spi_pins: spi_pins {
95 cs {
96 pins = "gpio20";
97 drive-strength = <12>;
98 };
99 };
100 };
101
102 &gsbi5 {
103 qcom,mode = <GSBI_PROT_SPI>;
104 status = "okay";
105
106 spi@1a280000 {
107 status = "okay";
108
109 pinctrl-0 = <&spi_pins>;
110 pinctrl-names = "default";
111
112 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
113
114 flash@0 {
115 compatible = "everspin,mr25h256";
116 spi-max-frequency = <40000000>;
117 reg = <0>;
118 };
119 };
120 };
121
122 &nand {
123 status = "okay";
124
125 nand@0 {
126 reg = <0>;
127 compatible = "qcom,nandcs";
128
129 nand-ecc-strength = <4>;
130 nand-bus-width = <8>;
131 nand-ecc-step-size = <512>;
132
133 qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
134
135 partitions {
136 compatible = "fixed-partitions";
137 #address-cells = <1>;
138 #size-cells = <1>;
139
140 partition@0 {
141 label = "0:SBL1";
142 reg = <0x0000000 0x0040000>;
143 read-only;
144 };
145 partition@40000 {
146 label = "0:MIBIB";
147 reg = <0x0040000 0x0140000>;
148 read-only;
149 };
150 partition@180000 {
151 label = "0:SBL2";
152 reg = <0x0180000 0x0140000>;
153 read-only;
154 };
155 partition@2c0000 {
156 label = "0:SBL3";
157 reg = <0x02c0000 0x0280000>;
158 read-only;
159 };
160 partition@540000 {
161 label = "0:DDRCONFIG";
162 reg = <0x0540000 0x0120000>;
163 read-only;
164 };
165 partition@660000 {
166 label = "0:SSD";
167 reg = <0x0660000 0x0120000>;
168 read-only;
169 };
170 partition@780000 {
171 label = "0:TZ";
172 reg = <0x0780000 0x0280000>;
173 read-only;
174 };
175 partition@a00000 {
176 label = "0:RPM";
177 reg = <0x0a00000 0x0280000>;
178 read-only;
179 };
180 partition@c80000 {
181 label = "0:APPSBL";
182 reg = <0x0c80000 0x0500000>;
183 read-only;
184 };
185 partition@1180000 {
186 label = "0:APPSBLENV";
187 reg = <0x1180000 0x0080000>;
188 };
189 partition@1200000 {
190 label = "0:ART";
191 reg = <0x1200000 0x0140000>;
192 read-only;
193
194 nvmem-layout {
195 compatible = "fixed-layout";
196 #address-cells = <1>;
197 #size-cells = <1>;
198
199 precal_ART_1000: precal@1000 {
200 reg = <0x1000 0x2f20>;
201 };
202 precal_ART_5000: precal@5000 {
203 reg = <0x5000 0x2f20>;
204 };
205 };
206 };
207 stock_partition@1340000 {
208 label = "stock_rootfs";
209 reg = <0x1340000 0x4000000>;
210
211 compatible = "fixed-partitions";
212 #address-cells = <1>;
213 #size-cells = <1>;
214
215 partition@0 {
216 label = "extra";
217 reg = <0x0 0x4000000>;
218 };
219 };
220 partition@5340000 {
221 label = "0:BOOTCONFIG";
222 reg = <0x5340000 0x0060000>;
223 read-only;
224 };
225 partition@53a0000 {
226 label = "0:SBL2_1";
227 reg = <0x53a0000 0x0140000>;
228 read-only;
229 };
230 partition@54e0000 {
231 label = "0:SBL3_1";
232 reg = <0x54e0000 0x0280000>;
233 read-only;
234 };
235 partition@5760000 {
236 label = "0:DDRCONFIG_1";
237 reg = <0x5760000 0x0120000>;
238 read-only;
239 };
240 partition@5880000 {
241 label = "0:SSD_1";
242 reg = <0x5880000 0x0120000>;
243 read-only;
244 };
245 partition@59a0000 {
246 label = "0:TZ_1";
247 reg = <0x59a0000 0x0280000>;
248 read-only;
249 };
250 partition@5c20000 {
251 label = "0:RPM_1";
252 reg = <0x5c20000 0x0280000>;
253 read-only;
254 };
255 partition@5ea0000 {
256 label = "0:BOOTCONFIG1";
257 reg = <0x5ea0000 0x0060000>;
258 read-only;
259 };
260 partition@5f00000 {
261 label = "0:APPSBL_1";
262 reg = <0x5f00000 0x0500000>;
263 read-only;
264 };
265 stock_partition@6400000 {
266 label = "stock_rootfs_1";
267 reg = <0x6400000 0x4000000>;
268
269 compatible = "fixed-partitions";
270 #address-cells = <1>;
271 #size-cells = <1>;
272
273 partition@0 {
274 label = "fw_env";
275 reg = <0x0 0x100000>;
276
277 nvmem-layout {
278 compatible = "fixed-layout";
279 #address-cells = <1>;
280 #size-cells = <1>;
281
282 macaddr_fw_env_0: macaddr@0 {
283 reg = <0x00 0x6>;
284 };
285 macaddr_fw_env_6: macaddr@6 {
286 reg = <0x06 0x6>;
287 };
288 macaddr_fw_env_c: macaddr@c {
289 reg = <0x0c 0x6>;
290 };
291 macaddr_fw_env_12: macaddr@12 {
292 reg = <0x12 0x6>;
293 };
294 macaddr_fw_env_18: macaddr@18 {
295 reg = <0x18 0x6>;
296 };
297 };
298 };
299
300 partition@100000 {
301 label = "ubi";
302 reg = <0x100000 0x9b00000>;
303 };
304 };
305 stock_partition@a400000 {
306 label = "stock_fw_env";
307 reg = <0xa400000 0x0100000>;
308 };
309 stock_partition@a500000 {
310 label = "stock_config";
311 reg = <0xa500000 0x0800000>;
312 };
313 stock_partition@ad00000 {
314 label = "stock_PKI";
315 reg = <0xad00000 0x0200000>;
316 };
317 stock_partition@af00000 {
318 label = "stock_scfgmgr";
319 reg = <0xaf00000 0x0100000>;
320 };
321 };
322 };
323 };
324
325 &mdio0 {
326 status = "okay";
327
328 pinctrl-0 = <&mdio0_pins>;
329 pinctrl-names = "default";
330
331 switch@10 {
332 compatible = "qca,qca8337";
333 #address-cells = <1>;
334 #size-cells = <0>;
335 reg = <0x10>;
336
337 ports {
338 #address-cells = <1>;
339 #size-cells = <0>;
340
341 port@0 {
342 reg = <0>;
343 label = "cpu";
344 ethernet = <&gmac0>;
345 phy-mode = "rgmii";
346 tx-internal-delay-ps = <1000>;
347 rx-internal-delay-ps = <1000>;
348
349 fixed-link {
350 speed = <1000>;
351 full-duplex;
352 };
353 };
354
355 port@1 {
356 reg = <1>;
357 label = "lan1";
358 phy-mode = "internal";
359 phy-handle = <&phy_port1>;
360 };
361
362 port@2 {
363 reg = <2>;
364 label = "lan2";
365 phy-mode = "internal";
366 phy-handle = <&phy_port2>;
367 };
368
369 port@3 {
370 reg = <3>;
371 label = "lan3";
372 phy-mode = "internal";
373 phy-handle = <&phy_port3>;
374 };
375
376 port@4 {
377 reg = <4>;
378 label = "lan4";
379 phy-mode = "internal";
380 phy-handle = <&phy_port4>;
381 };
382
383 port@6 {
384 reg = <6>;
385 label = "cpu";
386 ethernet = <&gmac1>;
387 phy-mode = "sgmii";
388 qca,sgmii-enable-pll;
389
390 fixed-link {
391 speed = <1000>;
392 full-duplex;
393 };
394 };
395 };
396
397 mdio {
398 #address-cells = <1>;
399 #size-cells = <0>;
400
401 phy_port1: phy@0 {
402 reg = <0>;
403 };
404
405 phy_port2: phy@1 {
406 reg = <1>;
407 };
408
409 phy_port3: phy@2 {
410 reg = <2>;
411 };
412
413 phy_port4: phy@3 {
414 reg = <3>;
415 };
416 };
417 };
418
419 phy7: ethernet-phy@7 {
420 reg = <7>;
421 };
422 };
423
424 &gmac0 {
425 status = "okay";
426 phy-mode = "rgmii";
427 qcom,id = <0>;
428
429 nvmem-cells = <&macaddr_fw_env_18>;
430 nvmem-cell-names = "mac-address";
431
432 pinctrl-0 = <&rgmii2_pins>;
433 pinctrl-names = "default";
434
435 fixed-link {
436 speed = <1000>;
437 full-duplex;
438 };
439 };
440
441 &gmac1 {
442 status = "okay";
443 phy-mode = "sgmii";
444 qcom,id = <1>;
445
446 nvmem-cells = <&macaddr_fw_env_0>;
447 nvmem-cell-names = "mac-address";
448
449 fixed-link {
450 speed = <1000>;
451 full-duplex;
452 };
453 };
454
455 &gmac3 {
456 status = "okay";
457 phy-mode = "sgmii";
458 qcom,id = <3>;
459 phy-handle = <&phy7>;
460
461 nvmem-cells = <&macaddr_fw_env_6>;
462 nvmem-cell-names = "mac-address";
463 };
464
465 &adm_dma {
466 status = "okay";
467 };
468
469 &hs_phy_1 {
470 status = "okay";
471 };
472
473 &ss_phy_1 {
474 status = "okay";
475 };
476
477 &usb3_1 {
478 status = "okay";
479 };
480
481 &pcie0 {
482 status = "okay";
483 reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
484 pinctrl-0 = <&pcie0_pins>;
485 pinctrl-names = "default";
486
487 bridge@0,0 {
488 reg = <0x00000000 0 0 0 0>;
489 #address-cells = <3>;
490 #size-cells = <2>;
491 ranges;
492
493 wifi0: wifi@1,0 {
494 compatible = "pci168c,0046";
495 reg = <0x00010000 0 0 0 0>;
496
497 nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
498 nvmem-cell-names = "pre-calibration", "mac-address";
499 };
500 };
501 };
502
503 &pcie1 {
504 status = "okay";
505 reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
506 pinctrl-0 = <&pcie1_pins>;
507 pinctrl-names = "default";
508 max-link-speed = <1>;
509
510 bridge@0,0 {
511 reg = <0x00000000 0 0 0 0>;
512 #address-cells = <3>;
513 #size-cells = <2>;
514 ranges;
515
516 wifi1: wifi@1,0 {
517 compatible = "pci168c,0040";
518 reg = <0x00010000 0 0 0 0>;
519
520 nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
521 nvmem-cell-names = "pre-calibration", "mac-address";
522 };
523 };
524 };