target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #include "qcom-ipq8065-smb208.dtsi"
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/leds/common.h>
   6
   7 / {
   8         model = "Askey RT4230W REV6";
   9         compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
  10
  11         memory@0 {
  12                 reg = <0x42000000 0x3e000000>;
  13                 device_type = "memory";
  14         };
  15
  16         aliases {
  17                 led-boot = &ledctrl3;
  18                 led-failsafe = &ledctrl1;
  19                 led-running = &ledctrl2;
  20                 led-upgrade = &ledctrl3;
  21         };
  22
  23         chosen {
  24                 bootargs = "rootfstype=squashfs noinitrd";
  25         };
  26
  27         keys {
  28                 compatible = "gpio-keys";
  29                 pinctrl-0 = <&button_pins>;
  30                 pinctrl-names = "default";
  31
  32                 reset {
  33                         label = "reset";
  34                         gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  35                         linux,code = <KEY_RESTART>;
  36                 };
  37
  38                 wps {
  39                         label = "wps";
  40                         gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  41                         linux,code = <KEY_WPS_BUTTON>;
  42                 };
  43         };
  44
  45         leds {
  46                 compatible = "gpio-leds";
  47                 pinctrl-0 = <&led_pins>;
  48                 pinctrl-names = "default";
  49
  50                 ledctrl1: ledctrl1 {
  51                         label = "ledctrl1";
  52                         gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  53                 };
  54
  55                 ledctrl2: ledctrl2 {
  56                         label = "ledctrl2";
  57                         gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  58                 };
  59
  60                 ledctrl3: ledctrl3 {
  61                         label = "ledctrl3";
  62                         gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  63                 };
  64         };
  65 };
  66
  67 &qcom_pinmux {
  68         button_pins: button_pins {
  69                 mux {
  70                         pins = "gpio54", "gpio68";
  71                         function = "gpio";
  72                         drive-strength = <2>;
  73                         bias-pull-up;
  74                 };
  75         };
  76
  77         led_pins: led_pins {
  78                 mux {
  79                         pins = "gpio22", "gpio23", "gpio24";
  80                         function = "gpio";
  81                         drive-strength = <2>;
  82                         bias-pull-down;
  83                 };
  84         };
  85
  86         rgmii2_pins: rgmii2-pins {
  87                 mux {
  88                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
  89                                 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
  90                         function = "rgmii2";
  91                         drive-strength = <8>;
  92                         bias-disable;
  93                 };
  94
  95                 tx {
  96                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  97                         input-disable;
  98                 };
  99         };
 100
 101         spi_pins: spi_pins {
 102                 cs {
 103                         pins = "gpio20";
 104                         drive-strength = <12>;
 105                 };
 106         };
 107 };
 108
 109 &gsbi5 {
 110         qcom,mode = <GSBI_PROT_SPI>;
 111         status = "okay";
 112
 113         spi@1a280000 {
 114                 status = "okay";
 115
 116                 pinctrl-0 = <&spi_pins>;
 117                 pinctrl-names = "default";
 118
 119                 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
 120
 121                 flash@0 {
 122                         compatible = "everspin,mr25h256";
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         spi-max-frequency = <40000000>;
 126                         reg = <0>;
 127                 };
 128         };
 129 };
 130
 131 &nand {
 132         status = "okay";
 133
 134         nand@0 {
 135                 reg = <0>;
 136                 compatible = "qcom,nandcs";
 137
 138                 nand-ecc-strength = <4>;
 139                 nand-bus-width = <8>;
 140                 nand-ecc-step-size = <512>;
 141
 142                 qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>;
 143
 144                 partitions {
 145                         compatible = "fixed-partitions";
 146                         #address-cells = <1>;
 147                         #size-cells = <1>;
 148
 149                         partition@0 {
 150                                 label = "0:SBL1";
 151                                 reg = <0x0000000 0x0040000>;
 152                                 read-only;
 153                         };
 154
 155                         partition@40000 {
 156                                 label = "0:MIBIB";
 157                                 reg = <0x0040000 0x0140000>;
 158                                 read-only;
 159                         };
 160
 161                         partition@180000 {
 162                                 label = "0:SBL2";
 163                                 reg = <0x0180000 0x0140000>;
 164                                 read-only;
 165                         };
 166
 167                         partition@2c0000 {
 168                                 label = "0:SBL3";
 169                                 reg = <0x02c0000 0x0280000>;
 170                                 read-only;
 171                         };
 172
 173                         partition@540000 {
 174                                 label = "0:DDRCONFIG";
 175                                 reg = <0x0540000 0x0120000>;
 176                                 read-only;
 177                         };
 178
 179                         partition@660000 {
 180                                 label = "0:SSD";
 181                                 reg = <0x0660000 0x0120000>;
 182                                 read-only;
 183                         };
 184
 185                         partition@780000 {
 186                                 label = "0:TZ";
 187                                 reg = <0x0780000 0x0280000>;
 188                                 read-only;
 189                         };
 190
 191                         partition@a00000 {
 192                                 label = "0:RPM";
 193                                 reg = <0x0a00000 0x0280000>;
 194                                 read-only;
 195                         };
 196
 197                         partition@c80000 {
 198                                 label = "0:APPSBL";
 199                                 reg = <0x0c80000 0x0500000>;
 200                                 read-only;
 201                         };
 202
 203                         partition@1180000 {
 204                                 label = "0:APPSBLENV";
 205                                 reg = <0x1180000 0x0080000>;
 206                         };
 207
 208                         partition@1200000 {
 209                                 label = "0:ART";
 210                                 reg = <0x1200000 0x0140000>;
 211                                 read-only;
 212                                 compatible = "nvmem-cells";
 213                                 #address-cells = <1>;
 214                                 #size-cells = <1>;
 215
 216                                 macaddr_ART_0: macaddr@0 {
 217                                         reg = <0x0 0x6>;
 218                                 };
 219
 220                                 macaddr_ART_6: macaddr@6 {
 221                                         reg = <0x6 0x6>;
 222                                 };
 223
 224                                 precal_ART_1000: precal@1000 {
 225                                         reg = <0x1000 0x2f20>;
 226                                 };
 227
 228                                 precal_ART_5000: precal@5000 {
 229                                         reg = <0x5000 0x2f20>;
 230                                 };
 231                         };
 232
 233                         partition@1340000 {
 234                                 label = "0:BOOTCONFIG";
 235                                 reg = <0x1340000 0x0060000>;
 236                                 read-only;
 237                         };
 238
 239                         partition@13a0000 {
 240                                 label = "0:SBL2_1";
 241                                 reg = <0x13a0000 0x0140000>;
 242                                 read-only;
 243                         };
 244
 245                         partition@14e0000 {
 246                                 label = "0:SBL3_1";
 247                                 reg = <0x14e0000 0x0280000>;
 248                                 read-only;
 249                         };
 250
 251                         partition@1760000 {
 252                                 label = "0:DDRCONFIG_1";
 253                                 reg = <0x1760000 0x0120000>;
 254                                 read-only;
 255                         };
 256
 257                         partition@1880000 {
 258                                 label = "0:SSD_1";
 259                                 reg = <0x1880000 0x0120000>;
 260                                 read-only;
 261                         };
 262
 263                         partition@19a0000 {
 264                                 label = "0:TZ_1";
 265                                 reg = <0x19a0000 0x0280000>;
 266                                 read-only;
 267                         };
 268
 269                         partition@1c20000 {
 270                                 label = "0:RPM_1";
 271                                 reg = <0x1c20000 0x0280000>;
 272                                 read-only;
 273                         };
 274
 275                         partition@1ea0000 {
 276                                 label = "0:BOOTCONFIG1";
 277                                 reg = <0x1ea0000 0x0060000>;
 278                                 read-only;
 279                         };
 280
 281                         partition@1f00000 {
 282                                 label = "0:APPSBL_1";
 283                                 reg = <0x1f00000 0x0500000>;
 284                                 read-only;
 285                         };
 286
 287                         partition@2400000 {
 288                                 label = "ubi";
 289                                 reg = <0x2400000 0x1a000000>;
 290                         };
 291                 };
 292         };
 293 };
 294
 295 &mdio0 {
 296         status = "okay";
 297
 298         pinctrl-0 = <&mdio0_pins>;
 299         pinctrl-names = "default";
 300
 301         switch@10 {
 302                 compatible = "qca,qca8337";
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 reg = <0x10>;
 306
 307                 ports {
 308                         #address-cells = <1>;
 309                         #size-cells = <0>;
 310
 311                         port@0 {
 312                                 reg = <0>;
 313                                 label = "cpu";
 314                                 ethernet = <&gmac0>;
 315                                 phy-mode = "rgmii";
 316                                 tx-internal-delay-ps = <1000>;
 317                                 rx-internal-delay-ps = <1000>;
 318
 319                                 fixed-link {
 320                                         speed = <1000>;
 321                                         full-duplex;
 322                                 };
 323                         };
 324
 325                         port@1 {
 326                                 reg = <1>;
 327                                 label = "wan";
 328                                 phy-mode = "internal";
 329                                 phy-handle = <&phy_port1>;
 330
 331                                 leds {
 332                                         #address-cells = <1>;
 333                                         #size-cells = <0>;
 334
 335                                         led@0 {
 336                                                 reg = <0>;
 337                                                 color = <LED_COLOR_ID_GREEN>;
 338                                                 function = LED_FUNCTION_WAN;
 339                                                 default-state = "keep";
 340                                         };
 341
 342                                         led@1 {
 343                                                 reg = <1>;
 344                                                 color = <LED_COLOR_ID_AMBER>;
 345                                                 function = LED_FUNCTION_WAN;
 346                                                 default-state = "keep";
 347                                         };
 348                                 };
 349                         };
 350
 351                         port@2 {
 352                                 reg = <2>;
 353                                 label = "lan1";
 354                                 phy-mode = "internal";
 355                                 phy-handle = <&phy_port2>;
 356
 357                                 leds {
 358                                         #address-cells = <1>;
 359                                         #size-cells = <0>;
 360
 361                                         led@0 {
 362                                                 reg = <0>;
 363                                                 color = <LED_COLOR_ID_GREEN>;
 364                                                 function = LED_FUNCTION_LAN;
 365                                                 default-state = "keep";
 366                                         };
 367
 368                                         led@1 {
 369                                                 reg = <1>;
 370                                                 color = <LED_COLOR_ID_AMBER>;
 371                                                 function = LED_FUNCTION_LAN;
 372                                                 default-state = "keep";
 373                                         };
 374                                 };
 375                         };
 376
 377                         port@3 {
 378                                 reg = <3>;
 379                                 label = "lan2";
 380                                 phy-mode = "internal";
 381                                 phy-handle = <&phy_port3>;
 382
 383                                 leds {
 384                                         #address-cells = <1>;
 385                                         #size-cells = <0>;
 386
 387                                         led@0 {
 388                                                 reg = <0>;
 389                                                 color = <LED_COLOR_ID_GREEN>;
 390                                                 function = LED_FUNCTION_LAN;
 391                                                 default-state = "keep";
 392                                         };
 393
 394                                         led@1 {
 395                                                 reg = <1>;
 396                                                 color = <LED_COLOR_ID_AMBER>;
 397                                                 function = LED_FUNCTION_LAN;
 398                                                 default-state = "keep";
 399                                         };
 400                                 };
 401                         };
 402
 403                         port@4 {
 404                                 reg = <4>;
 405                                 label = "lan3";
 406                                 phy-mode = "internal";
 407                                 phy-handle = <&phy_port4>;
 408
 409                                 leds {
 410                                         #address-cells = <1>;
 411                                         #size-cells = <0>;
 412
 413                                         led@0 {
 414                                                 reg = <0>;
 415                                                 color = <LED_COLOR_ID_GREEN>;
 416                                                 function = LED_FUNCTION_LAN;
 417                                                 default-state = "keep";
 418                                         };
 419
 420                                         led@1 {
 421                                                 reg = <1>;
 422                                                 color = <LED_COLOR_ID_AMBER>;
 423                                                 function = LED_FUNCTION_LAN;
 424                                                 default-state = "keep";
 425                                         };
 426                                 };
 427                         };
 428
 429                         port@5 {
 430                                 reg = <5>;
 431                                 label = "lan4";
 432                                 phy-mode = "internal";
 433                                 phy-handle = <&phy_port5>;
 434
 435                                 leds {
 436                                         #address-cells = <1>;
 437                                         #size-cells = <0>;
 438
 439                                         led@0 {
 440                                                 reg = <0>;
 441                                                 color = <LED_COLOR_ID_GREEN>;
 442                                                 function = LED_FUNCTION_LAN;
 443                                                 default-state = "keep";
 444                                         };
 445
 446                                         led@1 {
 447                                                 reg = <1>;
 448                                                 color = <LED_COLOR_ID_AMBER>;
 449                                                 function = LED_FUNCTION_LAN;
 450                                                 default-state = "keep";
 451                                         };
 452                                 };
 453                         };
 454
 455                         port@6 {
 456                                 reg = <6>;
 457                                 label = "cpu";
 458                                 ethernet = <&gmac1>;
 459                                 phy-mode = "sgmii";
 460                                 qca,sgmii-enable-pll;
 461
 462                                 fixed-link {
 463                                         speed = <1000>;
 464                                         full-duplex;
 465                                 };
 466                         };
 467                 };
 468
 469                 mdio {
 470                         #address-cells = <1>;
 471                         #size-cells = <0>;
 472
 473                         phy_port1: phy@0 {
 474                                 reg = <0>;
 475                         };
 476
 477                         phy_port2: phy@1 {
 478                                 reg = <1>;
 479                         };
 480
 481                         phy_port3: phy@2 {
 482                                 reg = <2>;
 483                         };
 484
 485                         phy_port4: phy@3 {
 486                                 reg = <3>;
 487                         };
 488
 489                         phy_port5: phy@4 {
 490                                 reg = <4>;
 491                         };
 492                 };
 493         };
 494 };
 495
 496 &gmac0 {
 497         status = "okay";
 498         phy-mode = "rgmii";
 499         qcom,id = <0>;
 500
 501         nvmem-cells = <&macaddr_ART_0>;
 502         nvmem-cell-names = "mac-address";
 503
 504         pinctrl-0 = <&rgmii2_pins>;
 505         pinctrl-names = "default";
 506
 507         fixed-link {
 508                 speed = <1000>;
 509                 full-duplex;
 510         };
 511 };
 512
 513 &gmac1 {
 514         status = "okay";
 515         phy-mode = "sgmii";
 516         qcom,id = <1>;
 517
 518         nvmem-cells = <&macaddr_ART_6>;
 519         nvmem-cell-names = "mac-address";
 520
 521         fixed-link {
 522                 speed = <1000>;
 523                 full-duplex;
 524         };
 525 };
 526
 527 &adm_dma {
 528         status = "okay";
 529 };
 530
 531 &hs_phy_0 {
 532         status = "okay";
 533 };
 534
 535 &ss_phy_0 {
 536         status = "okay";
 537 };
 538
 539 &usb3_0 {
 540         status = "okay";
 541 };
 542
 543 &hs_phy_1 {
 544         status = "okay";
 545 };
 546
 547 &ss_phy_1 {
 548         status = "okay";
 549 };
 550
 551 &usb3_1 {
 552         status = "okay";
 553 };
 554
 555 &pcie0 {
 556         status = "okay";
 557         reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
 558         pinctrl-0 = <&pcie0_pins>;
 559         pinctrl-names = "default";
 560
 561         bridge@0,0 {
 562                 reg = <0x00000000 0 0 0 0>;
 563                 #address-cells = <3>;
 564                 #size-cells = <2>;
 565                 ranges;
 566
 567                 wifi0: wifi@1,0 {
 568                         compatible = "pci168c,0046";
 569                         reg = <0x00010000 0 0 0 0>;
 570
 571                         nvmem-cells = <&precal_ART_1000>;
 572                         nvmem-cell-names = "pre-calibration";
 573                 };
 574         };
 575 };
 576
 577 &pcie1 {
 578         status = "okay";
 579         reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
 580         pinctrl-0 = <&pcie1_pins>;
 581         pinctrl-names = "default";
 582         max-link-speed = <1>;
 583
 584         bridge@0,0 {
 585                 reg = <0x00000000 0 0 0 0>;
 586                 #address-cells = <3>;
 587                 #size-cells = <2>;
 588                 ranges;
 589
 590                 wifi1: wifi@1,0 {
 591                         compatible = "pci168c,0046";
 592                         reg = <0x00010000 0 0 0 0>;
 593
 594                         nvmem-cells = <&precal_ART_5000>;
 595                         nvmem-cell-names = "pre-calibration";
 596                 };
 597         };
 598 };