ipq806x: convert each device to DSA implementation
[openwrt/openwrt.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065-nighthawk.dtsi
1 #include "qcom-ipq8065-smb208.dtsi"
2
3 #include <dt-bindings/input/input.h>
4
5 / {
6 memory@0 {
7 reg = <0x42000000 0x1e000000>;
8 device_type = "memory";
9 };
10
11 reserved-memory {
12 rsvd@5fe00000 {
13 reg = <0x5fe00000 0x200000>;
14 reusable;
15 };
16
17 ramoops@42100000 {
18 compatible = "ramoops";
19 reg = <0x42100000 0x40000>;
20 record-size = <0x4000>;
21 console-size = <0x4000>;
22 ftrace-size = <0x4000>;
23 pmsg-size = <0x4000>;
24 };
25 };
26
27 aliases {
28 label-mac-device = &gmac2;
29
30 led-boot = &power_white;
31 led-failsafe = &power_amber;
32 led-running = &power_white;
33 led-upgrade = &power_amber;
34
35 mdio-gpio0 = &mdio0;
36 };
37
38 keys {
39 compatible = "gpio-keys";
40 pinctrl-0 = <&button_pins>;
41 pinctrl-names = "default";
42
43 wifi {
44 label = "wifi";
45 gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
46 linux,code = <KEY_RFKILL>;
47 debounce-interval = <60>;
48 wakeup-source;
49 };
50
51 reset {
52 label = "reset";
53 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
54 linux,code = <KEY_RESTART>;
55 debounce-interval = <60>;
56 wakeup-source;
57 };
58
59 wps {
60 label = "wps";
61 gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
62 linux,code = <KEY_WPS_BUTTON>;
63 debounce-interval = <60>;
64 wakeup-source;
65 };
66 };
67
68 leds: leds {
69 compatible = "gpio-leds";
70 pinctrl-0 = <&led_pins>;
71 pinctrl-names = "default";
72
73 power_white: power_white {
74 label = "white:power";
75 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
76 default-state = "keep";
77 };
78
79 power_amber: power_amber {
80 label = "amber:power";
81 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
82 };
83
84 wan_white {
85 label = "white:wan";
86 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
87 };
88
89 wan_amber {
90 label = "amber:wan";
91 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
92 };
93
94 wifi {
95 label = "white:wifi";
96 gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
97 };
98
99 wps {
100 label = "white:wps";
101 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
102 };
103 };
104 };
105
106 &qcom_pinmux {
107 button_pins: button_pins {
108 mux {
109 pins = "gpio6", "gpio54", "gpio65";
110 function = "gpio";
111 drive-strength = <2>;
112 bias-pull-up;
113 };
114 };
115
116 led_pins: led_pins {
117 mux {
118 pins = "gpio7", "gpio8", "gpio9",
119 "gpio22", "gpio23", "gpio24",
120 "gpio26", "gpio53", "gpio64";
121 function = "gpio";
122 drive-strength = <2>;
123 bias-pull-down;
124 };
125 };
126
127 mdio0_pins: mdio0-pins {
128 clk {
129 pins = "gpio1";
130 input-disable;
131 };
132 };
133
134 rgmii2_pins: rgmii2-pins {
135 tx {
136 pins = "gpio27", "gpio28", "gpio29",
137 "gpio30", "gpio31", "gpio32";
138 input-disable;
139 };
140 };
141
142 spi_pins: spi_pins {
143 mux {
144 pins = "gpio18", "gpio19", "gpio21";
145 function = "gsbi5";
146 bias-pull-down;
147 };
148
149 data {
150 pins = "gpio18", "gpio19";
151 drive-strength = <10>;
152 };
153
154 cs {
155 pins = "gpio20";
156 drive-strength = <10>;
157 bias-pull-up;
158 };
159
160 clk {
161 pins = "gpio21";
162 drive-strength = <12>;
163 };
164 };
165
166 spi6_pins: spi6_pins {
167 mux {
168 pins = "gpio55", "gpio56", "gpio58";
169 function = "gsbi6";
170 bias-pull-down;
171 };
172
173 mosi {
174 pins = "gpio55";
175 drive-strength = <12>;
176 };
177
178 miso {
179 pins = "gpio56";
180 drive-strength = <14>;
181 };
182
183 cs {
184 pins = "gpio57";
185 drive-strength = <12>;
186 bias-pull-up;
187 };
188
189 clk {
190 pins = "gpio58";
191 drive-strength = <12>;
192 };
193
194 reset {
195 pins = "gpio33";
196 drive-strength = <10>;
197 bias-pull-down;
198 output-high;
199 };
200 };
201
202 usb0_pwr_en_pins: usb0_pwr_en_pins {
203 mux {
204 pins = "gpio15";
205 function = "gpio";
206 drive-strength = <12>;
207 bias-pull-down;
208 output-high;
209 };
210 };
211
212 usb1_pwr_en_pins: usb1_pwr_en_pins {
213 mux {
214 pins = "gpio16", "gpio68";
215 function = "gpio";
216 drive-strength = <12>;
217 bias-pull-down;
218 output-high;
219 };
220 };
221 };
222
223 &nand {
224 status = "okay";
225
226 nand@0 {
227 reg = <0>;
228 compatible = "qcom,nandcs";
229
230 nand-ecc-strength = <4>;
231 nand-bus-width = <8>;
232 nand-ecc-step-size = <512>;
233
234 nand-is-boot-medium;
235 qcom,boot-partitions = <0x0 0x1180000>;
236
237 partitions: partitions {
238 compatible = "fixed-partitions";
239 #address-cells = <1>;
240 #size-cells = <1>;
241
242 partition@0 {
243 label = "qcadata";
244 reg = <0x0000000 0x0c80000>;
245 read-only;
246 };
247
248 partition@c80000 {
249 label = "APPSBL";
250 reg = <0x0c80000 0x0500000>;
251 read-only;
252 };
253
254 partition@1180000 {
255 label = "APPSBLENV";
256 reg = <0x1180000 0x0080000>;
257 read-only;
258 };
259
260 art: partition@1200000 {
261 label = "art";
262 reg = <0x1200000 0x0140000>;
263 read-only;
264 compatible = "nvmem-cells";
265 #address-cells = <1>;
266 #size-cells = <1>;
267
268 macaddr_art_0: macaddr@0 {
269 reg = <0x0 0x6>;
270 };
271
272 macaddr_art_6: macaddr@6 {
273 reg = <0x6 0x6>;
274 };
275
276 precal_art_1000: precal@1000 {
277 reg = <0x1000 0x2f20>;
278 };
279
280 precal_art_5000: precal@5000 {
281 reg = <0x5000 0x2f20>;
282 };
283 };
284
285 partition@1340000 {
286 label = "artbak";
287 reg = <0x1340000 0x0140000>;
288 read-only;
289 };
290
291 partition@1480000 {
292 label = "kernel";
293 reg = <0x1480000 0x0400000>;
294 };
295 };
296 };
297 };
298
299 &mdio0 {
300 status = "okay";
301
302 pinctrl-0 = <&mdio0_pins>;
303 pinctrl-names = "default";
304
305 switch@10 {
306 compatible = "qca,qca8337";
307 #address-cells = <1>;
308 #size-cells = <0>;
309 reg = <0x10>;
310
311 ports {
312 #address-cells = <1>;
313 #size-cells = <0>;
314
315 port@0 {
316 reg = <0>;
317 label = "cpu";
318 ethernet = <&gmac1>;
319 phy-mode = "rgmii";
320 tx-internal-delay-ps = <1000>;
321 rx-internal-delay-ps = <1000>;
322
323 fixed-link {
324 speed = <1000>;
325 full-duplex;
326 };
327 };
328
329 port@1 {
330 reg = <1>;
331 label = "lan4";
332 phy-mode = "internal";
333 phy-handle = <&phy_port1>;
334 };
335
336 port@2 {
337 reg = <2>;
338 label = "lan3";
339 phy-mode = "internal";
340 phy-handle = <&phy_port2>;
341 };
342
343 port@3 {
344 reg = <3>;
345 label = "lan2";
346 phy-mode = "internal";
347 phy-handle = <&phy_port3>;
348 };
349
350 port@4 {
351 reg = <4>;
352 label = "lan1";
353 phy-mode = "internal";
354 phy-handle = <&phy_port4>;
355 };
356
357 port@5 {
358 reg = <5>;
359 label = "wan";
360 phy-mode = "internal";
361 phy-handle = <&phy_port5>;
362 };
363
364 /*
365 port@6 {
366 reg = <0>;
367 label = "cpu";
368 ethernet = <&gmac2>;
369 phy-mode = "rgmii";
370
371 fixed-link {
372 speed = <1000>;
373 full-duplex;
374 pause;
375 asym-pause;
376 };
377 };
378 */
379 };
380
381 mdio {
382 #address-cells = <1>;
383 #size-cells = <0>;
384
385 phy_port1: phy@0 {
386 reg = <0>;
387 };
388
389 phy_port2: phy@1 {
390 reg = <1>;
391 };
392
393 phy_port3: phy@2 {
394 reg = <2>;
395 };
396
397 phy_port4: phy@3 {
398 reg = <3>;
399 };
400
401 phy_port5: phy@4 {
402 reg = <4>;
403 };
404 };
405 };
406 };
407
408 &gmac1 {
409 status = "okay";
410
411 phy-mode = "rgmii";
412 qcom,id = <1>;
413 qcom,phy_mdio_addr = <4>;
414 qcom,poll_required = <0>;
415 qcom,rgmii_delay = <1>;
416 qcom,phy_mii_type = <0>;
417 qcom,emulation = <0>;
418 qcom,irq = <255>;
419 mdiobus = <&mdio0>;
420
421 pinctrl-0 = <&rgmii2_pins>;
422 pinctrl-names = "default";
423
424 nvmem-cells = <&macaddr_art_6>;
425 nvmem-cell-names = "mac-address";
426
427 fixed-link {
428 speed = <1000>;
429 full-duplex;
430 };
431 };
432
433 &gmac2 {
434 status = "okay";
435
436 phy-mode = "sgmii";
437 qcom,id = <2>;
438 qcom,phy_mdio_addr = <0>; /* none */
439 qcom,poll_required = <0>; /* no polling */
440 qcom,rgmii_delay = <0>;
441 qcom,phy_mii_type = <1>;
442 qcom,emulation = <0>;
443 qcom,irq = <258>;
444 mdiobus = <&mdio0>;
445
446 nvmem-cells = <&macaddr_art_0>;
447 nvmem-cell-names = "mac-address";
448
449 fixed-link {
450 speed = <1000>;
451 full-duplex;
452 };
453 };
454
455 &adm_dma {
456 status = "okay";
457 };
458
459 &sata_phy {
460 status = "okay";
461 };
462
463 &sata {
464 status = "okay";
465 };
466
467 &hs_phy_0 {
468 status = "okay";
469 };
470
471 &ss_phy_0 {
472 status = "okay";
473 };
474
475 &usb3_0 {
476 status = "okay";
477
478 pinctrl-0 = <&usb0_pwr_en_pins>;
479 pinctrl-names = "default";
480 };
481
482 &hs_phy_1 {
483 status = "okay";
484 };
485
486 &ss_phy_1 {
487 status = "okay";
488 };
489
490 &usb3_1 {
491 status = "okay";
492
493 pinctrl-0 = <&usb1_pwr_en_pins>;
494 pinctrl-names = "default";
495 };
496
497 &pcie0 {
498 status = "okay";
499
500 bridge@0,0 {
501 reg = <0x00000000 0 0 0 0>;
502 #address-cells = <3>;
503 #size-cells = <2>;
504 ranges;
505
506 wifi0: wifi@1,0 {
507 compatible = "pci168c,0046";
508 reg = <0x00010000 0 0 0 0>;
509 };
510 };
511 };
512
513 &pcie1 {
514 status = "okay";
515
516 max-link-speed = <1>;
517
518 bridge@0,0 {
519 reg = <0x00000000 0 0 0 0>;
520 #address-cells = <3>;
521 #size-cells = <2>;
522 ranges;
523
524 wifi1: wifi@1,0 {
525 compatible = "pci168c,0046";
526 reg = <0x00010000 0 0 0 0>;
527 };
528 };
529 };