ipq806x: rename kernel files to generic name
[openwrt/openwrt.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065-nighthawk.dtsi
1 #include "qcom-ipq8065-smb208.dtsi"
2
3 #include <dt-bindings/input/input.h>
4
5 / {
6 memory@0 {
7 reg = <0x42000000 0x1e000000>;
8 device_type = "memory";
9 };
10
11 reserved-memory {
12 rsvd@5fe00000 {
13 reg = <0x5fe00000 0x200000>;
14 reusable;
15 };
16
17 ramoops@42100000 {
18 compatible = "ramoops";
19 reg = <0x42100000 0x40000>;
20 record-size = <0x4000>;
21 console-size = <0x4000>;
22 ftrace-size = <0x4000>;
23 pmsg-size = <0x4000>;
24 };
25 };
26
27 aliases {
28 label-mac-device = &gmac2;
29
30 led-boot = &power_white;
31 led-failsafe = &power_amber;
32 led-running = &power_white;
33 led-upgrade = &power_amber;
34
35 mdio-gpio0 = &mdio0;
36 };
37
38 keys {
39 compatible = "gpio-keys";
40 pinctrl-0 = <&button_pins>;
41 pinctrl-names = "default";
42
43 wifi {
44 label = "wifi";
45 gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
46 linux,code = <KEY_RFKILL>;
47 debounce-interval = <60>;
48 wakeup-source;
49 };
50
51 reset {
52 label = "reset";
53 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
54 linux,code = <KEY_RESTART>;
55 debounce-interval = <60>;
56 wakeup-source;
57 };
58
59 wps {
60 label = "wps";
61 gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
62 linux,code = <KEY_WPS_BUTTON>;
63 debounce-interval = <60>;
64 wakeup-source;
65 };
66 };
67
68 leds: leds {
69 compatible = "gpio-leds";
70 pinctrl-0 = <&led_pins>;
71 pinctrl-names = "default";
72
73 power_white: power_white {
74 label = "white:power";
75 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
76 default-state = "keep";
77 };
78
79 power_amber: power_amber {
80 label = "amber:power";
81 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
82 };
83
84 wan_white {
85 label = "white:wan";
86 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
87 };
88
89 wan_amber {
90 label = "amber:wan";
91 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
92 };
93
94 wifi {
95 label = "white:wifi";
96 gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
97 };
98
99 wps {
100 label = "white:wps";
101 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
102 };
103 };
104 };
105
106 &qcom_pinmux {
107 button_pins: button_pins {
108 mux {
109 pins = "gpio6", "gpio54", "gpio65";
110 function = "gpio";
111 drive-strength = <2>;
112 bias-pull-up;
113 };
114 };
115
116 led_pins: led_pins {
117 mux {
118 pins = "gpio7", "gpio8", "gpio9",
119 "gpio22", "gpio23", "gpio24",
120 "gpio26", "gpio53", "gpio64";
121 function = "gpio";
122 drive-strength = <2>;
123 bias-pull-down;
124 };
125 };
126
127 mdio0_pins: mdio0-pins {
128 clk {
129 pins = "gpio1";
130 input-disable;
131 };
132 };
133
134 rgmii2_pins: rgmii2-pins {
135 tx {
136 pins = "gpio27", "gpio28", "gpio29",
137 "gpio30", "gpio31", "gpio32";
138 input-disable;
139 };
140 };
141
142 spi_pins: spi_pins {
143 mux {
144 pins = "gpio18", "gpio19", "gpio21";
145 function = "gsbi5";
146 bias-pull-down;
147 };
148
149 data {
150 pins = "gpio18", "gpio19";
151 drive-strength = <10>;
152 };
153
154 cs {
155 pins = "gpio20";
156 drive-strength = <10>;
157 bias-pull-up;
158 };
159
160 clk {
161 pins = "gpio21";
162 drive-strength = <12>;
163 };
164 };
165
166 spi6_pins: spi6_pins {
167 mux {
168 pins = "gpio55", "gpio56", "gpio58";
169 function = "gsbi6";
170 bias-pull-down;
171 };
172
173 mosi {
174 pins = "gpio55";
175 drive-strength = <12>;
176 };
177
178 miso {
179 pins = "gpio56";
180 drive-strength = <14>;
181 };
182
183 cs {
184 pins = "gpio57";
185 drive-strength = <12>;
186 bias-pull-up;
187 };
188
189 clk {
190 pins = "gpio58";
191 drive-strength = <12>;
192 };
193
194 reset {
195 pins = "gpio33";
196 drive-strength = <10>;
197 bias-pull-down;
198 output-high;
199 };
200 };
201
202 usb0_pwr_en_pins: usb0_pwr_en_pins {
203 mux {
204 pins = "gpio15";
205 function = "gpio";
206 drive-strength = <12>;
207 bias-pull-down;
208 output-high;
209 };
210 };
211
212 usb1_pwr_en_pins: usb1_pwr_en_pins {
213 mux {
214 pins = "gpio16", "gpio68";
215 function = "gpio";
216 drive-strength = <12>;
217 bias-pull-down;
218 output-high;
219 };
220 };
221 };
222
223 &nand {
224 status = "okay";
225
226 nand@0 {
227 reg = <0>;
228 compatible = "qcom,nandcs";
229
230 nand-ecc-strength = <4>;
231 nand-bus-width = <8>;
232 nand-ecc-step-size = <512>;
233
234 nand-is-boot-medium;
235 qcom,boot-partitions = <0x0 0x1180000>;
236
237 partitions: partitions {
238 compatible = "fixed-partitions";
239 #address-cells = <1>;
240 #size-cells = <1>;
241
242 partition@0 {
243 label = "qcadata";
244 reg = <0x0000000 0x0c80000>;
245 read-only;
246 };
247
248 partition@c80000 {
249 label = "APPSBL";
250 reg = <0x0c80000 0x0500000>;
251 read-only;
252 };
253
254 partition@1180000 {
255 label = "APPSBLENV";
256 reg = <0x1180000 0x0080000>;
257 read-only;
258 };
259
260 art: partition@1200000 {
261 label = "art";
262 reg = <0x1200000 0x0140000>;
263 read-only;
264 compatible = "nvmem-cells";
265 #address-cells = <1>;
266 #size-cells = <1>;
267
268 macaddr_art_0: macaddr@0 {
269 reg = <0x0 0x6>;
270 };
271
272 macaddr_art_6: macaddr@6 {
273 reg = <0x6 0x6>;
274 };
275
276 precal_art_1000: precal@1000 {
277 reg = <0x1000 0x2f20>;
278 };
279
280 precal_art_5000: precal@5000 {
281 reg = <0x5000 0x2f20>;
282 };
283 };
284
285 partition@1340000 {
286 label = "artbak";
287 reg = <0x1340000 0x0140000>;
288 read-only;
289 };
290
291 partition@1480000 {
292 label = "kernel";
293 reg = <0x1480000 0x0400000>;
294 };
295 };
296 };
297 };
298
299 &mdio0 {
300 status = "okay";
301
302 pinctrl-0 = <&mdio0_pins>;
303 pinctrl-names = "default";
304
305 phy0: ethernet-phy@0 {
306 reg = <0>;
307 qca,ar8327-initvals = <
308 0x00004 0x7600000 /* PAD0_MODE */
309 0x00008 0x1000000 /* PAD5_MODE */
310 0x0000c 0x80 /* PAD6_MODE */
311 0x000e4 0xaa545 /* MAC_POWER_SEL */
312 0x000e0 0xc74164de /* SGMII_CTRL */
313 0x0007c 0x4e /* PORT0_STATUS */
314 0x00094 0x4e /* PORT6_STATUS */
315 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */
316 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */
317 0x00978 0x19008643 /* QM_PORT1_CTRL0 */
318 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */
319 0x00980 0x19008643 /* QM_PORT2_CTRL0 */
320 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */
321 0x00988 0x19008643 /* QM_PORT3_CTRL0 */
322 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */
323 0x00990 0x19008643 /* QM_PORT4_CTRL0 */
324 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */
325 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */
326 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */
327 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */
328 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */
329 >;
330 qca,ar8327-vlans = <
331 0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */
332 0x2 0x21 /* VLAN2 Ports 0/5 */
333 >;
334 };
335
336 phy4: ethernet-phy@4 {
337 reg = <4>;
338 qca,ar8327-initvals = <
339 0x000e4 0x6a545 /* MAC_POWER_SEL */
340 0x0000c 0x80 /* PAD6_MODE */
341 >;
342 };
343 };
344
345 &gmac1 {
346 status = "okay";
347
348 phy-mode = "rgmii";
349 qcom,id = <1>;
350 qcom,phy_mdio_addr = <4>;
351 qcom,poll_required = <0>;
352 qcom,rgmii_delay = <1>;
353 qcom,phy_mii_type = <0>;
354 qcom,emulation = <0>;
355 qcom,irq = <255>;
356 mdiobus = <&mdio0>;
357
358 pinctrl-0 = <&rgmii2_pins>;
359 pinctrl-names = "default";
360
361 nvmem-cells = <&macaddr_art_6>;
362 nvmem-cell-names = "mac-address";
363
364 fixed-link {
365 speed = <1000>;
366 full-duplex;
367 };
368 };
369
370 &gmac2 {
371 status = "okay";
372
373 phy-mode = "sgmii";
374 qcom,id = <2>;
375 qcom,phy_mdio_addr = <0>; /* none */
376 qcom,poll_required = <0>; /* no polling */
377 qcom,rgmii_delay = <0>;
378 qcom,phy_mii_type = <1>;
379 qcom,emulation = <0>;
380 qcom,irq = <258>;
381 mdiobus = <&mdio0>;
382
383 nvmem-cells = <&macaddr_art_0>;
384 nvmem-cell-names = "mac-address";
385
386 fixed-link {
387 speed = <1000>;
388 full-duplex;
389 };
390 };
391
392 &adm_dma {
393 status = "okay";
394 };
395
396 &sata_phy {
397 status = "okay";
398 };
399
400 &sata {
401 status = "okay";
402 };
403
404 &hs_phy_0 {
405 status = "okay";
406 };
407
408 &ss_phy_0 {
409 status = "okay";
410 };
411
412 &usb3_0 {
413 status = "okay";
414
415 pinctrl-0 = <&usb0_pwr_en_pins>;
416 pinctrl-names = "default";
417 };
418
419 &hs_phy_1 {
420 status = "okay";
421 };
422
423 &ss_phy_1 {
424 status = "okay";
425 };
426
427 &usb3_1 {
428 status = "okay";
429
430 pinctrl-0 = <&usb1_pwr_en_pins>;
431 pinctrl-names = "default";
432 };
433
434 &pcie0 {
435 status = "okay";
436
437 bridge@0,0 {
438 reg = <0x00000000 0 0 0 0>;
439 #address-cells = <3>;
440 #size-cells = <2>;
441 ranges;
442
443 wifi0: wifi@1,0 {
444 compatible = "pci168c,0046";
445 reg = <0x00010000 0 0 0 0>;
446 };
447 };
448 };
449
450 &pcie1 {
451 status = "okay";
452
453 max-link-speed = <1>;
454
455 bridge@0,0 {
456 reg = <0x00000000 0 0 0 0>;
457 #address-cells = <3>;
458 #size-cells = <2>;
459 ranges;
460
461 wifi1: wifi@1,0 {
462 compatible = "pci168c,0046";
463 reg = <0x00010000 0 0 0 0>;
464 };
465 };
466 };