d20b55c2c2967689e4f694d7a4c42cfe6756855d
[openwrt/openwrt.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8064-onhub.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2014 The ChromiumOS Authors
4 */
5
6 #include "qcom-ipq8064-smb208.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/soc/qcom,tcsr.h>
10
11 / {
12 aliases {
13 ethernet0 = &gmac0;
14 ethernet1 = &gmac2;
15 mdio-gpio0 = &mdio;
16 serial0 = &gsbi4_serial;
17 };
18
19 chosen {
20 stdout-path = "serial0:115200n8";
21 };
22
23 reserved-memory {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 rsvd@41200000 {
29 reg = <0x41200000 0x300000>;
30 no-map;
31 };
32 };
33
34 keys {
35 compatible = "gpio-keys";
36 pinctrl-0 = <&button_pins>;
37 pinctrl-names = "default";
38
39 reset {
40 label = "reset";
41 gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_RESTART>;
43 debounce-interval = <60>;
44 wakeup-source;
45 };
46
47 dev {
48 label = "dev";
49 gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
50 linux,code = <KEY_CONFIG>;
51 debounce-interval = <60>;
52 wakeup-source;
53 };
54 };
55
56 mdio: mdio {
57 compatible = "virtual,mdio-gpio";
58 #address-cells = <1>;
59 #size-cells = <0>;
60 gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
61 <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
62 pinctrl-0 = <&mdio_pins>;
63 pinctrl-names = "default";
64
65 switch@10 {
66 compatible = "qca,qca8337";
67 #address-cells = <1>;
68 #size-cells = <0>;
69 reg = <0x10>;
70
71 ports {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
75 port@0 {
76 reg = <0>;
77 label = "cpu";
78 ethernet = <&gmac0>;
79 phy-mode = "rgmii";
80 tx-internal-delay-ps = <1000>;
81 rx-internal-delay-ps = <1000>;
82
83 fixed-link {
84 speed = <1000>;
85 full-duplex;
86 };
87 };
88
89 port@1 {
90 reg = <1>;
91 label = "lan1";
92 phy-mode = "internal";
93 phy-handle = <&phy_port1>;
94 };
95
96 port@2 {
97 reg = <2>;
98 label = "wan";
99 phy-mode = "internal";
100 phy-handle = <&phy_port2>;
101 };
102
103 /*
104 port@6 {
105 reg = <0>;
106 label = "cpu";
107 ethernet = <&gmac2>;
108 phy-mode = "rgmii";
109
110 fixed-link {
111 speed = <1000>;
112 full-duplex;
113 pause;
114 asym-pause;
115 };
116 };
117 */
118 };
119
120 mdio {
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 phy_port1: phy@0 {
125 reg = <0>;
126 };
127
128 phy_port2: phy@1 {
129 reg = <1>;
130 };
131 };
132 };
133 };
134
135 soc {
136 rng@1a500000 {
137 status = "disabled";
138 };
139
140 sound {
141 compatible = "google,storm-audio";
142 qcom,model = "ipq806x-storm";
143 cpu = <&lpass>;
144 codec = <&max98357a>;
145 };
146
147 lpass: lpass@28100000 {
148 status = "okay";
149 pinctrl-names = "default", "idle";
150 pinctrl-0 = <&mi2s_default>;
151 pinctrl-1 = <&mi2s_idle>;
152 };
153
154 max98357a: max98357a {
155 compatible = "maxim,max98357a";
156 #sound-dai-cells = <1>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&sdmode_pins>;
159 sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
160 };
161 };
162 };
163
164 &qcom_pinmux {
165 rgmii0_pins: rgmii0_pins {
166 mux {
167 pins = "gpio2", "gpio66";
168 drive-strength = <8>;
169 bias-disable;
170 };
171 };
172 mi2s_pins {
173 mi2s_default: mi2s_default {
174 dout {
175 pins = "gpio32";
176 function = "mi2s";
177 drive-strength = <16>;
178 bias-disable;
179 };
180 sync {
181 pins = "gpio27";
182 function = "mi2s";
183 drive-strength = <16>;
184 bias-disable;
185 };
186 clk {
187 pins = "gpio28";
188 function = "mi2s";
189 drive-strength = <16>;
190 bias-disable;
191 };
192 };
193 mi2s_idle: mi2s_idle {
194 dout {
195 pins = "gpio32";
196 function = "mi2s";
197 drive-strength = <2>;
198 bias-pull-down;
199 };
200 sync {
201 pins = "gpio27";
202 function = "mi2s";
203 drive-strength = <2>;
204 bias-pull-down;
205 };
206 clk {
207 pins = "gpio28";
208 function = "mi2s";
209 drive-strength = <2>;
210 bias-pull-down;
211 };
212 };
213 };
214
215 mdio_pins: mdio_pins {
216 mux {
217 pins = "gpio0", "gpio1";
218 function = "gpio";
219 drive-strength = <8>;
220 bias-disable;
221 };
222 rst {
223 pins = "gpio26";
224 output-low;
225 };
226 };
227
228 sdmode_pins: sdmode_pinmux {
229 pins = "gpio25";
230 function = "gpio";
231 drive-strength = <16>;
232 bias-disable;
233 };
234
235 sdcc1_pins: sdcc1_pinmux {
236 mux {
237 pins = "gpio38", "gpio39", "gpio40",
238 "gpio41", "gpio42", "gpio43",
239 "gpio44", "gpio45", "gpio46",
240 "gpio47";
241 function = "sdc1";
242 };
243 cmd {
244 pins = "gpio45";
245 drive-strength = <10>;
246 bias-pull-up;
247 };
248 data {
249 pins = "gpio38", "gpio39", "gpio40",
250 "gpio41", "gpio43", "gpio44",
251 "gpio46", "gpio47";
252 drive-strength = <10>;
253 bias-pull-up;
254 };
255 clk {
256 pins = "gpio42";
257 drive-strength = <16>;
258 bias-pull-down;
259 };
260 };
261
262 i2c1_pins: i2c1_pinmux {
263 pins = "gpio53", "gpio54";
264 function = "gsbi1";
265 bias-disable;
266 };
267
268 rpm_i2c_pinmux: rpm_i2c_pinmux {
269 mux {
270 pins = "gpio12", "gpio13";
271 function = "gsbi4";
272 drive-strength = <12>;
273 bias-disable;
274 };
275 };
276
277 spi_pins: spi_pins {
278 mux {
279 pins = "gpio18", "gpio19", "gpio21";
280 function = "gsbi5";
281 bias-pull-down;
282 /delete-property/ bias-none;
283 /delete-property/ drive-strength;
284 };
285 data {
286 pins = "gpio18", "gpio19";
287 drive-strength = <10>;
288 };
289 cs {
290 pins = "gpio20";
291 drive-strength = <10>;
292 bias-pull-up;
293 };
294 clk {
295 pins = "gpio21";
296 drive-strength = <12>;
297 };
298 };
299
300 fw_pinmux {
301 wp {
302 pins = "gpio17";
303 output-low;
304 };
305 };
306
307 button_pins: button_pins {
308 recovery {
309 pins = "gpio16";
310 function = "gpio";
311 bias-none;
312 };
313 developer {
314 pins = "gpio15";
315 function = "gpio";
316 bias-none;
317 };
318 };
319
320 spi6_pins: spi6_pins {
321 mux {
322 pins = "gpio55", "gpio56", "gpio58";
323 function = "gsbi6";
324 bias-pull-down;
325 };
326 data {
327 pins = "gpio55", "gpio56";
328 drive-strength = <10>;
329 };
330 cs {
331 pins = "gpio57";
332 drive-strength = <10>;
333 bias-pull-up;
334 output-high;
335 };
336 clk {
337 pins = "gpio58";
338 drive-strength = <12>;
339 };
340 };
341 };
342
343 &adm_dma {
344 status = "okay";
345 };
346
347 &gmac0 {
348 status = "okay";
349 phy-mode = "rgmii";
350 qcom,id = <0>;
351 phy-handle = <&phy1>;
352
353 pinctrl-0 = <&rgmii0_pins>;
354 pinctrl-names = "default";
355
356 fixed-link {
357 speed = <1000>;
358 full-duplex;
359 };
360 };
361
362 &gmac2 {
363 status = "okay";
364 phy-mode = "sgmii";
365 qcom,id = <2>;
366 phy-handle = <&phy0>;
367
368 fixed-link {
369 speed = <1000>;
370 full-duplex;
371 };
372 };
373
374 &gsbi1 {
375 status = "okay";
376 qcom,mode = <GSBI_PROT_I2C_UART>;
377 };
378
379 &gsbi1_i2c {
380 status = "okay";
381
382 clock-frequency = <100000>;
383
384 pinctrl-0 = <&i2c1_pins>;
385 pinctrl-names = "default";
386
387 tpm@20 {
388 compatible = "infineon,slb9645tt";
389 reg = <0x20>;
390 powered-while-suspended;
391 };
392 };
393
394 &gsbi4 {
395 status = "okay";
396 qcom,mode = <GSBI_PROT_I2C_UART>;
397 };
398
399 &gsbi4_serial {
400 status = "okay";
401 };
402
403 &gsbi5 {
404 status = "okay";
405 qcom,mode = <GSBI_PROT_SPI>;
406
407 spi4: spi@1a280000 {
408 status = "okay";
409 spi-max-frequency = <50000000>;
410 pinctrl-0 = <&spi_pins>;
411 pinctrl-names = "default";
412
413 cs-gpios = <&qcom_pinmux 20 0>;
414
415 flash: flash@0 {
416 compatible = "jedec,spi-nor";
417 spi-max-frequency = <50000000>;
418 reg = <0>;
419 };
420 };
421 };
422
423 &gsbi6 {
424 status = "okay";
425 qcom,mode = <GSBI_PROT_SPI>;
426 };
427
428 &gsbi6_spi {
429 status = "okay";
430 spi-max-frequency = <25000000>;
431
432 pinctrl-0 = <&spi6_pins>;
433 pinctrl-names = "default";
434
435 cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
436
437 dmas = <&adm_dma 8 0xb>,
438 <&adm_dma 7 0x14>;
439 dma-names = "rx", "tx";
440
441 /*
442 * This "spidev" was included in the manufacturer device tree. I suspect
443 * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
444 * no driver or binding for this at the moment.
445 */
446 spidev@0 {
447 compatible = "spidev";
448 reg = <0>;
449 spi-max-frequency = <25000000>;
450 };
451 };
452
453 &pcie0 {
454 status = "okay";
455
456 pcie@0 {
457 reg = <0 0 0 0 0>;
458 #interrupt-cells = <1>;
459 #size-cells = <2>;
460 #address-cells = <3>;
461 device_type = "pci";
462
463 ath10k@0,0 {
464 reg = <0 0 0 0 0>;
465 device_type = "pci";
466 qcom,ath10k-sa-gpio = <2 3 4 0>;
467 qcom,ath10k-sa-gpio-func = <5 5 5 0>;
468 };
469 };
470 };
471
472 &pcie1 {
473 status = "okay";
474
475 pcie@0 {
476 reg = <0 0 0 0 0>;
477 #interrupt-cells = <1>;
478 #size-cells = <2>;
479 #address-cells = <3>;
480 device_type = "pci";
481
482 ath10k@0,0 {
483 reg = <0 0 0 0 0>;
484 device_type = "pci";
485 qcom,ath10k-sa-gpio = <2 3 4 0>;
486 qcom,ath10k-sa-gpio-func = <5 5 5 0>;
487 };
488 };
489 };
490
491 &pcie2 {
492 status = "okay";
493
494 pcie@0 {
495 reg = <0 0 0 0 0>;
496 #interrupt-cells = <1>;
497 #size-cells = <2>;
498 #address-cells = <3>;
499 device_type = "pci";
500
501 ath10k@0,0 {
502 reg = <0 0 0 0 0>;
503 device_type = "pci";
504 };
505 };
506 };
507
508 &rpm {
509 pinctrl-0 = <&rpm_i2c_pinmux>;
510 pinctrl-names = "default";
511 };
512
513 &sdcc1 {
514 status = "okay";
515 pinctrl-0 = <&sdcc1_pins>;
516 pinctrl-names = "default";
517 /delete-property/ mmc-ddr-1_8v;
518 };
519
520 &tcsr {
521 compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
522 qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
523 };
524
525 &hs_phy_0 {
526 status = "okay";
527 };
528
529 &ss_phy_0 {
530 status = "okay";
531 };
532
533 &usb3_0 {
534 status = "okay";
535 };
536
537 &hs_phy_1 {
538 status = "okay";
539 };
540
541 &ss_phy_1 {
542 status = "okay";
543 };
544
545 &usb3_1 {
546 status = "okay";
547 };