target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #include "qcom-ipq8065-smb208.dtsi"
   4 #include <dt-bindings/input/input.h>
   5
   6 / {
   7         model = "Askey RT4230W REV6";
   8         compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
   9
  10         memory@0 {
  11                 reg = <0x42000000 0x3e000000>;
  12                 device_type = "memory";
  13         };
  14
  15         aliases {
  16                 led-boot = &ledctrl3;
  17                 led-failsafe = &ledctrl1;
  18                 led-running = &ledctrl2;
  19                 led-upgrade = &ledctrl3;
  20         };
  21
  22         chosen {
  23                 bootargs = "rootfstype=squashfs noinitrd";
  24         };
  25
  26         keys {
  27                 compatible = "gpio-keys";
  28                 pinctrl-0 = <&button_pins>;
  29                 pinctrl-names = "default";
  30
  31                 reset {
  32                         label = "reset";
  33                         gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_RESTART>;
  35                 };
  36
  37                 wps {
  38                         label = "wps";
  39                         gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  40                         linux,code = <KEY_WPS_BUTTON>;
  41                 };
  42         };
  43
  44         leds {
  45                 compatible = "gpio-leds";
  46                 pinctrl-0 = <&led_pins>;
  47                 pinctrl-names = "default";
  48
  49                 ledctrl1: ledctrl1 {
  50                         label = "ledctrl1";
  51                         gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  52                 };
  53
  54                 ledctrl2: ledctrl2 {
  55                         label = "ledctrl2";
  56                         gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  57                 };
  58
  59                 ledctrl3: ledctrl3 {
  60                         label = "ledctrl3";
  61                         gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  62                 };
  63         };
  64 };
  65
  66 &qcom_pinmux {
  67         button_pins: button_pins {
  68                 mux {
  69                         pins = "gpio54", "gpio68";
  70                         function = "gpio";
  71                         drive-strength = <2>;
  72                         bias-pull-up;
  73                 };
  74         };
  75
  76         led_pins: led_pins {
  77                 mux {
  78                         pins = "gpio22", "gpio23", "gpio24";
  79                         function = "gpio";
  80                         drive-strength = <2>;
  81                         bias-pull-down;
  82                 };
  83         };
  84
  85         rgmii2_pins: rgmii2-pins {
  86                 mux {
  87                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
  88                                 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
  89                         function = "rgmii2";
  90                         drive-strength = <8>;
  91                         bias-disable;
  92                 };
  93
  94                 tx {
  95                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  96                         input-disable;
  97                 };
  98         };
  99
 100         spi_pins: spi_pins {
 101                 cs {
 102                         pins = "gpio20";
 103                         drive-strength = <12>;
 104                 };
 105         };
 106 };
 107
 108 &gsbi5 {
 109         qcom,mode = <GSBI_PROT_SPI>;
 110         status = "okay";
 111
 112         spi@1a280000 {
 113                 status = "okay";
 114
 115                 pinctrl-0 = <&spi_pins>;
 116                 pinctrl-names = "default";
 117
 118                 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
 119
 120                 flash@0 {
 121                         compatible = "everspin,mr25h256";
 122                         #address-cells = <1>;
 123                         #size-cells = <1>;
 124                         spi-max-frequency = <40000000>;
 125                         reg = <0>;
 126                 };
 127         };
 128 };
 129
 130 &nand {
 131         status = "okay";
 132
 133         nand@0 {
 134                 reg = <0>;
 135                 compatible = "qcom,nandcs";
 136
 137                 nand-ecc-strength = <4>;
 138                 nand-bus-width = <8>;
 139                 nand-ecc-step-size = <512>;
 140
 141                 qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>;
 142
 143                 partitions {
 144                         compatible = "fixed-partitions";
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147
 148                         partition@0 {
 149                                 label = "0:SBL1";
 150                                 reg = <0x0000000 0x0040000>;
 151                                 read-only;
 152                         };
 153
 154                         partition@40000 {
 155                                 label = "0:MIBIB";
 156                                 reg = <0x0040000 0x0140000>;
 157                                 read-only;
 158                         };
 159
 160                         partition@180000 {
 161                                 label = "0:SBL2";
 162                                 reg = <0x0180000 0x0140000>;
 163                                 read-only;
 164                         };
 165
 166                         partition@2c0000 {
 167                                 label = "0:SBL3";
 168                                 reg = <0x02c0000 0x0280000>;
 169                                 read-only;
 170                         };
 171
 172                         partition@540000 {
 173                                 label = "0:DDRCONFIG";
 174                                 reg = <0x0540000 0x0120000>;
 175                                 read-only;
 176                         };
 177
 178                         partition@660000 {
 179                                 label = "0:SSD";
 180                                 reg = <0x0660000 0x0120000>;
 181                                 read-only;
 182                         };
 183
 184                         partition@780000 {
 185                                 label = "0:TZ";
 186                                 reg = <0x0780000 0x0280000>;
 187                                 read-only;
 188                         };
 189
 190                         partition@a00000 {
 191                                 label = "0:RPM";
 192                                 reg = <0x0a00000 0x0280000>;
 193                                 read-only;
 194                         };
 195
 196                         partition@c80000 {
 197                                 label = "0:APPSBL";
 198                                 reg = <0x0c80000 0x0500000>;
 199                                 read-only;
 200                         };
 201
 202                         partition@1180000 {
 203                                 label = "0:APPSBLENV";
 204                                 reg = <0x1180000 0x0080000>;
 205                         };
 206
 207                         partition@1200000 {
 208                                 label = "0:ART";
 209                                 reg = <0x1200000 0x0140000>;
 210                                 read-only;
 211                                 compatible = "nvmem-cells";
 212                                 #address-cells = <1>;
 213                                 #size-cells = <1>;
 214
 215                                 macaddr_ART_0: macaddr@0 {
 216                                         reg = <0x0 0x6>;
 217                                 };
 218
 219                                 macaddr_ART_6: macaddr@6 {
 220                                         reg = <0x6 0x6>;
 221                                 };
 222
 223                                 precal_ART_1000: precal@1000 {
 224                                         reg = <0x1000 0x2f20>;
 225                                 };
 226
 227                                 precal_ART_5000: precal@5000 {
 228                                         reg = <0x5000 0x2f20>;
 229                                 };
 230                         };
 231
 232                         partition@1340000 {
 233                                 label = "0:BOOTCONFIG";
 234                                 reg = <0x1340000 0x0060000>;
 235                                 read-only;
 236                         };
 237
 238                         partition@13a0000 {
 239                                 label = "0:SBL2_1";
 240                                 reg = <0x13a0000 0x0140000>;
 241                                 read-only;
 242                         };
 243
 244                         partition@14e0000 {
 245                                 label = "0:SBL3_1";
 246                                 reg = <0x14e0000 0x0280000>;
 247                                 read-only;
 248                         };
 249
 250                         partition@1760000 {
 251                                 label = "0:DDRCONFIG_1";
 252                                 reg = <0x1760000 0x0120000>;
 253                                 read-only;
 254                         };
 255
 256                         partition@1880000 {
 257                                 label = "0:SSD_1";
 258                                 reg = <0x1880000 0x0120000>;
 259                                 read-only;
 260                         };
 261
 262                         partition@19a0000 {
 263                                 label = "0:TZ_1";
 264                                 reg = <0x19a0000 0x0280000>;
 265                                 read-only;
 266                         };
 267
 268                         partition@1c20000 {
 269                                 label = "0:RPM_1";
 270                                 reg = <0x1c20000 0x0280000>;
 271                                 read-only;
 272                         };
 273
 274                         partition@1ea0000 {
 275                                 label = "0:BOOTCONFIG1";
 276                                 reg = <0x1ea0000 0x0060000>;
 277                                 read-only;
 278                         };
 279
 280                         partition@1f00000 {
 281                                 label = "0:APPSBL_1";
 282                                 reg = <0x1f00000 0x0500000>;
 283                                 read-only;
 284                         };
 285
 286                         partition@2400000 {
 287                                 label = "ubi";
 288                                 reg = <0x2400000 0x1a000000>;
 289                         };
 290                 };
 291         };
 292 };
 293
 294 &mdio0 {
 295         status = "okay";
 296
 297         pinctrl-0 = <&mdio0_pins>;
 298         pinctrl-names = "default";
 299
 300         phy0: ethernet-phy@0 {
 301                 reg = <0x0>;
 302                 qca,ar8327-initvals = <
 303                         0x00004 0x7600000   /* PAD0_MODE */
 304                         0x00008 0x1000000   /* PAD5_MODE */
 305                         0x0000c 0x80        /* PAD6_MODE */
 306                         0x000e4 0xaa545     /* MAC_POWER_SEL */
 307                         0x000e0 0xc74164de  /* SGMII_CTRL */
 308                         0x0007c 0x4e        /* PORT0_STATUS */
 309                         0x00094 0x4e        /* PORT6_STATUS */
 310                         0x00050 0xcf02cf02  /* LED_CTRL_0 */
 311                         0x00054 0xc832c832  /* LED_CTRL_1 */
 312                         >;
 313         };
 314 };
 315
 316 &gmac0 {
 317         status = "okay";
 318         phy-mode = "rgmii";
 319         qcom,id = <0>;
 320
 321         nvmem-cells = <&macaddr_ART_0>;
 322         nvmem-cell-names = "mac-address";
 323
 324         pinctrl-0 = <&rgmii2_pins>;
 325         pinctrl-names = "default";
 326
 327         fixed-link {
 328                 speed = <1000>;
 329                 full-duplex;
 330         };
 331 };
 332
 333 &gmac1 {
 334         status = "okay";
 335         phy-mode = "sgmii";
 336         qcom,id = <1>;
 337
 338         nvmem-cells = <&macaddr_ART_6>;
 339         nvmem-cell-names = "mac-address";
 340
 341         fixed-link {
 342                 speed = <1000>;
 343                 full-duplex;
 344         };
 345 };
 346
 347 &adm_dma {
 348         status = "okay";
 349 };
 350
 351 &hs_phy_0 {
 352         status = "okay";
 353 };
 354
 355 &ss_phy_0 {
 356         status = "okay";
 357 };
 358
 359 &usb3_0 {
 360         status = "okay";
 361 };
 362
 363 &hs_phy_1 {
 364         status = "okay";
 365 };
 366
 367 &ss_phy_1 {
 368         status = "okay";
 369 };
 370
 371 &usb3_1 {
 372         status = "okay";
 373 };
 374
 375 &pcie0 {
 376         status = "okay";
 377         reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
 378         pinctrl-0 = <&pcie0_pins>;
 379         pinctrl-names = "default";
 380
 381         bridge@0,0 {
 382                 reg = <0x00000000 0 0 0 0>;
 383                 #address-cells = <3>;
 384                 #size-cells = <2>;
 385                 ranges;
 386
 387                 wifi0: wifi@1,0 {
 388                         compatible = "pci168c,0046";
 389                         reg = <0x00010000 0 0 0 0>;
 390
 391                         nvmem-cells = <&precal_ART_1000>;
 392                         nvmem-cell-names = "pre-calibration";
 393                 };
 394         };
 395 };
 396
 397 &pcie1 {
 398         status = "okay";
 399         reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
 400         pinctrl-0 = <&pcie1_pins>;
 401         pinctrl-names = "default";
 402         max-link-speed = <1>;
 403
 404         bridge@0,0 {
 405                 reg = <0x00000000 0 0 0 0>;
 406                 #address-cells = <3>;
 407                 #size-cells = <2>;
 408                 ranges;
 409
 410                 wifi1: wifi@1,0 {
 411                         compatible = "pci168c,0046";
 412                         reg = <0x00010000 0 0 0 0>;
 413
 414                         nvmem-cells = <&precal_ART_5000>;
 415                         nvmem-cell-names = "pre-calibration";
 416                 };
 417         };
 418 };