target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #include "qcom-ipq8065-smb208.dtsi"
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/leds/common.h>
   6
   7 / {
   8         model = "Askey RT4230W REV6";
   9         compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
  10
  11         memory@0 {
  12                 reg = <0x42000000 0x3e000000>;
  13                 device_type = "memory";
  14         };
  15
  16         aliases {
  17                 led-boot = &ledctrl3;
  18                 led-failsafe = &ledctrl1;
  19                 led-running = &ledctrl2;
  20                 led-upgrade = &ledctrl3;
  21         };
  22
  23         chosen {
  24                 bootargs = "rootfstype=squashfs noinitrd";
  25         };
  26
  27         keys {
  28                 compatible = "gpio-keys";
  29                 pinctrl-0 = <&button_pins>;
  30                 pinctrl-names = "default";
  31
  32                 reset {
  33                         label = "reset";
  34                         gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  35                         linux,code = <KEY_RESTART>;
  36                 };
  37
  38                 wps {
  39                         label = "wps";
  40                         gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  41                         linux,code = <KEY_WPS_BUTTON>;
  42                 };
  43         };
  44
  45         leds {
  46                 compatible = "gpio-leds";
  47                 pinctrl-0 = <&led_pins>;
  48                 pinctrl-names = "default";
  49
  50                 ledctrl1: ledctrl1 {
  51                         label = "ledctrl1";
  52                         gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  53                 };
  54
  55                 ledctrl2: ledctrl2 {
  56                         label = "ledctrl2";
  57                         gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  58                 };
  59
  60                 ledctrl3: ledctrl3 {
  61                         label = "ledctrl3";
  62                         gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  63                 };
  64         };
  65 };
  66
  67 &qcom_pinmux {
  68         button_pins: button_pins {
  69                 mux {
  70                         pins = "gpio54", "gpio68";
  71                         function = "gpio";
  72                         drive-strength = <2>;
  73                         bias-pull-up;
  74                 };
  75         };
  76
  77         led_pins: led_pins {
  78                 mux {
  79                         pins = "gpio22", "gpio23", "gpio24";
  80                         function = "gpio";
  81                         drive-strength = <2>;
  82                         bias-pull-down;
  83                 };
  84         };
  85
  86         rgmii2_pins: rgmii2-pins {
  87                 mux {
  88                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
  89                                 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
  90                         function = "rgmii2";
  91                         drive-strength = <8>;
  92                         bias-disable;
  93                 };
  94
  95                 tx {
  96                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  97                         input-disable;
  98                 };
  99         };
 100
 101         spi_pins: spi_pins {
 102                 cs {
 103                         pins = "gpio20";
 104                         drive-strength = <12>;
 105                 };
 106         };
 107 };
 108
 109 &gsbi5 {
 110         qcom,mode = <GSBI_PROT_SPI>;
 111         status = "okay";
 112
 113         spi@1a280000 {
 114                 status = "okay";
 115
 116                 pinctrl-0 = <&spi_pins>;
 117                 pinctrl-names = "default";
 118
 119                 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
 120
 121                 flash@0 {
 122                         compatible = "everspin,mr25h256";
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         spi-max-frequency = <40000000>;
 126                         reg = <0>;
 127                 };
 128         };
 129 };
 130
 131 &nand {
 132         status = "okay";
 133
 134         nand@0 {
 135                 reg = <0>;
 136                 compatible = "qcom,nandcs";
 137
 138                 nand-ecc-strength = <4>;
 139                 nand-bus-width = <8>;
 140                 nand-ecc-step-size = <512>;
 141
 142                 qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>;
 143
 144                 partitions {
 145                         compatible = "fixed-partitions";
 146                         #address-cells = <1>;
 147                         #size-cells = <1>;
 148
 149                         partition@0 {
 150                                 label = "0:SBL1";
 151                                 reg = <0x0000000 0x0040000>;
 152                                 read-only;
 153                         };
 154
 155                         partition@40000 {
 156                                 label = "0:MIBIB";
 157                                 reg = <0x0040000 0x0140000>;
 158                                 read-only;
 159                         };
 160
 161                         partition@180000 {
 162                                 label = "0:SBL2";
 163                                 reg = <0x0180000 0x0140000>;
 164                                 read-only;
 165                         };
 166
 167                         partition@2c0000 {
 168                                 label = "0:SBL3";
 169                                 reg = <0x02c0000 0x0280000>;
 170                                 read-only;
 171                         };
 172
 173                         partition@540000 {
 174                                 label = "0:DDRCONFIG";
 175                                 reg = <0x0540000 0x0120000>;
 176                                 read-only;
 177                         };
 178
 179                         partition@660000 {
 180                                 label = "0:SSD";
 181                                 reg = <0x0660000 0x0120000>;
 182                                 read-only;
 183                         };
 184
 185                         partition@780000 {
 186                                 label = "0:TZ";
 187                                 reg = <0x0780000 0x0280000>;
 188                                 read-only;
 189                         };
 190
 191                         partition@a00000 {
 192                                 label = "0:RPM";
 193                                 reg = <0x0a00000 0x0280000>;
 194                                 read-only;
 195                         };
 196
 197                         partition@c80000 {
 198                                 label = "0:APPSBL";
 199                                 reg = <0x0c80000 0x0500000>;
 200                                 read-only;
 201                         };
 202
 203                         partition@1180000 {
 204                                 label = "0:APPSBLENV";
 205                                 reg = <0x1180000 0x0080000>;
 206                         };
 207
 208                         partition@1200000 {
 209                                 label = "0:ART";
 210                                 reg = <0x1200000 0x0140000>;
 211                                 read-only;
 212
 213                                 nvmem-layout {
 214                                         compatible = "fixed-layout";
 215                                         #address-cells = <1>;
 216                                         #size-cells = <1>;
 217
 218                                         macaddr_ART_0: macaddr@0 {
 219                                                 reg = <0x0 0x6>;
 220                                         };
 221
 222                                         macaddr_ART_6: macaddr@6 {
 223                                                 reg = <0x6 0x6>;
 224                                         };
 225
 226                                         precal_ART_1000: precal@1000 {
 227                                                 reg = <0x1000 0x2f20>;
 228                                         };
 229
 230                                         precal_ART_5000: precal@5000 {
 231                                                 reg = <0x5000 0x2f20>;
 232                                         };
 233                                 };
 234                         };
 235
 236                         partition@1340000 {
 237                                 label = "0:BOOTCONFIG";
 238                                 reg = <0x1340000 0x0060000>;
 239                                 read-only;
 240                         };
 241
 242                         partition@13a0000 {
 243                                 label = "0:SBL2_1";
 244                                 reg = <0x13a0000 0x0140000>;
 245                                 read-only;
 246                         };
 247
 248                         partition@14e0000 {
 249                                 label = "0:SBL3_1";
 250                                 reg = <0x14e0000 0x0280000>;
 251                                 read-only;
 252                         };
 253
 254                         partition@1760000 {
 255                                 label = "0:DDRCONFIG_1";
 256                                 reg = <0x1760000 0x0120000>;
 257                                 read-only;
 258                         };
 259
 260                         partition@1880000 {
 261                                 label = "0:SSD_1";
 262                                 reg = <0x1880000 0x0120000>;
 263                                 read-only;
 264                         };
 265
 266                         partition@19a0000 {
 267                                 label = "0:TZ_1";
 268                                 reg = <0x19a0000 0x0280000>;
 269                                 read-only;
 270                         };
 271
 272                         partition@1c20000 {
 273                                 label = "0:RPM_1";
 274                                 reg = <0x1c20000 0x0280000>;
 275                                 read-only;
 276                         };
 277
 278                         partition@1ea0000 {
 279                                 label = "0:BOOTCONFIG1";
 280                                 reg = <0x1ea0000 0x0060000>;
 281                                 read-only;
 282                         };
 283
 284                         partition@1f00000 {
 285                                 label = "0:APPSBL_1";
 286                                 reg = <0x1f00000 0x0500000>;
 287                                 read-only;
 288                         };
 289
 290                         partition@2400000 {
 291                                 label = "ubi";
 292                                 reg = <0x2400000 0x1a000000>;
 293                         };
 294                 };
 295         };
 296 };
 297
 298 &mdio0 {
 299         status = "okay";
 300
 301         pinctrl-0 = <&mdio0_pins>;
 302         pinctrl-names = "default";
 303
 304         switch@10 {
 305                 compatible = "qca,qca8337";
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308                 reg = <0x10>;
 309
 310                 ports {
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313
 314                         port@0 {
 315                                 reg = <0>;
 316                                 label = "cpu";
 317                                 ethernet = <&gmac0>;
 318                                 phy-mode = "rgmii";
 319                                 tx-internal-delay-ps = <1000>;
 320                                 rx-internal-delay-ps = <1000>;
 321
 322                                 fixed-link {
 323                                         speed = <1000>;
 324                                         full-duplex;
 325                                 };
 326                         };
 327
 328                         port@1 {
 329                                 reg = <1>;
 330                                 label = "wan";
 331                                 phy-mode = "internal";
 332                                 phy-handle = <&phy_port1>;
 333
 334                                 leds {
 335                                         #address-cells = <1>;
 336                                         #size-cells = <0>;
 337
 338                                         led@0 {
 339                                                 reg = <0>;
 340                                                 color = <LED_COLOR_ID_GREEN>;
 341                                                 function = LED_FUNCTION_WAN;
 342                                                 default-state = "keep";
 343                                         };
 344
 345                                         led@1 {
 346                                                 reg = <1>;
 347                                                 color = <LED_COLOR_ID_AMBER>;
 348                                                 function = LED_FUNCTION_WAN;
 349                                                 default-state = "keep";
 350                                         };
 351                                 };
 352                         };
 353
 354                         port@2 {
 355                                 reg = <2>;
 356                                 label = "lan1";
 357                                 phy-mode = "internal";
 358                                 phy-handle = <&phy_port2>;
 359
 360                                 leds {
 361                                         #address-cells = <1>;
 362                                         #size-cells = <0>;
 363
 364                                         led@0 {
 365                                                 reg = <0>;
 366                                                 color = <LED_COLOR_ID_GREEN>;
 367                                                 function = LED_FUNCTION_LAN;
 368                                                 default-state = "keep";
 369                                         };
 370
 371                                         led@1 {
 372                                                 reg = <1>;
 373                                                 color = <LED_COLOR_ID_AMBER>;
 374                                                 function = LED_FUNCTION_LAN;
 375                                                 default-state = "keep";
 376                                         };
 377                                 };
 378                         };
 379
 380                         port@3 {
 381                                 reg = <3>;
 382                                 label = "lan2";
 383                                 phy-mode = "internal";
 384                                 phy-handle = <&phy_port3>;
 385
 386                                 leds {
 387                                         #address-cells = <1>;
 388                                         #size-cells = <0>;
 389
 390                                         led@0 {
 391                                                 reg = <0>;
 392                                                 color = <LED_COLOR_ID_GREEN>;
 393                                                 function = LED_FUNCTION_LAN;
 394                                                 default-state = "keep";
 395                                         };
 396
 397                                         led@1 {
 398                                                 reg = <1>;
 399                                                 color = <LED_COLOR_ID_AMBER>;
 400                                                 function = LED_FUNCTION_LAN;
 401                                                 default-state = "keep";
 402                                         };
 403                                 };
 404                         };
 405
 406                         port@4 {
 407                                 reg = <4>;
 408                                 label = "lan3";
 409                                 phy-mode = "internal";
 410                                 phy-handle = <&phy_port4>;
 411
 412                                 leds {
 413                                         #address-cells = <1>;
 414                                         #size-cells = <0>;
 415
 416                                         led@0 {
 417                                                 reg = <0>;
 418                                                 color = <LED_COLOR_ID_GREEN>;
 419                                                 function = LED_FUNCTION_LAN;
 420                                                 default-state = "keep";
 421                                         };
 422
 423                                         led@1 {
 424                                                 reg = <1>;
 425                                                 color = <LED_COLOR_ID_AMBER>;
 426                                                 function = LED_FUNCTION_LAN;
 427                                                 default-state = "keep";
 428                                         };
 429                                 };
 430                         };
 431
 432                         port@5 {
 433                                 reg = <5>;
 434                                 label = "lan4";
 435                                 phy-mode = "internal";
 436                                 phy-handle = <&phy_port5>;
 437
 438                                 leds {
 439                                         #address-cells = <1>;
 440                                         #size-cells = <0>;
 441
 442                                         led@0 {
 443                                                 reg = <0>;
 444                                                 color = <LED_COLOR_ID_GREEN>;
 445                                                 function = LED_FUNCTION_LAN;
 446                                                 default-state = "keep";
 447                                         };
 448
 449                                         led@1 {
 450                                                 reg = <1>;
 451                                                 color = <LED_COLOR_ID_AMBER>;
 452                                                 function = LED_FUNCTION_LAN;
 453                                                 default-state = "keep";
 454                                         };
 455                                 };
 456                         };
 457
 458                         port@6 {
 459                                 reg = <6>;
 460                                 label = "cpu";
 461                                 ethernet = <&gmac1>;
 462                                 phy-mode = "sgmii";
 463                                 qca,sgmii-enable-pll;
 464
 465                                 fixed-link {
 466                                         speed = <1000>;
 467                                         full-duplex;
 468                                 };
 469                         };
 470                 };
 471
 472                 mdio {
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475
 476                         phy_port1: phy@0 {
 477                                 reg = <0>;
 478                         };
 479
 480                         phy_port2: phy@1 {
 481                                 reg = <1>;
 482                         };
 483
 484                         phy_port3: phy@2 {
 485                                 reg = <2>;
 486                         };
 487
 488                         phy_port4: phy@3 {
 489                                 reg = <3>;
 490                         };
 491
 492                         phy_port5: phy@4 {
 493                                 reg = <4>;
 494                         };
 495                 };
 496         };
 497 };
 498
 499 &gmac0 {
 500         status = "okay";
 501         phy-mode = "rgmii";
 502         qcom,id = <0>;
 503
 504         nvmem-cells = <&macaddr_ART_0>;
 505         nvmem-cell-names = "mac-address";
 506
 507         pinctrl-0 = <&rgmii2_pins>;
 508         pinctrl-names = "default";
 509
 510         fixed-link {
 511                 speed = <1000>;
 512                 full-duplex;
 513         };
 514 };
 515
 516 &gmac1 {
 517         status = "okay";
 518         phy-mode = "sgmii";
 519         qcom,id = <1>;
 520
 521         nvmem-cells = <&macaddr_ART_6>;
 522         nvmem-cell-names = "mac-address";
 523
 524         fixed-link {
 525                 speed = <1000>;
 526                 full-duplex;
 527         };
 528 };
 529
 530 &adm_dma {
 531         status = "okay";
 532 };
 533
 534 &hs_phy_0 {
 535         status = "okay";
 536 };
 537
 538 &ss_phy_0 {
 539         status = "okay";
 540 };
 541
 542 &usb3_0 {
 543         status = "okay";
 544 };
 545
 546 &hs_phy_1 {
 547         status = "okay";
 548 };
 549
 550 &ss_phy_1 {
 551         status = "okay";
 552 };
 553
 554 &usb3_1 {
 555         status = "okay";
 556 };
 557
 558 &pcie0 {
 559         status = "okay";
 560         reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
 561         pinctrl-0 = <&pcie0_pins>;
 562         pinctrl-names = "default";
 563
 564         bridge@0,0 {
 565                 reg = <0x00000000 0 0 0 0>;
 566                 #address-cells = <3>;
 567                 #size-cells = <2>;
 568                 ranges;
 569
 570                 wifi0: wifi@1,0 {
 571                         compatible = "pci168c,0046";
 572                         reg = <0x00010000 0 0 0 0>;
 573
 574                         nvmem-cells = <&precal_ART_1000>;
 575                         nvmem-cell-names = "pre-calibration";
 576                 };
 577         };
 578 };
 579
 580 &pcie1 {
 581         status = "okay";
 582         reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
 583         pinctrl-0 = <&pcie1_pins>;
 584         pinctrl-names = "default";
 585         max-link-speed = <1>;
 586
 587         bridge@0,0 {
 588                 reg = <0x00000000 0 0 0 0>;
 589                 #address-cells = <3>;
 590                 #size-cells = <2>;
 591                 ranges;
 592
 593                 wifi1: wifi@1,0 {
 594                         compatible = "pci168c,0046";
 595                         reg = <0x00010000 0 0 0 0>;
 596
 597                         nvmem-cells = <&precal_ART_5000>;
 598                         nvmem-cell-names = "pre-calibration";
 599                 };
 600         };
 601 };