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[openwrt/openwrt.git] / target / linux / ipq806x / files-6.1 / arch / arm / boot / dts / qcom-ipq8064-onhub.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2014 The ChromiumOS Authors
4 */
5
6 #include "qcom-ipq8064-smb208.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/soc/qcom,tcsr.h>
10
11 / {
12 aliases {
13 ethernet0 = &gmac0;
14 ethernet1 = &gmac2;
15 mdio-gpio0 = &mdio;
16 serial0 = &gsbi4_serial;
17 };
18
19 chosen {
20 stdout-path = "serial0:115200n8";
21 };
22
23 reserved-memory {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 rsvd@41200000 {
29 reg = <0x41200000 0x300000>;
30 no-map;
31 };
32 };
33
34 keys {
35 compatible = "gpio-keys";
36 pinctrl-0 = <&button_pins>;
37 pinctrl-names = "default";
38
39 reset {
40 label = "reset";
41 gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_RESTART>;
43 debounce-interval = <60>;
44 wakeup-source;
45 };
46
47 dev {
48 label = "dev";
49 gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
50 linux,code = <KEY_CONFIG>;
51 debounce-interval = <60>;
52 wakeup-source;
53 };
54 };
55
56 mdio: mdio {
57 compatible = "virtual,mdio-gpio";
58 #address-cells = <1>;
59 #size-cells = <0>;
60 gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
61 <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
62 pinctrl-0 = <&mdio_pins>;
63 pinctrl-names = "default";
64
65 phy0: ethernet-phy@0 {
66 reg = <0>;
67 qca,ar8327-initvals = <
68 0x00004 0x7600000 /* PAD0_MODE */
69 0x00008 0x1000000 /* PAD5_MODE */
70 0x0000c 0x80 /* PAD6_MODE */
71 0x000e4 0xaa545 /* MAC_POWER_SEL */
72 0x000e0 0xc74164de /* SGMII_CTRL */
73 0x0007c 0x4e /* PORT0_STATUS */
74 0x00094 0x4e /* PORT6_STATUS */
75 >;
76 };
77
78 phy1: ethernet-phy@1 {
79 reg = <1>;
80 };
81 };
82
83 soc {
84 rng@1a500000 {
85 status = "disabled";
86 };
87
88 sound {
89 compatible = "google,storm-audio";
90 qcom,model = "ipq806x-storm";
91 cpu = <&lpass>;
92 codec = <&max98357a>;
93 };
94
95 lpass: lpass@28100000 {
96 status = "okay";
97 pinctrl-names = "default", "idle";
98 pinctrl-0 = <&mi2s_default>;
99 pinctrl-1 = <&mi2s_idle>;
100 };
101
102 max98357a: max98357a {
103 compatible = "maxim,max98357a";
104 #sound-dai-cells = <1>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&sdmode_pins>;
107 sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
108 };
109 };
110 };
111
112 &qcom_pinmux {
113 rgmii0_pins: rgmii0_pins {
114 mux {
115 pins = "gpio2", "gpio66";
116 drive-strength = <8>;
117 bias-disable;
118 };
119 };
120 mi2s_pins {
121 mi2s_default: mi2s_default {
122 dout {
123 pins = "gpio32";
124 function = "mi2s";
125 drive-strength = <16>;
126 bias-disable;
127 };
128 sync {
129 pins = "gpio27";
130 function = "mi2s";
131 drive-strength = <16>;
132 bias-disable;
133 };
134 clk {
135 pins = "gpio28";
136 function = "mi2s";
137 drive-strength = <16>;
138 bias-disable;
139 };
140 };
141 mi2s_idle: mi2s_idle {
142 dout {
143 pins = "gpio32";
144 function = "mi2s";
145 drive-strength = <2>;
146 bias-pull-down;
147 };
148 sync {
149 pins = "gpio27";
150 function = "mi2s";
151 drive-strength = <2>;
152 bias-pull-down;
153 };
154 clk {
155 pins = "gpio28";
156 function = "mi2s";
157 drive-strength = <2>;
158 bias-pull-down;
159 };
160 };
161 };
162
163 mdio_pins: mdio_pins {
164 mux {
165 pins = "gpio0", "gpio1";
166 function = "gpio";
167 drive-strength = <8>;
168 bias-disable;
169 };
170 rst {
171 pins = "gpio26";
172 output-low;
173 };
174 };
175
176 sdmode_pins: sdmode_pinmux {
177 pins = "gpio25";
178 function = "gpio";
179 drive-strength = <16>;
180 bias-disable;
181 };
182
183 sdcc1_pins: sdcc1_pinmux {
184 mux {
185 pins = "gpio38", "gpio39", "gpio40",
186 "gpio41", "gpio42", "gpio43",
187 "gpio44", "gpio45", "gpio46",
188 "gpio47";
189 function = "sdc1";
190 };
191 cmd {
192 pins = "gpio45";
193 drive-strength = <10>;
194 bias-pull-up;
195 };
196 data {
197 pins = "gpio38", "gpio39", "gpio40",
198 "gpio41", "gpio43", "gpio44",
199 "gpio46", "gpio47";
200 drive-strength = <10>;
201 bias-pull-up;
202 };
203 clk {
204 pins = "gpio42";
205 drive-strength = <16>;
206 bias-pull-down;
207 };
208 };
209
210 i2c1_pins: i2c1_pinmux {
211 pins = "gpio53", "gpio54";
212 function = "gsbi1";
213 bias-disable;
214 };
215
216 rpm_i2c_pinmux: rpm_i2c_pinmux {
217 mux {
218 pins = "gpio12", "gpio13";
219 function = "gsbi4";
220 drive-strength = <12>;
221 bias-disable;
222 };
223 };
224
225 spi_pins: spi_pins {
226 mux {
227 pins = "gpio18", "gpio19", "gpio21";
228 function = "gsbi5";
229 bias-pull-down;
230 /delete-property/ bias-none;
231 /delete-property/ drive-strength;
232 };
233 data {
234 pins = "gpio18", "gpio19";
235 drive-strength = <10>;
236 };
237 cs {
238 pins = "gpio20";
239 drive-strength = <10>;
240 bias-pull-up;
241 };
242 clk {
243 pins = "gpio21";
244 drive-strength = <12>;
245 };
246 };
247
248 fw_pinmux {
249 wp {
250 pins = "gpio17";
251 output-low;
252 };
253 };
254
255 button_pins: button_pins {
256 recovery {
257 pins = "gpio16";
258 function = "gpio";
259 bias-none;
260 };
261 developer {
262 pins = "gpio15";
263 function = "gpio";
264 bias-none;
265 };
266 };
267
268 spi6_pins: spi6_pins {
269 mux {
270 pins = "gpio55", "gpio56", "gpio58";
271 function = "gsbi6";
272 bias-pull-down;
273 };
274 data {
275 pins = "gpio55", "gpio56";
276 drive-strength = <10>;
277 };
278 cs {
279 pins = "gpio57";
280 drive-strength = <10>;
281 bias-pull-up;
282 output-high;
283 };
284 clk {
285 pins = "gpio58";
286 drive-strength = <12>;
287 };
288 };
289 };
290
291 &gmac0 {
292 status = "okay";
293 phy-mode = "rgmii";
294 qcom,id = <0>;
295 phy-handle = <&phy1>;
296
297 pinctrl-0 = <&rgmii0_pins>;
298 pinctrl-names = "default";
299
300 fixed-link {
301 speed = <1000>;
302 full-duplex;
303 };
304 };
305
306 &gmac2 {
307 status = "okay";
308 phy-mode = "sgmii";
309 qcom,id = <2>;
310 phy-handle = <&phy0>;
311
312 fixed-link {
313 speed = <1000>;
314 full-duplex;
315 };
316 };
317
318 &gsbi1 {
319 status = "okay";
320 qcom,mode = <GSBI_PROT_I2C_UART>;
321 };
322
323 &gsbi1_i2c {
324 status = "okay";
325
326 clock-frequency = <100000>;
327
328 pinctrl-0 = <&i2c1_pins>;
329 pinctrl-names = "default";
330
331 tpm@20 {
332 compatible = "infineon,slb9645tt";
333 reg = <0x20>;
334 powered-while-suspended;
335 };
336 };
337
338 &gsbi4 {
339 status = "okay";
340 qcom,mode = <GSBI_PROT_I2C_UART>;
341 };
342
343 &gsbi4_serial {
344 status = "okay";
345 };
346
347 &gsbi5 {
348 status = "okay";
349 qcom,mode = <GSBI_PROT_SPI>;
350
351 spi4: spi@1a280000 {
352 status = "okay";
353 spi-max-frequency = <50000000>;
354 pinctrl-0 = <&spi_pins>;
355 pinctrl-names = "default";
356
357 cs-gpios = <&qcom_pinmux 20 0>;
358
359 flash: flash@0 {
360 compatible = "jedec,spi-nor";
361 spi-max-frequency = <50000000>;
362 reg = <0>;
363 };
364 };
365 };
366
367 &gsbi6 {
368 status = "okay";
369 qcom,mode = <GSBI_PROT_SPI>;
370 };
371
372 &gsbi6_spi {
373 status = "okay";
374 spi-max-frequency = <25000000>;
375
376 pinctrl-0 = <&spi6_pins>;
377 pinctrl-names = "default";
378
379 cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
380
381 dmas = <&adm_dma 8 0xb>,
382 <&adm_dma 7 0x14>;
383 dma-names = "rx", "tx";
384
385 /*
386 * This "spidev" was included in the manufacturer device tree. I suspect
387 * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
388 * no driver or binding for this at the moment.
389 */
390 spidev@0 {
391 compatible = "spidev";
392 reg = <0>;
393 spi-max-frequency = <25000000>;
394 };
395 };
396
397 &pcie0 {
398 status = "okay";
399
400 pcie@0 {
401 reg = <0 0 0 0 0>;
402 #interrupt-cells = <1>;
403 #size-cells = <2>;
404 #address-cells = <3>;
405 device_type = "pci";
406
407 ath10k@0,0 {
408 reg = <0 0 0 0 0>;
409 device_type = "pci";
410 qcom,ath10k-sa-gpio = <2 3 4 0>;
411 qcom,ath10k-sa-gpio-func = <5 5 5 0>;
412 };
413 };
414 };
415
416 &pcie1 {
417 status = "okay";
418
419 pcie@0 {
420 reg = <0 0 0 0 0>;
421 #interrupt-cells = <1>;
422 #size-cells = <2>;
423 #address-cells = <3>;
424 device_type = "pci";
425
426 ath10k@0,0 {
427 reg = <0 0 0 0 0>;
428 device_type = "pci";
429 qcom,ath10k-sa-gpio = <2 3 4 0>;
430 qcom,ath10k-sa-gpio-func = <5 5 5 0>;
431 };
432 };
433 };
434
435 &pcie2 {
436 status = "okay";
437
438 pcie@0 {
439 reg = <0 0 0 0 0>;
440 #interrupt-cells = <1>;
441 #size-cells = <2>;
442 #address-cells = <3>;
443 device_type = "pci";
444
445 ath10k@0,0 {
446 reg = <0 0 0 0 0>;
447 device_type = "pci";
448 };
449 };
450 };
451
452 &rpm {
453 pinctrl-0 = <&rpm_i2c_pinmux>;
454 pinctrl-names = "default";
455 };
456
457 &sdcc1 {
458 status = "okay";
459 pinctrl-0 = <&sdcc1_pins>;
460 pinctrl-names = "default";
461 /delete-property/ mmc-ddr-1_8v;
462 };
463
464 &tcsr {
465 compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
466 qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
467 };
468
469 &hs_phy_0 {
470 status = "okay";
471 };
472
473 &ss_phy_0 {
474 status = "okay";
475 };
476
477 &usb3_0 {
478 status = "okay";
479 };
480
481 &hs_phy_1 {
482 status = "okay";
483 };
484
485 &ss_phy_1 {
486 status = "okay";
487 };
488
489 &usb3_1 {
490 status = "okay";
491 };
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