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c1c21856ca5fb04ec9889aa4b1adc41ef045cddb
[openwrt/openwrt.git] / target / linux / ipq806x / files-5.10 / arch / arm / boot / dts / qcom-ipq8062-wg2600hp3.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qcom-ipq8062.dtsi"
4 #include <dt-bindings/input/input.h>
5
6 /delete-node/ &nand_pins;
7
8 / {
9 model = "NEC Platforms Aterm WG2600HP3";
10 compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064";
11
12 memory {
13 device_type = "memory";
14 reg = <0x42000000 0x1e000000>;
15 };
16
17 aliases {
18 label-mac-device = &gmac2;
19
20 led-boot = &led_power_green;
21 led-failsafe = &led_power_red;
22 led-running = &led_power_green;
23 led-upgrade = &led_power_red;
24 };
25
26 keys {
27 compatible = "gpio-keys";
28
29 pinctrl-0 = <&buttons_pins>;
30 pinctrl-names = "default";
31
32 reset {
33 label = "reset";
34 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_RESTART>;
36 debounce-interval = <60>;
37 wakeup-source;
38 };
39
40 wps {
41 label = "wps";
42 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
43 linux,code = <KEY_WPS_BUTTON>;
44 debounce-interval = <60>;
45 wakeup-source;
46 };
47
48 mode0 {
49 label = "mode0";
50 gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>;
51 linux,code = <BTN_0>;
52 linux,input-type = <EV_SW>;
53 debounce-interval = <60>;
54 wakeup-source;
55 };
56
57 mode1 {
58 label = "mode1";
59 gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>;
60 linux,code = <BTN_1>;
61 linux,input-type = <EV_SW>;
62 debounce-interval = <60>;
63 wakeup-source;
64 };
65 };
66
67 leds {
68 compatible = "gpio-leds";
69
70 pinctrl-0 = <&leds_pins>;
71 pinctrl-names = "default";
72
73 led_power_green: power_green {
74 label = "green:power";
75 gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
76 };
77
78 led_power_red: power_red {
79 label = "red:power";
80 gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;
81 };
82
83 active_green {
84 label = "green:active";
85 gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>;
86 };
87
88 active_red {
89 label = "red:active";
90 gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>;
91 };
92
93 wlan2g_green {
94 label = "green:wlan2g";
95 gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
96 linux,default-trigger = "phy1tpt";
97 };
98
99 wlan2g_red {
100 label = "red:wlan2g";
101 gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
102 };
103
104 wlan5g_green {
105 label = "green:wlan5g";
106 gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
107 linux,default-trigger = "phy0tpt";
108 };
109
110 wlan5g_red {
111 label = "red:wlan5g";
112 gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
113 };
114
115 tv_green {
116 label = "green:tv";
117 gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>;
118 };
119
120 tv_red {
121 label = "red:tv";
122 gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>;
123 };
124
125 converter_green {
126 label = "green:converter";
127 gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>;
128 };
129
130 converter_red {
131 label = "red:converter";
132 gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
133 };
134 };
135 };
136
137 &qcom_pinmux {
138 pinctrl-0 = <&akro_pins>;
139 pinctrl-names = "default";
140
141 spi_pins: spi_pins {
142 mux {
143 pins = "gpio18", "gpio19", "gpio21";
144 function = "gsbi5";
145 bias-pull-down;
146 };
147
148 data {
149 pins = "gpio18", "gpio19";
150 drive-strength = <10>;
151 };
152
153 cs {
154 pins = "gpio20";
155 drive-strength = <10>;
156 };
157
158 clk {
159 pins = "gpio21";
160 drive-strength = <12>;
161 };
162 };
163
164 buttons_pins: buttons_pins {
165 mux {
166 pins = "gpio22", "gpio24", "gpio40",
167 "gpio41";
168 function = "gpio";
169 drive-strength = <2>;
170 bias-pull-up;
171 };
172 };
173
174 leds_pins: leds_pins {
175 mux {
176 pins = "gpio14", "gpio15", "gpio35",
177 "gpio36", "gpio38", "gpio42",
178 "gpio43", "gpio46", "gpio55",
179 "gpio56", "gpio57", "gpio58";
180 function = "gpio";
181 bias-pull-down;
182 };
183
184 akro2 {
185 pins = "gpio15", "gpio35", "gpio38",
186 "gpio42", "gpio43", "gpio46",
187 "gpio55", "gpio56", "gpio57",
188 "gpio58";
189 drive-strength = <2>;
190 };
191
192 akro4 {
193 pins = "gpio14", "gpio36";
194 drive-strength = <4>;
195 };
196 };
197
198 /*
199 * Stock firmware has the following settings, so let's do the same.
200 * I don't sure why these are required.
201 */
202 akro_pins: akro_pinmux {
203 akro {
204 pins = "gpio17", "gpio26", "gpio47";
205 function = "gpio";
206 drive-strength = <2>;
207 bias-pull-down;
208 };
209
210 reset {
211 pins = "gpio45";
212 function = "gpio";
213 drive-strength = <2>;
214 bias-disable;
215 output-low;
216 };
217
218 gmac0_rgmii {
219 pins = "gpio25";
220 function = "gpio";
221 drive-strength = <8>;
222 bias-disable;
223 };
224 };
225 };
226
227 &gsbi5 {
228 status = "okay";
229 qcom,mode = <GSBI_PROT_SPI>;
230
231 spi@1a280000 {
232 status = "okay";
233
234 pinctrl-0 = <&spi_pins>;
235 pinctrl-names = "default";
236
237 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
238
239 flash@0 {
240 compatible = "jedec,spi-nor";
241 reg = <0>;
242 spi-max-frequency = <50000000>;
243 m25p,fast-read;
244
245 partitions {
246 compatible = "fixed-partitions";
247 #address-cells = <1>;
248 #size-cells = <1>;
249
250 partition@0 {
251 label = "SBL1";
252 reg = <0x0000000 0x0020000>;
253 read-only;
254 };
255
256 partition@20000 {
257 label = "MIBIB";
258 reg = <0x0020000 0x0020000>;
259 read-only;
260 };
261
262 partition@40000 {
263 label = "SBL2";
264 reg = <0x0040000 0x0040000>;
265 read-only;
266 };
267
268 partition@80000 {
269 label = "SBL3";
270 reg = <0x0080000 0x0080000>;
271 read-only;
272 };
273
274 partition@100000 {
275 label = "DDRCONFIG";
276 reg = <0x0100000 0x0010000>;
277 read-only;
278 };
279
280 partition@110000 {
281 label = "SSD";
282 reg = <0x0110000 0x0010000>;
283 read-only;
284 };
285
286 partition@120000 {
287 label = "TZ";
288 reg = <0x0120000 0x0080000>;
289 read-only;
290 };
291
292 partition@1a0000 {
293 label = "RPM";
294 reg = <0x01a0000 0x0080000>;
295 read-only;
296 };
297
298 partition@220000 {
299 label = "APPSBL";
300 reg = <0x0220000 0x0080000>;
301 read-only;
302 };
303
304 partition@2a0000 {
305 label = "APPSBLENV";
306 reg = <0x02a0000 0x0010000>;
307 read-only;
308 };
309
310 factory: partition@2b0000 {
311 label = "PRODUCTDATA";
312 reg = <0x02b0000 0x0030000>;
313 read-only;
314 };
315
316 partition@2e0000 {
317 label = "ART";
318 reg = <0x02e0000 0x0040000>;
319 read-only;
320 compatible = "nvmem-cells";
321 #address-cells = <1>;
322 #size-cells = <1>;
323
324 precal_ART_1000: precal@1000 {
325 reg = <0x1000 0x2f20>;
326 };
327
328 precal_ART_5000: precal@5000 {
329 reg = <0x5000 0x2f20>;
330 };
331 };
332
333 partition@320000 {
334 label = "TP";
335 reg = <0x0320000 0x0040000>;
336 read-only;
337 };
338
339 partition@360000 {
340 label = "TINY";
341 reg = <0x0360000 0x0500000>;
342 read-only;
343 };
344
345 partition@860000 {
346 compatible = "denx,uimage";
347 label = "firmware";
348 reg = <0x0860000 0x17a0000>;
349 };
350 };
351 };
352 };
353 };
354
355 &adm_dma {
356 status = "okay";
357 };
358
359 &pcie0 {
360 status = "okay";
361
362 bridge@0,0 {
363 reg = <0x00000000 0 0 0 0>;
364 #address-cells = <3>;
365 #size-cells = <2>;
366 ranges;
367
368 wifi@1,0 {
369 compatible = "qcom,ath10k";
370 reg = <0x00010000 0 0 0 0>;
371
372 qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
373
374 nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
375 nvmem-cell-names = "mac-address", "pre-calibration";
376 };
377 };
378 };
379
380 &pcie1 {
381 status = "okay";
382 force_gen1 = <1>;
383
384 bridge@0,0 {
385 reg = <0x00000000 0 0 0 0>;
386 #address-cells = <3>;
387 #size-cells = <2>;
388 ranges;
389
390 wifi@1,0 {
391 compatible = "qcom,ath10k";
392 reg = <0x00010000 0 0 0 0>;
393
394 ieee80211-freq-limit = <2400000 2483000>;
395 qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
396
397 nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
398 nvmem-cell-names = "mac-address", "pre-calibration";
399 };
400 };
401 };
402
403 &mdio0 {
404 status = "okay";
405
406 pinctrl-0 = <&mdio0_pins>;
407 pinctrl-names = "default";
408
409 phy0: ethernet-phy@0 {
410 reg = <0>;
411 qca,ar8327-initvals = <
412 0x04 0x80080080 /* PAD0_MODE */
413 0x0c 0x06000000 /* PAD6_MODE */
414 0x10 0x002613a0 /* PWS_REG */
415 0x50 0xcc36cc36 /* LED_CTRL0 */
416 0x54 0xca36ca36 /* LED_CTRL1 */
417 0x58 0xc936c936 /* LED_CTRL2 */
418 0x5c 0x03ffff00 /* LED_CTRL3 */
419 0x7c 0x0000004e /* PORT0_STATUS */
420 0x94 0x0000004e /* PORT6_STATUS */
421 0xe0 0xc74164de /* SGMII_CTRL */
422 0xe4 0x0006a545 /* MAC_PWR_SEL */
423 >;
424 };
425 };
426
427 &gmac1 {
428 status = "okay";
429
430 pinctrl-0 = <&rgmii2_pins>;
431 pinctrl-names = "default";
432
433 phy-mode = "rgmii";
434 qcom,id = <1>;
435 mdiobus = <&mdio0>;
436 nvmem-cells = <&macaddr_factory_0>;
437 nvmem-cell-names = "mac-address";
438
439 fixed-link {
440 speed = <1000>;
441 full-duplex;
442 };
443 };
444
445 &gmac2 {
446 status = "okay";
447 phy-mode = "sgmii";
448 qcom,id = <2>;
449 mdiobus = <&mdio0>;
450 nvmem-cells = <&macaddr_factory_6>;
451 nvmem-cell-names = "mac-address";
452
453 fixed-link {
454 speed = <1000>;
455 full-duplex;
456 };
457 };
458
459 &factory {
460 compatible = "nvmem-cells";
461 #address-cells = <1>;
462 #size-cells = <1>;
463
464 macaddr_factory_0: macaddr@0 {
465 reg = <0x0 0x6>;
466 };
467
468 macaddr_factory_6: macaddr@6 {
469 reg = <0x6 0x6>;
470 };
471
472 macaddr_PRODUCTDATA_c: macaddr@c {
473 reg = <0xc 0x6>;
474 };
475
476 macaddr_PRODUCTDATA_12: macaddr@12 {
477 reg = <0x12 0x6>;
478 };
479 };
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