target/linux/generic/pending-6.6/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch

   1 From patchwork Thu Feb  1 21:52:20 2024
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   5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
   6 X-Patchwork-Id: 13541842
   7 Date: Thu, 1 Feb 2024 21:52:20 +0000
   8 From: Daniel Golle <daniel@makrotopia.org>
   9 To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
  10         Steven Liu <steven.liu@mediatek.com>,
  11         John Crispin <john@phrozen.org>,
  12         Chunfeng Yun <chunfeng.yun@mediatek.com>,
  13         Vinod Koul <vkoul@kernel.org>,
  14         Kishon Vijay Abraham I <kishon@kernel.org>,
  15         Rob Herring <robh@kernel.org>,
  16         Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
  17         Conor Dooley <conor+dt@kernel.org>,
  18         Daniel Golle <daniel@makrotopia.org>,
  19         Qingfang Deng <dqfext@gmail.com>,
  20         SkyLake Huang <SkyLake.Huang@mediatek.com>,
  21         Matthias Brugger <matthias.bgg@gmail.com>,
  22         AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
  23         Philipp Zabel <p.zabel@pengutronix.de>,
  24         linux-arm-kernel@lists.infradead.org,
  25         linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
  26         devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
  27         netdev@vger.kernel.org
  28 Subject: [PATCH 1/2] dt-bindings: phy: mediatek,xfi-tphy: add new bindings
  29 Message-ID:
  30  <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
  31 MIME-Version: 1.0
  32 Content-Disposition: inline
  33 List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
  34
  35 Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the
  36 MediaTek MT7988 SoC which can operate at various interfaces modes:
  37
  38 via USXGMII PCS:
  39  * USXGMII
  40  * 10GBase-R
  41  * 5GBase-R
  42
  43 via LynxI SGMII PCS:
  44  * 2500Base-X
  45  * 1000Base-X
  46  * Cisco SGMII (MAC side)
  47
  48 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  49 ---
  50  .../bindings/phy/mediatek,xfi-tphy.yaml       | 80 +++++++++++++++++++
  51  1 file changed, 80 insertions(+)
  52  create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
  53
  54 --- /dev/null
  55 +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
  56 @@ -0,0 +1,80 @@
  57 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  58 +%YAML 1.2
  59 +---
  60 +$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml#
  61 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  62 +
  63 +title: MediaTek XFI T-PHY
  64 +
  65 +maintainers:
  66 +  - Daniel Golle <daniel@makrotopia.org>
  67 +
  68 +description:
  69 +  The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
  70 +  used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
  71 +  MediaTek's 10G-capabale SoCs.
  72 +
  73 +properties:
  74 +  $nodename:
  75 +    pattern: "^phy@[0-9a-f]+$"
  76 +
  77 +  compatible:
  78 +    const: mediatek,mt7988-xfi-tphy
  79 +
  80 +  reg:
  81 +    maxItems: 1
  82 +
  83 +  clocks:
  84 +    items:
  85 +      - description: XFI PHY clock
  86 +      - description: XFI register clock
  87 +
  88 +  clock-names:
  89 +    items:
  90 +      - const: xfipll
  91 +      - const: topxtal
  92 +
  93 +  resets:
  94 +    items:
  95 +      - description: PEXTP reset
  96 +
  97 +  mediatek,usxgmii-performance-errata:
  98 +    $ref: /schemas/types.yaml#/definitions/flag
  99 +    description:
 100 +      One instance of the T-PHY on MT7988 suffers from a performance
 101 +      problem in 10GBase-R mode which needs a work-around in the driver.
 102 +      The work-around is enabled using this flag.
 103 +
 104 +  "#phy-cells":
 105 +    const: 0
 106 +
 107 +required:
 108 +  - compatible
 109 +  - reg
 110 +  - clocks
 111 +  - clock-names
 112 +  - resets
 113 +  - "#phy-cells"
 114 +
 115 +additionalProperties: false
 116 +
 117 +examples:
 118 +  - |
 119 +    #include <dt-bindings/clock/mediatek,mt7988-clk.h>
 120 +    soc {
 121 +      #address-cells = <2>;
 122 +      #size-cells = <2>;
 123 +
 124 +      phy@11f20000 {
 125 +        compatible = "mediatek,mt7988-xfi-tphy";
 126 +        reg = <0 0x11f20000 0 0x10000>;
 127 +        clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
 128 +                 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
 129 +        clock-names = "xfipll", "topxtal";
 130 +        resets = <&watchdog 14>;
 131 +        mediatek,usxgmii-performance-errata;
 132 +        #phy-cells = <0>;
 133 +      };
 134 +    };
 135 +
 136 +...