target/linux/generic/pending-6.1/852-clk-bcm-Add-BCM63268-timer-clock-and-reset-driver.patch

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  65 From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?=  <noltari@gmail.com>
  66 To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
  67         krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de,
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  69         william.zhang@broadcom.com, linux-clk@vger.kernel.org,
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  71 Cc: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?=  <noltari@gmail.com>
  72 Subject: [PATCH v4 4/4] clk: bcm: Add BCM63268 timer clock and reset driver
  73 Date: Wed, 22 Mar 2023 18:15:15 +0100
  74 Message-Id: <20230322171515.120353-5-noltari@gmail.com>
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  80 List-ID: <linux-clk.vger.kernel.org>
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  82
  83 Add driver for BCM63268 timer clock and reset controller.
  84
  85 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
  86 ---
  87  v4: add changes suggested by Stephen Boyd:
  88   - Usage of of_device_get_match_data() isn't needed.
  89   - Use devm_clk_hw_register_gate().
  90   - Drop clk_hw_unregister_gate().
  91  v3: add missing <linux/io.h> include to fix build warning
  92  v2: add changes suggested by Stephen Boyd
  93
  94  drivers/clk/bcm/Kconfig              |   9 ++
  95  drivers/clk/bcm/Makefile             |   1 +
  96  drivers/clk/bcm/clk-bcm63268-timer.c | 215 +++++++++++++++++++++++++++
  97  3 files changed, 225 insertions(+)
  98  create mode 100644 drivers/clk/bcm/clk-bcm63268-timer.c
  99
 100 --- a/drivers/clk/bcm/Kconfig
 101 +++ b/drivers/clk/bcm/Kconfig
 102 @@ -37,6 +37,15 @@ config CLK_BCM_63XX_GATE
 103           Enable common clock framework support for Broadcom BCM63xx DSL SoCs
 104           based on the MIPS architecture
 105
 106 +config CLK_BCM63268_TIMER
 107 +       bool "Broadcom BCM63268 timer clock and reset support"
 108 +       depends on BMIPS_GENERIC || COMPILE_TEST
 109 +       default BMIPS_GENERIC
 110 +       select RESET_CONTROLLER
 111 +       help
 112 +         Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs
 113 +         based on the MIPS architecture.
 114 +
 115  config CLK_BCM_KONA
 116         bool "Broadcom Kona CCU clock support"
 117         depends on ARCH_BCM_MOBILE || COMPILE_TEST
 118 --- a/drivers/clk/bcm/Makefile
 119 +++ b/drivers/clk/bcm/Makefile
 120 @@ -1,6 +1,7 @@
 121  # SPDX-License-Identifier: GPL-2.0
 122  obj-$(CONFIG_CLK_BCM_63XX)     += clk-bcm63xx.o
 123  obj-$(CONFIG_CLK_BCM_63XX_GATE)        += clk-bcm63xx-gate.o
 124 +obj-$(CONFIG_CLK_BCM63268_TIMER) += clk-bcm63268-timer.o
 125  obj-$(CONFIG_CLK_BCM_KONA)     += clk-kona.o
 126  obj-$(CONFIG_CLK_BCM_KONA)     += clk-kona-setup.o
 127  obj-$(CONFIG_CLK_BCM_KONA)     += clk-bcm281xx.o
 128 --- /dev/null
 129 +++ b/drivers/clk/bcm/clk-bcm63268-timer.c
 130 @@ -0,0 +1,215 @@
 131 +// SPDX-License-Identifier: GPL-2.0
 132 +/*
 133 + * BCM63268 Timer Clock and Reset Controller Driver
 134 + *
 135 + * Copyright (C) 2023 Álvaro Fernández Rojas <noltari@gmail.com>
 136 + */
 137 +
 138 +#include <linux/clk-provider.h>
 139 +#include <linux/delay.h>
 140 +#include <linux/io.h>
 141 +#include <linux/of.h>
 142 +#include <linux/of_device.h>
 143 +#include <linux/platform_device.h>
 144 +#include <linux/reset-controller.h>
 145 +
 146 +#include <dt-bindings/clock/bcm63268-clock.h>
 147 +
 148 +#define BCM63268_TIMER_RESET_SLEEP_MIN_US      10000
 149 +#define BCM63268_TIMER_RESET_SLEEP_MAX_US      20000
 150 +
 151 +struct bcm63268_tclkrst_hw {
 152 +       void __iomem *regs;
 153 +       spinlock_t lock;
 154 +
 155 +       struct reset_controller_dev rcdev;
 156 +       struct clk_hw_onecell_data data;
 157 +};
 158 +
 159 +struct bcm63268_tclk_table_entry {
 160 +       const char * const name;
 161 +       u8 bit;
 162 +};
 163 +
 164 +static const struct bcm63268_tclk_table_entry bcm63268_timer_clocks[] = {
 165 +       {
 166 +               .name = "ephy1",
 167 +               .bit = BCM63268_TCLK_EPHY1,
 168 +       }, {
 169 +               .name = "ephy2",
 170 +               .bit = BCM63268_TCLK_EPHY2,
 171 +       }, {
 172 +               .name = "ephy3",
 173 +               .bit = BCM63268_TCLK_EPHY3,
 174 +       }, {
 175 +               .name = "gphy1",
 176 +               .bit = BCM63268_TCLK_GPHY1,
 177 +       }, {
 178 +               .name = "dsl",
 179 +               .bit = BCM63268_TCLK_DSL,
 180 +       }, {
 181 +               .name = "wakeon_ephy",
 182 +               .bit = BCM63268_TCLK_WAKEON_EPHY,
 183 +       }, {
 184 +               .name = "wakeon_dsl",
 185 +               .bit = BCM63268_TCLK_WAKEON_DSL,
 186 +       }, {
 187 +               .name = "fap1_pll",
 188 +               .bit = BCM63268_TCLK_FAP1,
 189 +       }, {
 190 +               .name = "fap2_pll",
 191 +               .bit = BCM63268_TCLK_FAP2,
 192 +       }, {
 193 +               .name = "uto_50",
 194 +               .bit = BCM63268_TCLK_UTO_50,
 195 +       }, {
 196 +               .name = "uto_extin",
 197 +               .bit = BCM63268_TCLK_UTO_EXTIN,
 198 +       }, {
 199 +               .name = "usb_ref",
 200 +               .bit = BCM63268_TCLK_USB_REF,
 201 +       }, {
 202 +               /* sentinel */
 203 +       }
 204 +};
 205 +
 206 +static inline struct bcm63268_tclkrst_hw *
 207 +to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
 208 +{
 209 +       return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
 210 +}
 211 +
 212 +static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,
 213 +                               unsigned long id, bool assert)
 214 +{
 215 +       struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
 216 +       unsigned long flags;
 217 +       uint32_t val;
 218 +
 219 +       spin_lock_irqsave(&reset->lock, flags);
 220 +       val = __raw_readl(reset->regs);
 221 +       if (assert)
 222 +               val &= ~BIT(id);
 223 +       else
 224 +               val |= BIT(id);
 225 +       __raw_writel(val, reset->regs);
 226 +       spin_unlock_irqrestore(&reset->lock, flags);
 227 +
 228 +       return 0;
 229 +}
 230 +
 231 +static int bcm63268_timer_reset_assert(struct reset_controller_dev *rcdev,
 232 +                               unsigned long id)
 233 +{
 234 +       return bcm63268_timer_reset_update(rcdev, id, true);
 235 +}
 236 +
 237 +static int bcm63268_timer_reset_deassert(struct reset_controller_dev *rcdev,
 238 +                                 unsigned long id)
 239 +{
 240 +       return bcm63268_timer_reset_update(rcdev, id, false);
 241 +}
 242 +
 243 +static int bcm63268_timer_reset_reset(struct reset_controller_dev *rcdev,
 244 +                              unsigned long id)
 245 +{
 246 +       bcm63268_timer_reset_update(rcdev, id, true);
 247 +       usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,
 248 +                    BCM63268_TIMER_RESET_SLEEP_MAX_US);
 249 +
 250 +       bcm63268_timer_reset_update(rcdev, id, false);
 251 +       /*
 252 +        * Ensure component is taken out reset state by sleeping also after
 253 +        * deasserting the reset. Otherwise, the component may not be ready
 254 +        * for operation.
 255 +        */
 256 +       usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,
 257 +                    BCM63268_TIMER_RESET_SLEEP_MAX_US);
 258 +
 259 +       return 0;
 260 +}
 261 +
 262 +static int bcm63268_timer_reset_status(struct reset_controller_dev *rcdev,
 263 +                               unsigned long id)
 264 +{
 265 +       struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
 266 +
 267 +       return !(__raw_readl(reset->regs) & BIT(id));
 268 +}
 269 +
 270 +static struct reset_control_ops bcm63268_timer_reset_ops = {
 271 +       .assert = bcm63268_timer_reset_assert,
 272 +       .deassert = bcm63268_timer_reset_deassert,
 273 +       .reset = bcm63268_timer_reset_reset,
 274 +       .status = bcm63268_timer_reset_status,
 275 +};
 276 +
 277 +static int bcm63268_tclk_probe(struct platform_device *pdev)
 278 +{
 279 +       struct device *dev = &pdev->dev;
 280 +       const struct bcm63268_tclk_table_entry *entry;
 281 +       struct bcm63268_tclkrst_hw *hw;
 282 +       struct clk_hw *clk;
 283 +       u8 maxbit = 0;
 284 +       int i, ret;
 285 +
 286 +       for (entry = bcm63268_timer_clocks; entry->name; entry++)
 287 +               maxbit = max(maxbit, entry->bit);
 288 +       maxbit++;
 289 +
 290 +       hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),
 291 +                         GFP_KERNEL);
 292 +       if (!hw)
 293 +               return -ENOMEM;
 294 +
 295 +       platform_set_drvdata(pdev, hw);
 296 +
 297 +       spin_lock_init(&hw->lock);
 298 +
 299 +       hw->data.num = maxbit;
 300 +       for (i = 0; i < maxbit; i++)
 301 +               hw->data.hws[i] = ERR_PTR(-ENODEV);
 302 +
 303 +       hw->regs = devm_platform_ioremap_resource(pdev, 0);
 304 +       if (IS_ERR(hw->regs))
 305 +               return PTR_ERR(hw->regs);
 306 +
 307 +       for (entry = bcm63268_timer_clocks; entry->name; entry++) {
 308 +               clk = devm_clk_hw_register_gate(dev, entry->name, NULL, 0,
 309 +                                               hw->regs, entry->bit,
 310 +                                               CLK_GATE_BIG_ENDIAN,
 311 +                                               &hw->lock);
 312 +               if (IS_ERR(clk))
 313 +                       return PTR_ERR(clk);
 314 +
 315 +               hw->data.hws[entry->bit] = clk;
 316 +       }
 317 +
 318 +       ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
 319 +                                         &hw->data);
 320 +       if (ret)
 321 +               return ret;
 322 +
 323 +       hw->rcdev.of_node = dev->of_node;
 324 +       hw->rcdev.ops = &bcm63268_timer_reset_ops;
 325 +
 326 +       ret = devm_reset_controller_register(dev, &hw->rcdev);
 327 +       if (ret)
 328 +               dev_err(dev, "Failed to register reset controller\n");
 329 +
 330 +       return 0;
 331 +}
 332 +
 333 +static const struct of_device_id bcm63268_tclk_dt_ids[] = {
 334 +       { .compatible = "brcm,bcm63268-timer-clocks" },
 335 +       { /* sentinel */ }
 336 +};
 337 +
 338 +static struct platform_driver bcm63268_tclk = {
 339 +       .probe = bcm63268_tclk_probe,
 340 +       .driver = {
 341 +               .name = "bcm63268-timer-clock",
 342 +               .of_match_table = bcm63268_tclk_dt_ids,
 343 +       },
 344 +};
 345 +builtin_platform_driver(bcm63268_tclk);