target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch

   1 From 5f7c5e1c0d7a79be144e5efc1f24728ddd7fc25c Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Sat, 5 Nov 2022 20:02:56 +0100
   4 Subject: [PATCH 1/2] bus: mhi: core: add SBL state callback
   5
   6 Add support for SBL state callback in MHI core.
   7
   8 It is required for ath11k MHI devices in order to be able to set QRTR
   9 instance ID in the SBL state so that QRTR instance ID-s dont conflict in
  10 case of multiple PCI/MHI cards or AHB + PCI/MHI card.
  11 Setting QRTR instance ID is only possible in SBL state and there is
  12 currently no way to ensure that we are in that state, so provide a
  13 callback that the controller can trigger off.
  14
  15 Signed-off-by: Robert Marko <robimarko@gmail.com>
  16 ---
  17  drivers/bus/mhi/host/main.c | 1 +
  18  include/linux/mhi.h         | 2 ++
  19  2 files changed, 3 insertions(+)
  20
  21 --- a/drivers/bus/mhi/host/main.c
  22 +++ b/drivers/bus/mhi/host/main.c
  23 @@ -906,6 +906,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
  24                         switch (event) {
  25                         case MHI_EE_SBL:
  26                                 st = DEV_ST_TRANSITION_SBL;
  27 +                               mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_SBL_MODE);
  28                                 break;
  29                         case MHI_EE_WFW:
  30                         case MHI_EE_AMSS:
  31 --- a/include/linux/mhi.h
  32 +++ b/include/linux/mhi.h
  33 @@ -34,6 +34,7 @@ struct mhi_buf_info;
  34   * @MHI_CB_SYS_ERROR: MHI device entered error state (may recover)
  35   * @MHI_CB_FATAL_ERROR: MHI device entered fatal error state
  36   * @MHI_CB_BW_REQ: Received a bandwidth switch request from device
  37 + * @MHI_CB_EE_SBL_MODE: MHI device entered SBL mode
  38   */
  39  enum mhi_callback {
  40         MHI_CB_IDLE,
  41 @@ -45,6 +46,7 @@ enum mhi_callback {
  42         MHI_CB_SYS_ERROR,
  43         MHI_CB_FATAL_ERROR,
  44         MHI_CB_BW_REQ,
  45 +       MHI_CB_EE_SBL_MODE,
  46  };
  47
  48  /**