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[openwrt/openwrt.git] / target / linux / generic / pending-5.4 / 770-06-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch
1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Wed, 26 Aug 2020 17:02:30 +0200
3 Subject: [PATCH] net: ethernet: mtk_eth_soc: implement dynamic interrupt
4 moderation
5
6 Reduces the number of interrupts under load
7
8 Signed-off-by: Felix Fietkau <nbd@nbd.name>
9 ---
10
11 --- a/drivers/net/ethernet/mediatek/Kconfig
12 +++ b/drivers/net/ethernet/mediatek/Kconfig
13 @@ -10,6 +10,7 @@ if NET_VENDOR_MEDIATEK
14 config NET_MEDIATEK_SOC
15 tristate "MediaTek SoC Gigabit Ethernet support"
16 select PHYLINK
17 + select DIMLIB
18 ---help---
19 This driver supports the gigabit ethernet MACs in the
20 MediaTek SoC family.
21 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
22 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
23 @@ -1228,12 +1228,13 @@ static void mtk_update_rx_cpu_idx(struct
24 static int mtk_poll_rx(struct napi_struct *napi, int budget,
25 struct mtk_eth *eth)
26 {
27 + struct dim_sample dim_sample = {};
28 struct mtk_rx_ring *ring;
29 int idx;
30 struct sk_buff *skb;
31 u8 *data, *new_data;
32 struct mtk_rx_dma *rxd, trxd;
33 - int done = 0;
34 + int done = 0, bytes = 0;
35
36 while (done < budget) {
37 struct net_device *netdev;
38 @@ -1307,6 +1308,7 @@ static int mtk_poll_rx(struct napi_struc
39 else
40 skb_checksum_none_assert(skb);
41 skb->protocol = eth_type_trans(skb, netdev);
42 + bytes += pktlen;
43
44 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
45 (trxd.rxd2 & RX_DMA_VTAG))
46 @@ -1338,6 +1340,12 @@ rx_done:
47 mtk_update_rx_cpu_idx(eth);
48 }
49
50 + eth->rx_packets += done;
51 + eth->rx_bytes += bytes;
52 + dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,
53 + &dim_sample);
54 + net_dim(&eth->rx_dim, dim_sample);
55 +
56 return done;
57 }
58
59 @@ -1430,6 +1438,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
60 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
61 {
62 struct mtk_tx_ring *ring = &eth->tx_ring;
63 + struct dim_sample dim_sample = {};
64 unsigned int done[MTK_MAX_DEVS];
65 unsigned int bytes[MTK_MAX_DEVS];
66 int total = 0, i;
67 @@ -1447,8 +1456,14 @@ static int mtk_poll_tx(struct mtk_eth *e
68 continue;
69 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
70 total += done[i];
71 + eth->tx_packets += done[i];
72 + eth->tx_bytes += bytes[i];
73 }
74
75 + dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
76 + &dim_sample);
77 + net_dim(&eth->tx_dim, dim_sample);
78 +
79 if (mtk_queue_stopped(eth) &&
80 (atomic_read(&ring->free_count) > ring->thresh))
81 mtk_wake_queue(eth);
82 @@ -2123,6 +2138,7 @@ static irqreturn_t mtk_handle_irq_rx(int
83 {
84 struct mtk_eth *eth = _eth;
85
86 + eth->rx_events++;
87 if (likely(napi_schedule_prep(&eth->rx_napi))) {
88 __napi_schedule(&eth->rx_napi);
89 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
90 @@ -2135,6 +2151,7 @@ static irqreturn_t mtk_handle_irq_tx(int
91 {
92 struct mtk_eth *eth = _eth;
93
94 + eth->tx_events++;
95 if (likely(napi_schedule_prep(&eth->tx_napi))) {
96 __napi_schedule(&eth->tx_napi);
97 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
98 @@ -2311,6 +2328,9 @@ static int mtk_stop(struct net_device *d
99 napi_disable(&eth->tx_napi);
100 napi_disable(&eth->rx_napi);
101
102 + cancel_work_sync(&eth->rx_dim.work);
103 + cancel_work_sync(&eth->tx_dim.work);
104 +
105 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
106 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
107 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
108 @@ -2360,6 +2380,64 @@ err_disable_clks:
109 return ret;
110 }
111
112 +static void mtk_dim_rx(struct work_struct *work)
113 +{
114 + struct dim *dim = container_of(work, struct dim, work);
115 + struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
116 + struct dim_cq_moder cur_profile;
117 + u32 val, cur;
118 +
119 + cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,
120 + dim->profile_ix);
121 + spin_lock_bh(&eth->dim_lock);
122 +
123 + val = mtk_r32(eth, MTK_PDMA_DELAY_INT);
124 + val &= MTK_PDMA_DELAY_TX_MASK;
125 + val |= MTK_PDMA_DELAY_RX_EN;
126 +
127 + cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
128 + val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;
129 +
130 + cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
131 + val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
132 +
133 + mtk_w32(eth, val, MTK_PDMA_DELAY_INT);
134 + mtk_w32(eth, val, MTK_QDMA_DELAY_INT);
135 +
136 + spin_unlock_bh(&eth->dim_lock);
137 +
138 + dim->state = DIM_START_MEASURE;
139 +}
140 +
141 +static void mtk_dim_tx(struct work_struct *work)
142 +{
143 + struct dim *dim = container_of(work, struct dim, work);
144 + struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
145 + struct dim_cq_moder cur_profile;
146 + u32 val, cur;
147 +
148 + cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,
149 + dim->profile_ix);
150 + spin_lock_bh(&eth->dim_lock);
151 +
152 + val = mtk_r32(eth, MTK_PDMA_DELAY_INT);
153 + val &= MTK_PDMA_DELAY_RX_MASK;
154 + val |= MTK_PDMA_DELAY_TX_EN;
155 +
156 + cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
157 + val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;
158 +
159 + cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
160 + val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
161 +
162 + mtk_w32(eth, val, MTK_PDMA_DELAY_INT);
163 + mtk_w32(eth, val, MTK_QDMA_DELAY_INT);
164 +
165 + spin_unlock_bh(&eth->dim_lock);
166 +
167 + dim->state = DIM_START_MEASURE;
168 +}
169 +
170 static int mtk_hw_init(struct mtk_eth *eth)
171 {
172 int i, val, ret;
173 @@ -2381,9 +2459,6 @@ static int mtk_hw_init(struct mtk_eth *e
174 goto err_disable_pm;
175 }
176
177 - /* enable interrupt delay for RX */
178 - mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
179 -
180 /* disable delay and normal interrupt */
181 mtk_tx_irq_disable(eth, ~0);
182 mtk_rx_irq_disable(eth, ~0);
183 @@ -2422,11 +2497,10 @@ static int mtk_hw_init(struct mtk_eth *e
184 /* Enable RX VLan Offloading */
185 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
186
187 - /* enable interrupt delay for RX */
188 - mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
189 + mtk_dim_rx(&eth->rx_dim.work);
190 + mtk_dim_tx(&eth->tx_dim.work);
191
192 /* disable delay and normal interrupt */
193 - mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
194 mtk_tx_irq_disable(eth, ~0);
195 mtk_rx_irq_disable(eth, ~0);
196
197 @@ -2930,6 +3004,13 @@ static int mtk_probe(struct platform_dev
198 spin_lock_init(&eth->page_lock);
199 spin_lock_init(&eth->tx_irq_lock);
200 spin_lock_init(&eth->rx_irq_lock);
201 + spin_lock_init(&eth->dim_lock);
202 +
203 + eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
204 + INIT_WORK(&eth->rx_dim.work, mtk_dim_rx);
205 +
206 + eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
207 + INIT_WORK(&eth->tx_dim.work, mtk_dim_tx);
208
209 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
210 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
211 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
212 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
213 @@ -15,6 +15,7 @@
214 #include <linux/u64_stats_sync.h>
215 #include <linux/refcount.h>
216 #include <linux/phylink.h>
217 +#include <linux/dim.h>
218
219 #define MTK_QDMA_PAGE_SIZE 2048
220 #define MTK_MAX_RX_LENGTH 1536
221 @@ -131,13 +132,18 @@
222
223 /* PDMA Delay Interrupt Register */
224 #define MTK_PDMA_DELAY_INT 0xa0c
225 +#define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
226 #define MTK_PDMA_DELAY_RX_EN BIT(15)
227 -#define MTK_PDMA_DELAY_RX_PINT 4
228 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
229 -#define MTK_PDMA_DELAY_RX_PTIME 4
230 -#define MTK_PDMA_DELAY_RX_DELAY \
231 - (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \
232 - (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT))
233 +#define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0
234 +
235 +#define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16)
236 +#define MTK_PDMA_DELAY_TX_EN BIT(31)
237 +#define MTK_PDMA_DELAY_TX_PINT_SHIFT 24
238 +#define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16
239 +
240 +#define MTK_PDMA_DELAY_PINT_MASK 0x7f
241 +#define MTK_PDMA_DELAY_PTIME_MASK 0xff
242
243 /* PDMA Interrupt Status Register */
244 #define MTK_PDMA_INT_STATUS 0xa20
245 @@ -219,6 +225,7 @@
246 /* QDMA Interrupt Status Register */
247 #define MTK_QDMA_INT_STATUS 0x1A18
248 #define MTK_RX_DONE_DLY BIT(30)
249 +#define MTK_TX_DONE_DLY BIT(28)
250 #define MTK_RX_DONE_INT3 BIT(19)
251 #define MTK_RX_DONE_INT2 BIT(18)
252 #define MTK_RX_DONE_INT1 BIT(17)
253 @@ -228,8 +235,7 @@
254 #define MTK_TX_DONE_INT1 BIT(1)
255 #define MTK_TX_DONE_INT0 BIT(0)
256 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY
257 -#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
258 - MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
259 +#define MTK_TX_DONE_INT MTK_TX_DONE_DLY
260
261 /* QDMA Interrupt grouping registers */
262 #define MTK_QDMA_INT_GRP1 0x1a20
263 @@ -892,6 +898,18 @@ struct mtk_eth {
264
265 const struct mtk_soc_data *soc;
266
267 + spinlock_t dim_lock;
268 +
269 + u32 rx_events;
270 + u32 rx_packets;
271 + u32 rx_bytes;
272 + struct dim rx_dim;
273 +
274 + u32 tx_events;
275 + u32 tx_packets;
276 + u32 tx_bytes;
277 + struct dim tx_dim;
278 +
279 u32 tx_int_mask_reg;
280 u32 tx_int_status_reg;
281 u32 rx_dma_l4_valid;
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