kernel: bump 5.10 to 5.10.147
[openwrt/openwrt.git] / target / linux / generic / pending-5.15 / 722-net-mt7531-only-do-PLL-once-after-the-reset.patch
1 From 9fec662b54fc956b776df15c704e996c61292850 Mon Sep 17 00:00:00 2001
2 From: Alexander Couzens <lynxis@fe80.eu>
3 Date: Sat, 13 Aug 2022 13:05:09 +0200
4 Subject: [PATCH 02/10] net: mt7531: only do PLL once after the reset
5
6 Move the PLL init of the switch out of the pad configuration of the port
7 6 (usally cpu port).
8
9 Fix a unidirectional 100 mbit limitation on 1 gbit or 2.5 gbit links for
10 outbound traffic on port 5 or port 6.
11
12 Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
13 ---
14 drivers/net/dsa/mt7530.c | 15 +++++++++------
15 1 file changed, 9 insertions(+), 6 deletions(-)
16
17 --- a/drivers/net/dsa/mt7530.c
18 +++ b/drivers/net/dsa/mt7530.c
19 @@ -506,14 +506,19 @@ static bool mt7531_dual_sgmii_supported(
20 static int
21 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
22 {
23 - struct mt7530_priv *priv = ds->priv;
24 + return 0;
25 +}
26 +
27 +static void
28 +mt7531_pll_setup(struct mt7530_priv *priv)
29 +{
30 u32 top_sig;
31 u32 hwstrap;
32 u32 xtal;
33 u32 val;
34
35 if (mt7531_dual_sgmii_supported(priv))
36 - return 0;
37 + return;
38
39 val = mt7530_read(priv, MT7531_CREV);
40 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
41 @@ -592,8 +597,6 @@ mt7531_pad_setup(struct dsa_switch *ds,
42 val |= EN_COREPLL;
43 mt7530_write(priv, MT7531_PLLGP_EN, val);
44 usleep_range(25, 35);
45 -
46 - return 0;
47 }
48
49 static void
50 @@ -2326,6 +2329,8 @@ mt7531_setup(struct dsa_switch *ds)
51 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
52 SYS_CTRL_REG_RST);
53
54 + mt7531_pll_setup(priv);
55 +
56 if (mt7531_dual_sgmii_supported(priv)) {
57 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
58
59 @@ -2882,8 +2887,6 @@ mt7531_cpu_port_config(struct dsa_switch
60 case 6:
61 interface = PHY_INTERFACE_MODE_2500BASEX;
62
63 - mt7531_pad_setup(ds, interface);
64 -
65 priv->p6_interface = interface;
66 break;
67 default: