target/linux/generic/pending-5.15/301-MIPS-Add-barriers-between-dcache-icache-flushes.patch

   1 From e6e6ef4275978823ec3a84133fc91f4ffbef5c84 Mon Sep 17 00:00:00 2001
   2 From: Paul Burton <paul.burton@imgtec.com>
   3 Date: Mon, 22 Feb 2016 18:09:44 +0000
   4 Subject: [PATCH] MIPS: Add barriers between dcache & icache flushes
   5
   6 Index-based cache operations may be arbitrarily reordered by out of
   7 order CPUs. Thus code which writes back the dcache & then invalidates
   8 the icache using indexed cache ops must include a barrier between
   9 operating on the 2 caches in order to prevent the scenario in which:
  10
  11   - icache invalidation occurs.
  12
  13   - icache fetch occurs, due to speculation.
  14
  15   - dcache writeback occurs.
  16
  17 If the above were allowed to happen then the icache would contain stale
  18 data. Forcing the dcache writeback to complete before the icache
  19 invalidation avoids this.
  20
  21 Signed-off-by: Paul Burton <paul.burton@imgtec.com>
  22 Cc: James Hogan <james.hogan@imgtec.com>
  23 ---
  24  arch/mips/mm/c-r4k.c | 13 +++++++++++--
  25  1 file changed, 11 insertions(+), 2 deletions(-)
  26
  27 --- a/arch/mips/mm/c-r4k.c
  28 +++ b/arch/mips/mm/c-r4k.c
  29 @@ -515,6 +515,7 @@ static inline void local_r4k___flush_cac
  30
  31         default:
  32                 r4k_blast_dcache();
  33 +               mb(); /* cache instructions may be reordered */
  34                 r4k_blast_icache();
  35                 break;
  36         }
  37 @@ -595,8 +596,10 @@ static inline void local_r4k_flush_cache
  38         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
  39                 r4k_blast_dcache();
  40         /* If executable, blast stale lines from icache */
  41 -       if (exec)
  42 +       if (exec) {
  43 +               mb(); /* cache instructions may be reordered */
  44                 r4k_blast_icache();
  45 +       }
  46  }
  47
  48  static void r4k_flush_cache_range(struct vm_area_struct *vma,
  49 @@ -697,8 +700,13 @@ static inline void local_r4k_flush_cache
  50         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
  51                 vaddr ? r4k_blast_dcache_page(addr) :
  52                         r4k_blast_dcache_user_page(addr);
  53 -               if (exec && !cpu_icache_snoops_remote_store)
  54 +               if (exec)
  55 +                       mb(); /* cache instructions may be reordered */
  56 +
  57 +               if (exec && !cpu_icache_snoops_remote_store) {
  58                         r4k_blast_scache_page(addr);
  59 +                       mb(); /* cache instructions may be reordered */
  60 +               }
  61         }
  62         if (exec) {
  63                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
  64 @@ -765,6 +773,7 @@ static inline void __local_r4k_flush_ica
  65                         else
  66                                 blast_dcache_range(start, end);
  67                 }
  68 +               mb(); /* cache instructions may be reordered */
  69         }
  70
  71         if (type == R4K_INDEX ||