target/linux/generic/pending-5.10/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch

   1 From 245224608b5368c10407da07557e546743d3c489 Mon Sep 17 00:00:00 2001
   2 From: Nick Hainke <vincent@systemli.org>
   3 Date: Mon, 27 Dec 2021 09:33:13 +0100
   4 Subject: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
   5
   6 Macronix flash chips seem to consist of only one status register.
   7 These chips will not work with the "16-bit Write Status (01h) Command".
   8 Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
   9
  10 Tested with MX25L6405D.
  11
  12 Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
  13 lock()/unlock()")
  14
  15 Signed-off-by: David Bauer <mail@david-bauer.net>
  16 Signed-off-by: Nick Hainke <vincent@systemli.org>
  17 ---
  18  drivers/mtd/spi-nor/macronix.c | 1 +
  19  1 file changed, 1 insertion(+)
  20
  21 --- a/drivers/mtd/spi-nor/macronix.c
  22 +++ b/drivers/mtd/spi-nor/macronix.c
  23 @@ -94,6 +94,7 @@ static void macronix_default_init(struct
  24  {
  25         nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
  26         nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
  27 +       nor->flags &= ~SNOR_F_HAS_16BIT_SR;
  28         nor->flags |= SNOR_F_HAS_LOCK;
  29  }
  30