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c50ef88d9a1980d8d672b785ba653da84c7365d7
[openwrt/openwrt.git] / target / linux / generic / patches-4.3 / 090-m25p80_spi-nor_update_to_4.4rc1.patch
1 --- a/drivers/mtd/devices/m25p80.c
2 +++ b/drivers/mtd/devices/m25p80.c
3 @@ -31,7 +31,6 @@
4 struct m25p {
5 struct spi_device *spi;
6 struct spi_nor spi_nor;
7 - struct mtd_info mtd;
8 u8 command[MAX_CMD_SIZE];
9 };
10
11 @@ -62,8 +61,7 @@ static int m25p_cmdsz(struct spi_nor *no
12 return 1 + nor->addr_width;
13 }
14
15 -static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
16 - int wr_en)
17 +static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
18 {
19 struct m25p *flash = nor->priv;
20 struct spi_device *spi = flash->spi;
21 @@ -159,7 +157,7 @@ static int m25p80_erase(struct spi_nor *
22 struct m25p *flash = nor->priv;
23
24 dev_dbg(nor->dev, "%dKiB at 0x%08x\n",
25 - flash->mtd.erasesize / 1024, (u32)offset);
26 + flash->spi_nor.mtd.erasesize / 1024, (u32)offset);
27
28 /* Set up command buffer. */
29 flash->command[0] = nor->erase_opcode;
30 @@ -201,11 +199,10 @@ static int m25p_probe(struct spi_device
31 nor->read_reg = m25p80_read_reg;
32
33 nor->dev = &spi->dev;
34 - nor->mtd = &flash->mtd;
35 + nor->flash_node = spi->dev.of_node;
36 nor->priv = flash;
37
38 spi_set_drvdata(spi, flash);
39 - flash->mtd.priv = nor;
40 flash->spi = spi;
41
42 if (spi->mode & SPI_RX_QUAD)
43 @@ -214,7 +211,7 @@ static int m25p_probe(struct spi_device
44 mode = SPI_NOR_DUAL;
45
46 if (data && data->name)
47 - flash->mtd.name = data->name;
48 + nor->mtd.name = data->name;
49
50 /* For some (historical?) reason many platforms provide two different
51 * names in flash_platform_data: "name" and "type". Quite often name is
52 @@ -232,7 +229,7 @@ static int m25p_probe(struct spi_device
53
54 ppdata.of_node = spi->dev.of_node;
55
56 - return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
57 + return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
58 data ? data->parts : NULL,
59 data ? data->nr_parts : 0);
60 }
61 @@ -243,7 +240,7 @@ static int m25p_remove(struct spi_device
62 struct m25p *flash = spi_get_drvdata(spi);
63
64 /* Clean up MTD stuff. */
65 - return mtd_device_unregister(&flash->mtd);
66 + return mtd_device_unregister(&flash->spi_nor.mtd);
67 }
68
69 /*
70 @@ -304,7 +301,6 @@ MODULE_DEVICE_TABLE(of, m25p_of_table);
71 static struct spi_driver m25p80_driver = {
72 .driver = {
73 .name = "m25p80",
74 - .owner = THIS_MODULE,
75 .of_match_table = m25p_of_table,
76 },
77 .id_table = m25p_ids,
78 --- a/drivers/mtd/spi-nor/spi-nor.c
79 +++ b/drivers/mtd/spi-nor/spi-nor.c
80 @@ -16,15 +16,26 @@
81 #include <linux/device.h>
82 #include <linux/mutex.h>
83 #include <linux/math64.h>
84 +#include <linux/sizes.h>
85
86 -#include <linux/mtd/cfi.h>
87 #include <linux/mtd/mtd.h>
88 #include <linux/of_platform.h>
89 #include <linux/spi/flash.h>
90 #include <linux/mtd/spi-nor.h>
91
92 /* Define max times to check status register before we give up. */
93 -#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
94 +
95 +/*
96 + * For everything but full-chip erase; probably could be much smaller, but kept
97 + * around for safety for now
98 + */
99 +#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
100 +
101 +/*
102 + * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
103 + * for larger flash
104 + */
105 +#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
106
107 #define SPI_NOR_MAX_ID_LEN 6
108
109 @@ -145,7 +156,7 @@ static inline int spi_nor_read_dummy_cyc
110 static inline int write_sr(struct spi_nor *nor, u8 val)
111 {
112 nor->cmd_buf[0] = val;
113 - return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
114 + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
115 }
116
117 /*
118 @@ -154,7 +165,7 @@ static inline int write_sr(struct spi_no
119 */
120 static inline int write_enable(struct spi_nor *nor)
121 {
122 - return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
123 + return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
124 }
125
126 /*
127 @@ -162,7 +173,7 @@ static inline int write_enable(struct sp
128 */
129 static inline int write_disable(struct spi_nor *nor)
130 {
131 - return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
132 + return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
133 }
134
135 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
136 @@ -179,16 +190,16 @@ static inline int set_4byte(struct spi_n
137 u8 cmd;
138
139 switch (JEDEC_MFR(info)) {
140 - case CFI_MFR_ST: /* Micron, actually */
141 + case SNOR_MFR_MICRON:
142 /* Some Micron need WREN command; all will accept it */
143 need_wren = true;
144 - case CFI_MFR_MACRONIX:
145 - case 0xEF /* winbond */:
146 + case SNOR_MFR_MACRONIX:
147 + case SNOR_MFR_WINBOND:
148 if (need_wren)
149 write_enable(nor);
150
151 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
152 - status = nor->write_reg(nor, cmd, NULL, 0, 0);
153 + status = nor->write_reg(nor, cmd, NULL, 0);
154 if (need_wren)
155 write_disable(nor);
156
157 @@ -196,7 +207,7 @@ static inline int set_4byte(struct spi_n
158 default:
159 /* Spansion style */
160 nor->cmd_buf[0] = enable << 7;
161 - return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
162 + return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
163 }
164 }
165 static inline int spi_nor_sr_ready(struct spi_nor *nor)
166 @@ -233,12 +244,13 @@ static int spi_nor_ready(struct spi_nor
167 * Service routine to read status register until ready, or timeout occurs.
168 * Returns non-zero if error.
169 */
170 -static int spi_nor_wait_till_ready(struct spi_nor *nor)
171 +static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
172 + unsigned long timeout_jiffies)
173 {
174 unsigned long deadline;
175 int timeout = 0, ret;
176
177 - deadline = jiffies + MAX_READY_WAIT_JIFFIES;
178 + deadline = jiffies + timeout_jiffies;
179
180 while (!timeout) {
181 if (time_after_eq(jiffies, deadline))
182 @@ -258,6 +270,12 @@ static int spi_nor_wait_till_ready(struc
183 return -ETIMEDOUT;
184 }
185
186 +static int spi_nor_wait_till_ready(struct spi_nor *nor)
187 +{
188 + return spi_nor_wait_till_ready_with_timeout(nor,
189 + DEFAULT_READY_WAIT_JIFFIES);
190 +}
191 +
192 /*
193 * Erase the whole flash memory
194 *
195 @@ -265,9 +283,9 @@ static int spi_nor_wait_till_ready(struc
196 */
197 static int erase_chip(struct spi_nor *nor)
198 {
199 - dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
200 + dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
201
202 - return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
203 + return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
204 }
205
206 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
207 @@ -321,6 +339,8 @@ static int spi_nor_erase(struct mtd_info
208
209 /* whole-chip erase? */
210 if (len == mtd->size) {
211 + unsigned long timeout;
212 +
213 write_enable(nor);
214
215 if (erase_chip(nor)) {
216 @@ -328,7 +348,16 @@ static int spi_nor_erase(struct mtd_info
217 goto erase_err;
218 }
219
220 - ret = spi_nor_wait_till_ready(nor);
221 + /*
222 + * Scale the timeout linearly with the size of the flash, with
223 + * a minimum calibrated to an old 2MB flash. We could try to
224 + * pull these from CFI/SFDP, but these values should be good
225 + * enough for now.
226 + */
227 + timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
228 + CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
229 + (unsigned long)(mtd->size / SZ_2M));
230 + ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
231 if (ret)
232 goto erase_err;
233
234 @@ -371,72 +400,171 @@ erase_err:
235 return ret;
236 }
237
238 +static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
239 + uint64_t *len)
240 +{
241 + struct mtd_info *mtd = &nor->mtd;
242 + u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
243 + int shift = ffs(mask) - 1;
244 + int pow;
245 +
246 + if (!(sr & mask)) {
247 + /* No protection */
248 + *ofs = 0;
249 + *len = 0;
250 + } else {
251 + pow = ((sr & mask) ^ mask) >> shift;
252 + *len = mtd->size >> pow;
253 + *ofs = mtd->size - *len;
254 + }
255 +}
256 +
257 +/*
258 + * Return 1 if the entire region is locked, 0 otherwise
259 + */
260 +static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
261 + u8 sr)
262 +{
263 + loff_t lock_offs;
264 + uint64_t lock_len;
265 +
266 + stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
267 +
268 + return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
269 +}
270 +
271 +/*
272 + * Lock a region of the flash. Compatible with ST Micro and similar flash.
273 + * Supports only the block protection bits BP{0,1,2} in the status register
274 + * (SR). Does not support these features found in newer SR bitfields:
275 + * - TB: top/bottom protect - only handle TB=0 (top protect)
276 + * - SEC: sector/block protect - only handle SEC=0 (block protect)
277 + * - CMP: complement protect - only support CMP=0 (range is not complemented)
278 + *
279 + * Sample table portion for 8MB flash (Winbond w25q64fw):
280 + *
281 + * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
282 + * --------------------------------------------------------------------------
283 + * X | X | 0 | 0 | 0 | NONE | NONE
284 + * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
285 + * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
286 + * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
287 + * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
288 + * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
289 + * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
290 + * X | X | 1 | 1 | 1 | 8 MB | ALL
291 + *
292 + * Returns negative on errors, 0 on success.
293 + */
294 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
295 {
296 - struct mtd_info *mtd = nor->mtd;
297 - uint32_t offset = ofs;
298 - uint8_t status_old, status_new;
299 - int ret = 0;
300 + struct mtd_info *mtd = &nor->mtd;
301 + u8 status_old, status_new;
302 + u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
303 + u8 shift = ffs(mask) - 1, pow, val;
304
305 status_old = read_sr(nor);
306
307 - if (offset < mtd->size - (mtd->size / 2))
308 - status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
309 - else if (offset < mtd->size - (mtd->size / 4))
310 - status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
311 - else if (offset < mtd->size - (mtd->size / 8))
312 - status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
313 - else if (offset < mtd->size - (mtd->size / 16))
314 - status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
315 - else if (offset < mtd->size - (mtd->size / 32))
316 - status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
317 - else if (offset < mtd->size - (mtd->size / 64))
318 - status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
319 - else
320 - status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
321 + /* SPI NOR always locks to the end */
322 + if (ofs + len != mtd->size) {
323 + /* Does combined region extend to end? */
324 + if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len,
325 + status_old))
326 + return -EINVAL;
327 + len = mtd->size - ofs;
328 + }
329 +
330 + /*
331 + * Need smallest pow such that:
332 + *
333 + * 1 / (2^pow) <= (len / size)
334 + *
335 + * so (assuming power-of-2 size) we do:
336 + *
337 + * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
338 + */
339 + pow = ilog2(mtd->size) - ilog2(len);
340 + val = mask - (pow << shift);
341 + if (val & ~mask)
342 + return -EINVAL;
343 + /* Don't "lock" with no region! */
344 + if (!(val & mask))
345 + return -EINVAL;
346 +
347 + status_new = (status_old & ~mask) | val;
348
349 /* Only modify protection if it will not unlock other areas */
350 - if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
351 - (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
352 - write_enable(nor);
353 - ret = write_sr(nor, status_new);
354 - }
355 + if ((status_new & mask) <= (status_old & mask))
356 + return -EINVAL;
357
358 - return ret;
359 + write_enable(nor);
360 + return write_sr(nor, status_new);
361 }
362
363 +/*
364 + * Unlock a region of the flash. See stm_lock() for more info
365 + *
366 + * Returns negative on errors, 0 on success.
367 + */
368 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
369 {
370 - struct mtd_info *mtd = nor->mtd;
371 - uint32_t offset = ofs;
372 + struct mtd_info *mtd = &nor->mtd;
373 uint8_t status_old, status_new;
374 - int ret = 0;
375 + u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
376 + u8 shift = ffs(mask) - 1, pow, val;
377
378 status_old = read_sr(nor);
379
380 - if (offset+len > mtd->size - (mtd->size / 64))
381 - status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
382 - else if (offset+len > mtd->size - (mtd->size / 32))
383 - status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
384 - else if (offset+len > mtd->size - (mtd->size / 16))
385 - status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
386 - else if (offset+len > mtd->size - (mtd->size / 8))
387 - status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
388 - else if (offset+len > mtd->size - (mtd->size / 4))
389 - status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
390 - else if (offset+len > mtd->size - (mtd->size / 2))
391 - status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
392 - else
393 - status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
394 + /* Cannot unlock; would unlock larger region than requested */
395 + if (stm_is_locked_sr(nor, status_old, ofs - mtd->erasesize,
396 + mtd->erasesize))
397 + return -EINVAL;
398
399 - /* Only modify protection if it will not lock other areas */
400 - if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
401 - (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
402 - write_enable(nor);
403 - ret = write_sr(nor, status_new);
404 + /*
405 + * Need largest pow such that:
406 + *
407 + * 1 / (2^pow) >= (len / size)
408 + *
409 + * so (assuming power-of-2 size) we do:
410 + *
411 + * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
412 + */
413 + pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len));
414 + if (ofs + len == mtd->size) {
415 + val = 0; /* fully unlocked */
416 + } else {
417 + val = mask - (pow << shift);
418 + /* Some power-of-two sizes are not supported */
419 + if (val & ~mask)
420 + return -EINVAL;
421 }
422
423 - return ret;
424 + status_new = (status_old & ~mask) | val;
425 +
426 + /* Only modify protection if it will not lock other areas */
427 + if ((status_new & mask) >= (status_old & mask))
428 + return -EINVAL;
429 +
430 + write_enable(nor);
431 + return write_sr(nor, status_new);
432 +}
433 +
434 +/*
435 + * Check if a region of the flash is (completely) locked. See stm_lock() for
436 + * more info.
437 + *
438 + * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
439 + * negative on errors.
440 + */
441 +static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
442 +{
443 + int status;
444 +
445 + status = read_sr(nor);
446 + if (status < 0)
447 + return status;
448 +
449 + return stm_is_locked_sr(nor, ofs, len, status);
450 }
451
452 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
453 @@ -469,6 +597,21 @@ static int spi_nor_unlock(struct mtd_inf
454 return ret;
455 }
456
457 +static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
458 +{
459 + struct spi_nor *nor = mtd_to_spi_nor(mtd);
460 + int ret;
461 +
462 + ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
463 + if (ret)
464 + return ret;
465 +
466 + ret = nor->flash_is_locked(nor, ofs, len);
467 +
468 + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
469 + return ret;
470 +}
471 +
472 /* Used when the "_ext_id" is two bytes at most */
473 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
474 .id = { \
475 @@ -585,6 +728,7 @@ static const struct flash_info spi_nor_i
476
477 /* Micron */
478 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
479 + { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
480 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
481 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
482 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
483 @@ -618,12 +762,13 @@ static const struct flash_info spi_nor_i
484 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
485 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
486 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
487 - { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
488 - { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
489 + { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
490 + { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
491 + { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
492 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
493 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
494 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
495 - { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K) },
496 + { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
497
498 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
499 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
500 @@ -635,6 +780,7 @@ static const struct flash_info spi_nor_i
501 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
502 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
503 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
504 + { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
505 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
506 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
507
508 @@ -683,10 +829,11 @@ static const struct flash_info spi_nor_i
509 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
510 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
511 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
512 - { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
513 + { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
514 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
515 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
516 - { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K) },
517 + { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
518 + { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
519 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
520 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
521 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
522 @@ -868,8 +1015,7 @@ static int macronix_quad_enable(struct s
523 val = read_sr(nor);
524 write_enable(nor);
525
526 - nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
527 - nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
528 + write_sr(nor, val | SR_QUAD_EN_MX);
529
530 if (spi_nor_wait_till_ready(nor))
531 return 1;
532 @@ -894,7 +1040,7 @@ static int write_sr_cr(struct spi_nor *n
533 nor->cmd_buf[0] = val & 0xff;
534 nor->cmd_buf[1] = (val >> 8);
535
536 - return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
537 + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
538 }
539
540 static int spansion_quad_enable(struct spi_nor *nor)
541 @@ -936,7 +1082,7 @@ static int micron_quad_enable(struct spi
542
543 /* set EVCR, enable quad I/O */
544 nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
545 - ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
546 + ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
547 if (ret < 0) {
548 dev_err(nor->dev, "error while writing EVCR register\n");
549 return ret;
550 @@ -965,14 +1111,14 @@ static int set_quad_mode(struct spi_nor
551 int status;
552
553 switch (JEDEC_MFR(info)) {
554 - case CFI_MFR_MACRONIX:
555 + case SNOR_MFR_MACRONIX:
556 status = macronix_quad_enable(nor);
557 if (status) {
558 dev_err(nor->dev, "Macronix quad-read not enabled\n");
559 return -EINVAL;
560 }
561 return status;
562 - case CFI_MFR_ST:
563 + case SNOR_MFR_MICRON:
564 status = micron_quad_enable(nor);
565 if (status) {
566 dev_err(nor->dev, "Micron quad-read not enabled\n");
567 @@ -1004,8 +1150,8 @@ int spi_nor_scan(struct spi_nor *nor, co
568 {
569 const struct flash_info *info = NULL;
570 struct device *dev = nor->dev;
571 - struct mtd_info *mtd = nor->mtd;
572 - struct device_node *np = dev->of_node;
573 + struct mtd_info *mtd = &nor->mtd;
574 + struct device_node *np = nor->flash_node;
575 int ret;
576 int i;
577
578 @@ -1048,19 +1194,21 @@ int spi_nor_scan(struct spi_nor *nor, co
579 mutex_init(&nor->lock);
580
581 /*
582 - * Atmel, SST and Intel/Numonyx serial nor tend to power
583 - * up with the software protection bits set
584 + * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
585 + * with the software protection bits set
586 */
587
588 - if (JEDEC_MFR(info) == CFI_MFR_ATMEL ||
589 - JEDEC_MFR(info) == CFI_MFR_INTEL ||
590 - JEDEC_MFR(info) == CFI_MFR_SST) {
591 + if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
592 + JEDEC_MFR(info) == SNOR_MFR_INTEL ||
593 + JEDEC_MFR(info) == SNOR_MFR_SST ||
594 + JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
595 write_enable(nor);
596 write_sr(nor, 0);
597 }
598
599 if (!mtd->name)
600 mtd->name = dev_name(dev);
601 + mtd->priv = nor;
602 mtd->type = MTD_NORFLASH;
603 mtd->writesize = 1;
604 mtd->flags = MTD_CAP_NORFLASH;
605 @@ -1068,15 +1216,18 @@ int spi_nor_scan(struct spi_nor *nor, co
606 mtd->_erase = spi_nor_erase;
607 mtd->_read = spi_nor_read;
608
609 - /* nor protection support for STmicro chips */
610 - if (JEDEC_MFR(info) == CFI_MFR_ST) {
611 + /* NOR protection support for STmicro/Micron chips and similar */
612 + if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
613 + JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
614 nor->flash_lock = stm_lock;
615 nor->flash_unlock = stm_unlock;
616 + nor->flash_is_locked = stm_is_locked;
617 }
618
619 - if (nor->flash_lock && nor->flash_unlock) {
620 + if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
621 mtd->_lock = spi_nor_lock;
622 mtd->_unlock = spi_nor_unlock;
623 + mtd->_is_locked = spi_nor_is_locked;
624 }
625
626 /* sst nor chips use AAI word program */
627 @@ -1163,7 +1314,7 @@ int spi_nor_scan(struct spi_nor *nor, co
628 else if (mtd->size > 0x1000000) {
629 /* enable 4-byte addressing if the device exceeds 16MiB */
630 nor->addr_width = 4;
631 - if (JEDEC_MFR(info) == CFI_MFR_AMD) {
632 + if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
633 /* Dedicated 4-byte command set */
634 switch (nor->flash_read) {
635 case SPI_NOR_QUAD:
636 --- a/include/linux/mtd/spi-nor.h
637 +++ b/include/linux/mtd/spi-nor.h
638 @@ -10,6 +10,23 @@
639 #ifndef __LINUX_MTD_SPI_NOR_H
640 #define __LINUX_MTD_SPI_NOR_H
641
642 +#include <linux/bitops.h>
643 +#include <linux/mtd/cfi.h>
644 +
645 +/*
646 + * Manufacturer IDs
647 + *
648 + * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
649 + * Sometimes these are the same as CFI IDs, but sometimes they aren't.
650 + */
651 +#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
652 +#define SNOR_MFR_INTEL CFI_MFR_INTEL
653 +#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
654 +#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
655 +#define SNOR_MFR_SPANSION CFI_MFR_AMD
656 +#define SNOR_MFR_SST CFI_MFR_SST
657 +#define SNOR_MFR_WINBOND 0xef
658 +
659 /*
660 * Note on opcode nomenclature: some opcodes have a format like
661 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
662 @@ -61,24 +78,24 @@
663 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
664
665 /* Status Register bits. */
666 -#define SR_WIP 1 /* Write in progress */
667 -#define SR_WEL 2 /* Write enable latch */
668 +#define SR_WIP BIT(0) /* Write in progress */
669 +#define SR_WEL BIT(1) /* Write enable latch */
670 /* meaning of other SR_* bits may differ between vendors */
671 -#define SR_BP0 4 /* Block protect 0 */
672 -#define SR_BP1 8 /* Block protect 1 */
673 -#define SR_BP2 0x10 /* Block protect 2 */
674 -#define SR_SRWD 0x80 /* SR write protect */
675 +#define SR_BP0 BIT(2) /* Block protect 0 */
676 +#define SR_BP1 BIT(3) /* Block protect 1 */
677 +#define SR_BP2 BIT(4) /* Block protect 2 */
678 +#define SR_SRWD BIT(7) /* SR write protect */
679
680 -#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
681 +#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
682
683 /* Enhanced Volatile Configuration Register bits */
684 -#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */
685 +#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
686
687 /* Flag Status Register bits */
688 -#define FSR_READY 0x80
689 +#define FSR_READY BIT(7)
690
691 /* Configuration Register bits. */
692 -#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
693 +#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
694
695 enum read_mode {
696 SPI_NOR_NORMAL = 0,
697 @@ -87,33 +104,6 @@ enum read_mode {
698 SPI_NOR_QUAD,
699 };
700
701 -/**
702 - * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
703 - * @wren: command for "Write Enable", or 0x00 for not required
704 - * @cmd: command for operation
705 - * @cmd_pins: number of pins to send @cmd (1, 2, 4)
706 - * @addr: address for operation
707 - * @addr_pins: number of pins to send @addr (1, 2, 4)
708 - * @addr_width: number of address bytes
709 - * (3,4, or 0 for address not required)
710 - * @mode: mode data
711 - * @mode_pins: number of pins to send @mode (1, 2, 4)
712 - * @mode_cycles: number of mode cycles (0 for mode not required)
713 - * @dummy_cycles: number of dummy cycles (0 for dummy not required)
714 - */
715 -struct spi_nor_xfer_cfg {
716 - u8 wren;
717 - u8 cmd;
718 - u8 cmd_pins;
719 - u32 addr;
720 - u8 addr_pins;
721 - u8 addr_width;
722 - u8 mode;
723 - u8 mode_pins;
724 - u8 mode_cycles;
725 - u8 dummy_cycles;
726 -};
727 -
728 #define SPI_NOR_MAX_CMD_SIZE 8
729 enum spi_nor_ops {
730 SPI_NOR_OPS_READ = 0,
731 @@ -127,11 +117,14 @@ enum spi_nor_option_flags {
732 SNOR_F_USE_FSR = BIT(0),
733 };
734
735 +struct mtd_info;
736 +
737 /**
738 * struct spi_nor - Structure for defining a the SPI NOR layer
739 * @mtd: point to a mtd_info structure
740 * @lock: the lock for the read/write/erase/lock/unlock operations
741 * @dev: point to a spi device, or a spi nor controller device.
742 + * @flash_node: point to a device node describing this flash instance.
743 * @page_size: the page size of the SPI NOR
744 * @addr_width: number of address bytes
745 * @erase_opcode: the opcode for erasing a sector
746 @@ -141,28 +134,28 @@ enum spi_nor_option_flags {
747 * @flash_read: the mode of the read
748 * @sst_write_second: used by the SST write operation
749 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
750 - * @cfg: used by the read_xfer/write_xfer
751 * @cmd_buf: used by the write_reg
752 * @prepare: [OPTIONAL] do some preparations for the
753 * read/write/erase/lock/unlock operations
754 * @unprepare: [OPTIONAL] do some post work after the
755 * read/write/erase/lock/unlock operations
756 - * @read_xfer: [OPTIONAL] the read fundamental primitive
757 - * @write_xfer: [OPTIONAL] the writefundamental primitive
758 * @read_reg: [DRIVER-SPECIFIC] read out the register
759 * @write_reg: [DRIVER-SPECIFIC] write data to the register
760 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
761 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
762 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
763 * at the offset @offs
764 - * @lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
765 - * @unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
766 + * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
767 + * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
768 + * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
769 + * completely locked
770 * @priv: the private data
771 */
772 struct spi_nor {
773 - struct mtd_info *mtd;
774 + struct mtd_info mtd;
775 struct mutex lock;
776 struct device *dev;
777 + struct device_node *flash_node;
778 u32 page_size;
779 u8 addr_width;
780 u8 erase_opcode;
781 @@ -172,18 +165,12 @@ struct spi_nor {
782 enum read_mode flash_read;
783 bool sst_write_second;
784 u32 flags;
785 - struct spi_nor_xfer_cfg cfg;
786 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
787
788 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
789 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
790 - int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
791 - u8 *buf, size_t len);
792 - int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
793 - u8 *buf, size_t len);
794 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
795 - int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
796 - int write_enable);
797 + int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
798
799 int (*read)(struct spi_nor *nor, loff_t from,
800 size_t len, size_t *retlen, u_char *read_buf);
801 @@ -193,6 +180,7 @@ struct spi_nor {
802
803 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
804 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
805 + int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
806
807 void *priv;
808 };
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