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[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/platform_data/b53.h>
28
29 #include "b53_regs.h"
30 #include "b53_priv.h"
31
32 /* buffer size needed for displaying all MIBs with max'd values */
33 #define B53_BUF_SIZE 1188
34
35 struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39 };
40
41
42 /* BCM5365 MIB counters */
43 static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76 { },
77 };
78
79 /* BCM63xx MIB counters */
80 static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123 { }
124 };
125
126 /* MIB counters */
127 static const struct b53_mib_desc b53_mibs[] = {
128 { 8, 0x00, "TxOctets" },
129 { 4, 0x08, "TxDropPkts" },
130 { 4, 0x10, "TxBroadcastPkts" },
131 { 4, 0x14, "TxMulticastPkts" },
132 { 4, 0x18, "TxUnicastPkts" },
133 { 4, 0x1c, "TxCollisions" },
134 { 4, 0x20, "TxSingleCollision" },
135 { 4, 0x24, "TxMultipleCollision" },
136 { 4, 0x28, "TxDeferredTransmit" },
137 { 4, 0x2c, "TxLateCollision" },
138 { 4, 0x30, "TxExcessiveCollision" },
139 { 4, 0x38, "TxPausePkts" },
140 { 8, 0x50, "RxOctets" },
141 { 4, 0x58, "RxUndersizePkts" },
142 { 4, 0x5c, "RxPausePkts" },
143 { 4, 0x60, "Pkts64Octets" },
144 { 4, 0x64, "Pkts65to127Octets" },
145 { 4, 0x68, "Pkts128to255Octets" },
146 { 4, 0x6c, "Pkts256to511Octets" },
147 { 4, 0x70, "Pkts512to1023Octets" },
148 { 4, 0x74, "Pkts1024to1522Octets" },
149 { 4, 0x78, "RxOversizePkts" },
150 { 4, 0x7c, "RxJabbers" },
151 { 4, 0x80, "RxAlignmentErrors" },
152 { 4, 0x84, "RxFCSErrors" },
153 { 8, 0x88, "RxGoodOctets" },
154 { 4, 0x90, "RxDropPkts" },
155 { 4, 0x94, "RxUnicastPkts" },
156 { 4, 0x98, "RxMulticastPkts" },
157 { 4, 0x9c, "RxBroadcastPkts" },
158 { 4, 0xa0, "RxSAChanges" },
159 { 4, 0xa4, "RxFragments" },
160 { 4, 0xa8, "RxJumboPkts" },
161 { 4, 0xac, "RxSymbolErrors" },
162 { 4, 0xc0, "RxDiscarded" },
163 { }
164 };
165
166 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
167 {
168 unsigned int i;
169
170 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
171
172 for (i = 0; i < 10; i++) {
173 u8 vta;
174
175 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
176 if (!(vta & VTA_START_CMD))
177 return 0;
178
179 usleep_range(100, 200);
180 }
181
182 return -EIO;
183 }
184
185 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
186 u16 untag)
187 {
188 if (is5325(dev)) {
189 u32 entry = 0;
190
191 if (members) {
192 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
193 members;
194 if (dev->core_rev >= 3)
195 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
196 else
197 entry |= VA_VALID_25;
198 }
199
200 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
201 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
202 VTA_RW_STATE_WR | VTA_RW_OP_EN);
203 } else if (is5365(dev)) {
204 u16 entry = 0;
205
206 if (members)
207 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
208 members | VA_VALID_65;
209
210 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
211 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
212 VTA_RW_STATE_WR | VTA_RW_OP_EN);
213 } else {
214 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
215 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
216 (untag << VTE_UNTAG_S) | members);
217
218 b53_do_vlan_op(dev, VTA_CMD_WRITE);
219 }
220 }
221
222 void b53_set_forwarding(struct b53_device *dev, int enable)
223 {
224 u8 mgmt;
225
226 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
227
228 if (enable)
229 mgmt |= SM_SW_FWD_EN;
230 else
231 mgmt &= ~SM_SW_FWD_EN;
232
233 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
234 }
235
236 static void b53_enable_vlan(struct b53_device *dev, int enable)
237 {
238 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
239
240 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
241 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
242 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
243
244 if (is5325(dev) || is5365(dev)) {
245 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
246 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
247 } else if (is63xx(dev)) {
248 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
250 } else {
251 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
252 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
253 }
254
255 mgmt &= ~SM_SW_FWD_MODE;
256
257 if (enable) {
258 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
259 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
260 vc4 &= ~VC4_ING_VID_CHECK_MASK;
261 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
262 vc5 |= VC5_DROP_VTABLE_MISS;
263
264 if (is5325(dev))
265 vc0 &= ~VC0_RESERVED_1;
266
267 if (is5325(dev) || is5365(dev))
268 vc1 |= VC1_RX_MCST_TAG_EN;
269
270 if (!is5325(dev) && !is5365(dev)) {
271 if (dev->allow_vid_4095)
272 vc5 |= VC5_VID_FFF_EN;
273 else
274 vc5 &= ~VC5_VID_FFF_EN;
275 }
276 } else {
277 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
278 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
279 vc4 &= ~VC4_ING_VID_CHECK_MASK;
280 vc5 &= ~VC5_DROP_VTABLE_MISS;
281
282 if (is5325(dev) || is5365(dev))
283 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
284 else
285 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
286
287 if (is5325(dev) || is5365(dev))
288 vc1 &= ~VC1_RX_MCST_TAG_EN;
289
290 if (!is5325(dev) && !is5365(dev))
291 vc5 &= ~VC5_VID_FFF_EN;
292 }
293
294 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
295 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
296
297 if (is5325(dev) || is5365(dev)) {
298 /* enable the high 8 bit vid check on 5325 */
299 if (is5325(dev) && enable)
300 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
301 VC3_HIGH_8BIT_EN);
302 else
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
304
305 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
306 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
307 } else if (is63xx(dev)) {
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
309 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
310 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
311 } else {
312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
314 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
315 }
316
317 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
318 }
319
320 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
321 {
322 u32 port_mask = 0;
323 u16 max_size = JMS_MIN_SIZE;
324
325 if (is5325(dev) || is5365(dev))
326 return -EINVAL;
327
328 if (enable) {
329 port_mask = dev->enabled_ports;
330 max_size = JMS_MAX_SIZE;
331 if (allow_10_100)
332 port_mask |= JPM_10_100_JUMBO_EN;
333 }
334
335 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
336 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
337 }
338
339 static int b53_flush_arl(struct b53_device *dev)
340 {
341 unsigned int i;
342
343 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
344 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
345
346 for (i = 0; i < 10; i++) {
347 u8 fast_age_ctrl;
348
349 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
350 &fast_age_ctrl);
351
352 if (!(fast_age_ctrl & FAST_AGE_DONE))
353 return 0;
354
355 mdelay(1);
356 }
357
358 pr_warn("time out while flushing ARL\n");
359
360 return -EINVAL;
361 }
362
363 static void b53_enable_ports(struct b53_device *dev)
364 {
365 unsigned i;
366
367 b53_for_each_port(dev, i) {
368 u8 port_ctrl;
369 u16 pvlan_mask;
370
371 /*
372 * prevent leaking packets between wan and lan in unmanaged
373 * mode through port vlans.
374 */
375 if (dev->enable_vlan || is_cpu_port(dev, i))
376 pvlan_mask = 0x1ff;
377 else if (is531x5(dev) || is5301x(dev))
378 /* BCM53115 may use a different port as cpu port */
379 pvlan_mask = BIT(dev->sw_dev.cpu_port);
380 else
381 pvlan_mask = BIT(B53_CPU_PORT);
382
383 /* BCM5325 CPU port is at 8 */
384 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
385 i = B53_CPU_PORT;
386
387 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
388 /* disable unused ports 6 & 7 */
389 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
390 else if (i == B53_CPU_PORT)
391 port_ctrl = PORT_CTRL_RX_BCST_EN |
392 PORT_CTRL_RX_MCST_EN |
393 PORT_CTRL_RX_UCST_EN;
394 else
395 port_ctrl = 0;
396
397 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
398 pvlan_mask);
399
400 /* port state is handled by bcm63xx_enet driver */
401 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
402 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
403 port_ctrl);
404 }
405 }
406
407 static void b53_enable_mib(struct b53_device *dev)
408 {
409 u8 gc;
410
411 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
412
413 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
414
415 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
416 }
417
418 static int b53_apply(struct b53_device *dev)
419 {
420 int i;
421
422 /* clear all vlan entries */
423 if (is5325(dev) || is5365(dev)) {
424 for (i = 1; i < dev->sw_dev.vlans; i++)
425 b53_set_vlan_entry(dev, i, 0, 0);
426 } else {
427 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
428 }
429
430 b53_enable_vlan(dev, dev->enable_vlan);
431
432 /* fill VLAN table */
433 if (dev->enable_vlan) {
434 for (i = 0; i < dev->sw_dev.vlans; i++) {
435 struct b53_vlan *vlan = &dev->vlans[i];
436
437 if (!vlan->members)
438 continue;
439
440 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
441 }
442
443 b53_for_each_port(dev, i)
444 b53_write16(dev, B53_VLAN_PAGE,
445 B53_VLAN_PORT_DEF_TAG(i),
446 dev->ports[i].pvid);
447 } else {
448 b53_for_each_port(dev, i)
449 b53_write16(dev, B53_VLAN_PAGE,
450 B53_VLAN_PORT_DEF_TAG(i), 1);
451
452 }
453
454 b53_enable_ports(dev);
455
456 if (!is5325(dev) && !is5365(dev))
457 b53_set_jumbo(dev, dev->enable_jumbo, 1);
458
459 return 0;
460 }
461
462 static void b53_switch_reset_gpio(struct b53_device *dev)
463 {
464 int gpio = dev->reset_gpio;
465
466 if (gpio < 0)
467 return;
468
469 /*
470 * Reset sequence: RESET low(50ms)->high(20ms)
471 */
472 gpio_set_value(gpio, 0);
473 mdelay(50);
474
475 gpio_set_value(gpio, 1);
476 mdelay(20);
477
478 dev->current_page = 0xff;
479 }
480
481 static int b53_switch_reset(struct b53_device *dev)
482 {
483 u8 cpu_port = dev->sw_dev.cpu_port;
484 u8 mgmt;
485
486 b53_switch_reset_gpio(dev);
487
488 if (is539x(dev)) {
489 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
490 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
491 }
492
493 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
494
495 if (!(mgmt & SM_SW_FWD_EN)) {
496 mgmt &= ~SM_SW_FWD_MODE;
497 mgmt |= SM_SW_FWD_EN;
498
499 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
500 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
501
502 if (!(mgmt & SM_SW_FWD_EN)) {
503 pr_err("Failed to enable switch!\n");
504 return -EINVAL;
505 }
506 }
507
508 /* enable all ports */
509 b53_enable_ports(dev);
510
511 /* configure MII port if necessary */
512 if (is5325(dev)) {
513 u8 mii_port_override;
514
515 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
516 &mii_port_override);
517 /* reverse mii needs to be enabled */
518 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
519 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
520 mii_port_override | PORT_OVERRIDE_RV_MII_25);
521 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
522 &mii_port_override);
523
524 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
525 pr_err("Failed to enable reverse MII mode\n");
526 return -EINVAL;
527 }
528 }
529 } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) {
530 u8 mii_port_override;
531
532 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
533 &mii_port_override);
534 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
535 mii_port_override | PORT_OVERRIDE_EN |
536 PORT_OVERRIDE_LINK);
537
538 /* BCM47189 has another interface connected to the port 5 */
539 if (dev->enabled_ports & BIT(5)) {
540 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(5);
541 u8 gmii_po;
542
543 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
544 gmii_po |= GMII_PO_LINK |
545 GMII_PO_RX_FLOW |
546 GMII_PO_TX_FLOW |
547 GMII_PO_EN;
548 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
549 }
550 } else if (is5301x(dev)) {
551 if (cpu_port == 8) {
552 u8 mii_port_override;
553
554 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
555 &mii_port_override);
556 mii_port_override |= PORT_OVERRIDE_LINK |
557 PORT_OVERRIDE_RX_FLOW |
558 PORT_OVERRIDE_TX_FLOW |
559 PORT_OVERRIDE_SPEED_2000M |
560 PORT_OVERRIDE_EN;
561 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
562 mii_port_override);
563
564 /* TODO: Ports 5 & 7 require some extra handling */
565 } else {
566 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port);
567 u8 gmii_po;
568
569 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
570 gmii_po |= GMII_PO_LINK |
571 GMII_PO_RX_FLOW |
572 GMII_PO_TX_FLOW |
573 GMII_PO_EN |
574 GMII_PO_SPEED_2000M;
575 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
576 }
577 }
578
579 b53_enable_mib(dev);
580
581 return b53_flush_arl(dev);
582 }
583
584 /*
585 * Swconfig glue functions
586 */
587
588 static int b53_global_get_vlan_enable(struct switch_dev *dev,
589 const struct switch_attr *attr,
590 struct switch_val *val)
591 {
592 struct b53_device *priv = sw_to_b53(dev);
593
594 val->value.i = priv->enable_vlan;
595
596 return 0;
597 }
598
599 static int b53_global_set_vlan_enable(struct switch_dev *dev,
600 const struct switch_attr *attr,
601 struct switch_val *val)
602 {
603 struct b53_device *priv = sw_to_b53(dev);
604
605 priv->enable_vlan = val->value.i;
606
607 return 0;
608 }
609
610 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
611 const struct switch_attr *attr,
612 struct switch_val *val)
613 {
614 struct b53_device *priv = sw_to_b53(dev);
615
616 val->value.i = priv->enable_jumbo;
617
618 return 0;
619 }
620
621 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
622 const struct switch_attr *attr,
623 struct switch_val *val)
624 {
625 struct b53_device *priv = sw_to_b53(dev);
626
627 priv->enable_jumbo = val->value.i;
628
629 return 0;
630 }
631
632 static int b53_global_get_4095_enable(struct switch_dev *dev,
633 const struct switch_attr *attr,
634 struct switch_val *val)
635 {
636 struct b53_device *priv = sw_to_b53(dev);
637
638 val->value.i = priv->allow_vid_4095;
639
640 return 0;
641 }
642
643 static int b53_global_set_4095_enable(struct switch_dev *dev,
644 const struct switch_attr *attr,
645 struct switch_val *val)
646 {
647 struct b53_device *priv = sw_to_b53(dev);
648
649 priv->allow_vid_4095 = val->value.i;
650
651 return 0;
652 }
653
654 static int b53_global_get_ports(struct switch_dev *dev,
655 const struct switch_attr *attr,
656 struct switch_val *val)
657 {
658 struct b53_device *priv = sw_to_b53(dev);
659
660 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
661 priv->enabled_ports);
662 val->value.s = priv->buf;
663
664 return 0;
665 }
666
667 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
668 {
669 struct b53_device *priv = sw_to_b53(dev);
670
671 *val = priv->ports[port].pvid;
672
673 return 0;
674 }
675
676 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
677 {
678 struct b53_device *priv = sw_to_b53(dev);
679
680 if (val > 15 && is5325(priv))
681 return -EINVAL;
682 if (val == 4095 && !priv->allow_vid_4095)
683 return -EINVAL;
684
685 priv->ports[port].pvid = val;
686
687 return 0;
688 }
689
690 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
691 {
692 struct b53_device *priv = sw_to_b53(dev);
693 struct switch_port *port = &val->value.ports[0];
694 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
695 int i;
696
697 val->len = 0;
698
699 if (!vlan->members)
700 return 0;
701
702 for (i = 0; i < dev->ports; i++) {
703 if (!(vlan->members & BIT(i)))
704 continue;
705
706
707 if (!(vlan->untag & BIT(i)))
708 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
709 else
710 port->flags = 0;
711
712 port->id = i;
713 val->len++;
714 port++;
715 }
716
717 return 0;
718 }
719
720 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
721 {
722 struct b53_device *priv = sw_to_b53(dev);
723 struct switch_port *port;
724 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
725 int i;
726
727 /* only BCM5325 and BCM5365 supports VID 0 */
728 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
729 return -EINVAL;
730
731 /* VLAN 4095 needs special handling */
732 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
733 return -EINVAL;
734
735 port = &val->value.ports[0];
736 vlan->members = 0;
737 vlan->untag = 0;
738 for (i = 0; i < val->len; i++, port++) {
739 vlan->members |= BIT(port->id);
740
741 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
742 vlan->untag |= BIT(port->id);
743 priv->ports[port->id].pvid = val->port_vlan;
744 };
745 }
746
747 /* ignore disabled ports */
748 vlan->members &= priv->enabled_ports;
749 vlan->untag &= priv->enabled_ports;
750
751 return 0;
752 }
753
754 static int b53_port_get_link(struct switch_dev *dev, int port,
755 struct switch_port_link *link)
756 {
757 struct b53_device *priv = sw_to_b53(dev);
758
759 if (is_cpu_port(priv, port)) {
760 link->link = 1;
761 link->duplex = 1;
762 link->speed = is5325(priv) || is5365(priv) ?
763 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
764 link->aneg = 0;
765 } else if (priv->enabled_ports & BIT(port)) {
766 u32 speed;
767 u16 lnk, duplex;
768
769 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
770 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
771
772 lnk = (lnk >> port) & 1;
773 duplex = (duplex >> port) & 1;
774
775 if (is5325(priv) || is5365(priv)) {
776 u16 tmp;
777
778 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
779 speed = SPEED_PORT_FE(tmp, port);
780 } else {
781 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
782 speed = SPEED_PORT_GE(speed, port);
783 }
784
785 link->link = lnk;
786 if (lnk) {
787 link->duplex = duplex;
788 switch (speed) {
789 case SPEED_STAT_10M:
790 link->speed = SWITCH_PORT_SPEED_10;
791 break;
792 case SPEED_STAT_100M:
793 link->speed = SWITCH_PORT_SPEED_100;
794 break;
795 case SPEED_STAT_1000M:
796 link->speed = SWITCH_PORT_SPEED_1000;
797 break;
798 }
799 }
800
801 link->aneg = 1;
802 } else {
803 link->link = 0;
804 }
805
806 return 0;
807
808 }
809
810 static int b53_port_set_link(struct switch_dev *sw_dev, int port,
811 struct switch_port_link *link)
812 {
813 struct b53_device *dev = sw_to_b53(sw_dev);
814
815 /*
816 * TODO: BCM63XX requires special handling as it can have external phys
817 * and ports might be GE or only FE
818 */
819 if (is63xx(dev))
820 return -ENOTSUPP;
821
822 if (port == sw_dev->cpu_port)
823 return -EINVAL;
824
825 if (!(BIT(port) & dev->enabled_ports))
826 return -EINVAL;
827
828 if (link->speed == SWITCH_PORT_SPEED_1000 &&
829 (is5325(dev) || is5365(dev)))
830 return -EINVAL;
831
832 if (link->speed == SWITCH_PORT_SPEED_1000 && !link->duplex)
833 return -EINVAL;
834
835 return switch_generic_set_link(sw_dev, port, link);
836 }
837
838 static int b53_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)
839 {
840 struct b53_device *priv = sw_to_b53(dev);
841
842 if (priv->ops->phy_read16)
843 return priv->ops->phy_read16(priv, addr, reg, value);
844
845 return b53_read16(priv, B53_PORT_MII_PAGE(addr), reg, value);
846 }
847
848 static int b53_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)
849 {
850 struct b53_device *priv = sw_to_b53(dev);
851
852 if (priv->ops->phy_write16)
853 return priv->ops->phy_write16(priv, addr, reg, value);
854
855 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg, value);
856 }
857
858 static int b53_global_reset_switch(struct switch_dev *dev)
859 {
860 struct b53_device *priv = sw_to_b53(dev);
861
862 /* reset vlans */
863 priv->enable_vlan = 0;
864 priv->enable_jumbo = 0;
865 priv->allow_vid_4095 = 0;
866
867 memset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans);
868 memset(priv->ports, 0, sizeof(*priv->ports) * dev->ports);
869
870 return b53_switch_reset(priv);
871 }
872
873 static int b53_global_apply_config(struct switch_dev *dev)
874 {
875 struct b53_device *priv = sw_to_b53(dev);
876
877 /* disable switching */
878 b53_set_forwarding(priv, 0);
879
880 b53_apply(priv);
881
882 /* enable switching */
883 b53_set_forwarding(priv, 1);
884
885 return 0;
886 }
887
888
889 static int b53_global_reset_mib(struct switch_dev *dev,
890 const struct switch_attr *attr,
891 struct switch_val *val)
892 {
893 struct b53_device *priv = sw_to_b53(dev);
894 u8 gc;
895
896 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
897
898 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
899 mdelay(1);
900 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
901 mdelay(1);
902
903 return 0;
904 }
905
906 static int b53_port_get_mib(struct switch_dev *sw_dev,
907 const struct switch_attr *attr,
908 struct switch_val *val)
909 {
910 struct b53_device *dev = sw_to_b53(sw_dev);
911 const struct b53_mib_desc *mibs;
912 int port = val->port_vlan;
913 int len = 0;
914
915 if (!(BIT(port) & dev->enabled_ports))
916 return -1;
917
918 if (is5365(dev)) {
919 if (port == 5)
920 port = 8;
921
922 mibs = b53_mibs_65;
923 } else if (is63xx(dev)) {
924 mibs = b53_mibs_63xx;
925 } else {
926 mibs = b53_mibs;
927 }
928
929 dev->buf[0] = 0;
930
931 for (; mibs->size > 0; mibs++) {
932 u64 val;
933
934 if (mibs->size == 8) {
935 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
936 } else {
937 u32 val32;
938
939 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
940 &val32);
941 val = val32;
942 }
943
944 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
945 "%-20s: %llu\n", mibs->name, val);
946 }
947
948 val->len = len;
949 val->value.s = dev->buf;
950
951 return 0;
952 }
953
954 static struct switch_attr b53_global_ops_25[] = {
955 {
956 .type = SWITCH_TYPE_INT,
957 .name = "enable_vlan",
958 .description = "Enable VLAN mode",
959 .set = b53_global_set_vlan_enable,
960 .get = b53_global_get_vlan_enable,
961 .max = 1,
962 },
963 {
964 .type = SWITCH_TYPE_STRING,
965 .name = "ports",
966 .description = "Available ports (as bitmask)",
967 .get = b53_global_get_ports,
968 },
969 };
970
971 static struct switch_attr b53_global_ops_65[] = {
972 {
973 .type = SWITCH_TYPE_INT,
974 .name = "enable_vlan",
975 .description = "Enable VLAN mode",
976 .set = b53_global_set_vlan_enable,
977 .get = b53_global_get_vlan_enable,
978 .max = 1,
979 },
980 {
981 .type = SWITCH_TYPE_STRING,
982 .name = "ports",
983 .description = "Available ports (as bitmask)",
984 .get = b53_global_get_ports,
985 },
986 {
987 .type = SWITCH_TYPE_INT,
988 .name = "reset_mib",
989 .description = "Reset MIB counters",
990 .set = b53_global_reset_mib,
991 },
992 };
993
994 static struct switch_attr b53_global_ops[] = {
995 {
996 .type = SWITCH_TYPE_INT,
997 .name = "enable_vlan",
998 .description = "Enable VLAN mode",
999 .set = b53_global_set_vlan_enable,
1000 .get = b53_global_get_vlan_enable,
1001 .max = 1,
1002 },
1003 {
1004 .type = SWITCH_TYPE_STRING,
1005 .name = "ports",
1006 .description = "Available Ports (as bitmask)",
1007 .get = b53_global_get_ports,
1008 },
1009 {
1010 .type = SWITCH_TYPE_INT,
1011 .name = "reset_mib",
1012 .description = "Reset MIB counters",
1013 .set = b53_global_reset_mib,
1014 },
1015 {
1016 .type = SWITCH_TYPE_INT,
1017 .name = "enable_jumbo",
1018 .description = "Enable Jumbo Frames",
1019 .set = b53_global_set_jumbo_enable,
1020 .get = b53_global_get_jumbo_enable,
1021 .max = 1,
1022 },
1023 {
1024 .type = SWITCH_TYPE_INT,
1025 .name = "allow_vid_4095",
1026 .description = "Allow VID 4095",
1027 .set = b53_global_set_4095_enable,
1028 .get = b53_global_get_4095_enable,
1029 .max = 1,
1030 },
1031 };
1032
1033 static struct switch_attr b53_port_ops[] = {
1034 {
1035 .type = SWITCH_TYPE_STRING,
1036 .name = "mib",
1037 .description = "Get port's MIB counters",
1038 .get = b53_port_get_mib,
1039 },
1040 };
1041
1042 static struct switch_attr b53_no_ops[] = {
1043 };
1044
1045 static const struct switch_dev_ops b53_switch_ops_25 = {
1046 .attr_global = {
1047 .attr = b53_global_ops_25,
1048 .n_attr = ARRAY_SIZE(b53_global_ops_25),
1049 },
1050 .attr_port = {
1051 .attr = b53_no_ops,
1052 .n_attr = ARRAY_SIZE(b53_no_ops),
1053 },
1054 .attr_vlan = {
1055 .attr = b53_no_ops,
1056 .n_attr = ARRAY_SIZE(b53_no_ops),
1057 },
1058
1059 .get_vlan_ports = b53_vlan_get_ports,
1060 .set_vlan_ports = b53_vlan_set_ports,
1061 .get_port_pvid = b53_port_get_pvid,
1062 .set_port_pvid = b53_port_set_pvid,
1063 .apply_config = b53_global_apply_config,
1064 .reset_switch = b53_global_reset_switch,
1065 .get_port_link = b53_port_get_link,
1066 .set_port_link = b53_port_set_link,
1067 .phy_read16 = b53_phy_read16,
1068 .phy_write16 = b53_phy_write16,
1069 };
1070
1071 static const struct switch_dev_ops b53_switch_ops_65 = {
1072 .attr_global = {
1073 .attr = b53_global_ops_65,
1074 .n_attr = ARRAY_SIZE(b53_global_ops_65),
1075 },
1076 .attr_port = {
1077 .attr = b53_port_ops,
1078 .n_attr = ARRAY_SIZE(b53_port_ops),
1079 },
1080 .attr_vlan = {
1081 .attr = b53_no_ops,
1082 .n_attr = ARRAY_SIZE(b53_no_ops),
1083 },
1084
1085 .get_vlan_ports = b53_vlan_get_ports,
1086 .set_vlan_ports = b53_vlan_set_ports,
1087 .get_port_pvid = b53_port_get_pvid,
1088 .set_port_pvid = b53_port_set_pvid,
1089 .apply_config = b53_global_apply_config,
1090 .reset_switch = b53_global_reset_switch,
1091 .get_port_link = b53_port_get_link,
1092 .set_port_link = b53_port_set_link,
1093 .phy_read16 = b53_phy_read16,
1094 .phy_write16 = b53_phy_write16,
1095 };
1096
1097 static const struct switch_dev_ops b53_switch_ops = {
1098 .attr_global = {
1099 .attr = b53_global_ops,
1100 .n_attr = ARRAY_SIZE(b53_global_ops),
1101 },
1102 .attr_port = {
1103 .attr = b53_port_ops,
1104 .n_attr = ARRAY_SIZE(b53_port_ops),
1105 },
1106 .attr_vlan = {
1107 .attr = b53_no_ops,
1108 .n_attr = ARRAY_SIZE(b53_no_ops),
1109 },
1110
1111 .get_vlan_ports = b53_vlan_get_ports,
1112 .set_vlan_ports = b53_vlan_set_ports,
1113 .get_port_pvid = b53_port_get_pvid,
1114 .set_port_pvid = b53_port_set_pvid,
1115 .apply_config = b53_global_apply_config,
1116 .reset_switch = b53_global_reset_switch,
1117 .get_port_link = b53_port_get_link,
1118 .set_port_link = b53_port_set_link,
1119 .phy_read16 = b53_phy_read16,
1120 .phy_write16 = b53_phy_write16,
1121 };
1122
1123 struct b53_chip_data {
1124 u32 chip_id;
1125 const char *dev_name;
1126 const char *alias;
1127 u16 vlans;
1128 u16 enabled_ports;
1129 u8 cpu_port;
1130 u8 vta_regs[3];
1131 u8 duplex_reg;
1132 u8 jumbo_pm_reg;
1133 u8 jumbo_size_reg;
1134 const struct switch_dev_ops *sw_ops;
1135 };
1136
1137 #define B53_VTA_REGS \
1138 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1139 #define B53_VTA_REGS_9798 \
1140 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1141 #define B53_VTA_REGS_63XX \
1142 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1143
1144 static const struct b53_chip_data b53_switch_chips[] = {
1145 {
1146 .chip_id = BCM5325_DEVICE_ID,
1147 .dev_name = "BCM5325",
1148 .alias = "bcm5325",
1149 .vlans = 16,
1150 .enabled_ports = 0x1f,
1151 .cpu_port = B53_CPU_PORT_25,
1152 .duplex_reg = B53_DUPLEX_STAT_FE,
1153 .sw_ops = &b53_switch_ops_25,
1154 },
1155 {
1156 .chip_id = BCM5365_DEVICE_ID,
1157 .dev_name = "BCM5365",
1158 .alias = "bcm5365",
1159 .vlans = 256,
1160 .enabled_ports = 0x1f,
1161 .cpu_port = B53_CPU_PORT_25,
1162 .duplex_reg = B53_DUPLEX_STAT_FE,
1163 .sw_ops = &b53_switch_ops_65,
1164 },
1165 {
1166 .chip_id = BCM5395_DEVICE_ID,
1167 .dev_name = "BCM5395",
1168 .alias = "bcm5395",
1169 .vlans = 4096,
1170 .enabled_ports = 0x1f,
1171 .cpu_port = B53_CPU_PORT,
1172 .vta_regs = B53_VTA_REGS,
1173 .duplex_reg = B53_DUPLEX_STAT_GE,
1174 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1175 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1176 .sw_ops = &b53_switch_ops,
1177 },
1178 {
1179 .chip_id = BCM5397_DEVICE_ID,
1180 .dev_name = "BCM5397",
1181 .alias = "bcm5397",
1182 .vlans = 4096,
1183 .enabled_ports = 0x1f,
1184 .cpu_port = B53_CPU_PORT,
1185 .vta_regs = B53_VTA_REGS_9798,
1186 .duplex_reg = B53_DUPLEX_STAT_GE,
1187 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1188 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1189 .sw_ops = &b53_switch_ops,
1190 },
1191 {
1192 .chip_id = BCM5398_DEVICE_ID,
1193 .dev_name = "BCM5398",
1194 .alias = "bcm5398",
1195 .vlans = 4096,
1196 .enabled_ports = 0x7f,
1197 .cpu_port = B53_CPU_PORT,
1198 .vta_regs = B53_VTA_REGS_9798,
1199 .duplex_reg = B53_DUPLEX_STAT_GE,
1200 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1201 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1202 .sw_ops = &b53_switch_ops,
1203 },
1204 {
1205 .chip_id = BCM53115_DEVICE_ID,
1206 .dev_name = "BCM53115",
1207 .alias = "bcm53115",
1208 .vlans = 4096,
1209 .enabled_ports = 0x1f,
1210 .vta_regs = B53_VTA_REGS,
1211 .cpu_port = B53_CPU_PORT,
1212 .duplex_reg = B53_DUPLEX_STAT_GE,
1213 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1214 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1215 .sw_ops = &b53_switch_ops,
1216 },
1217 {
1218 .chip_id = BCM53125_DEVICE_ID,
1219 .dev_name = "BCM53125",
1220 .alias = "bcm53125",
1221 .vlans = 4096,
1222 .enabled_ports = 0x1f,
1223 .cpu_port = B53_CPU_PORT,
1224 .vta_regs = B53_VTA_REGS,
1225 .duplex_reg = B53_DUPLEX_STAT_GE,
1226 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1227 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1228 .sw_ops = &b53_switch_ops,
1229 },
1230 {
1231 .chip_id = BCM53128_DEVICE_ID,
1232 .dev_name = "BCM53128",
1233 .alias = "bcm53128",
1234 .vlans = 4096,
1235 .enabled_ports = 0x1ff,
1236 .cpu_port = B53_CPU_PORT,
1237 .vta_regs = B53_VTA_REGS,
1238 .duplex_reg = B53_DUPLEX_STAT_GE,
1239 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1240 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1241 .sw_ops = &b53_switch_ops,
1242 },
1243 {
1244 .chip_id = BCM63XX_DEVICE_ID,
1245 .dev_name = "BCM63xx",
1246 .alias = "bcm63xx",
1247 .vlans = 4096,
1248 .enabled_ports = 0, /* pdata must provide them */
1249 .cpu_port = B53_CPU_PORT,
1250 .vta_regs = B53_VTA_REGS_63XX,
1251 .duplex_reg = B53_DUPLEX_STAT_63XX,
1252 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1253 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1254 .sw_ops = &b53_switch_ops,
1255 },
1256 {
1257 .chip_id = BCM53010_DEVICE_ID,
1258 .dev_name = "BCM53010",
1259 .alias = "bcm53011",
1260 .vlans = 4096,
1261 .enabled_ports = 0x1f,
1262 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1263 .vta_regs = B53_VTA_REGS,
1264 .duplex_reg = B53_DUPLEX_STAT_GE,
1265 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1266 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1267 .sw_ops = &b53_switch_ops,
1268 },
1269 {
1270 .chip_id = BCM53011_DEVICE_ID,
1271 .dev_name = "BCM53011",
1272 .alias = "bcm53011",
1273 .vlans = 4096,
1274 .enabled_ports = 0x1bf,
1275 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1276 .vta_regs = B53_VTA_REGS,
1277 .duplex_reg = B53_DUPLEX_STAT_GE,
1278 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1279 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1280 .sw_ops = &b53_switch_ops,
1281 },
1282 {
1283 .chip_id = BCM53012_DEVICE_ID,
1284 .dev_name = "BCM53012",
1285 .alias = "bcm53011",
1286 .vlans = 4096,
1287 .enabled_ports = 0x1bf,
1288 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1289 .vta_regs = B53_VTA_REGS,
1290 .duplex_reg = B53_DUPLEX_STAT_GE,
1291 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1292 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1293 .sw_ops = &b53_switch_ops,
1294 },
1295 {
1296 .chip_id = BCM53018_DEVICE_ID,
1297 .dev_name = "BCM53018",
1298 .alias = "bcm53018",
1299 .vlans = 4096,
1300 .enabled_ports = 0x1f,
1301 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1302 .vta_regs = B53_VTA_REGS,
1303 .duplex_reg = B53_DUPLEX_STAT_GE,
1304 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1305 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1306 .sw_ops = &b53_switch_ops,
1307 },
1308 {
1309 .chip_id = BCM53019_DEVICE_ID,
1310 .dev_name = "BCM53019",
1311 .alias = "bcm53019",
1312 .vlans = 4096,
1313 .enabled_ports = 0x1f,
1314 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1315 .vta_regs = B53_VTA_REGS,
1316 .duplex_reg = B53_DUPLEX_STAT_GE,
1317 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1318 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1319 .sw_ops = &b53_switch_ops,
1320 },
1321 };
1322
1323 static int b53_switch_init(struct b53_device *dev)
1324 {
1325 struct switch_dev *sw_dev = &dev->sw_dev;
1326 unsigned i;
1327 int ret;
1328
1329 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1330 const struct b53_chip_data *chip = &b53_switch_chips[i];
1331
1332 if (chip->chip_id == dev->chip_id) {
1333 sw_dev->name = chip->dev_name;
1334 if (!sw_dev->alias)
1335 sw_dev->alias = chip->alias;
1336 if (!dev->enabled_ports)
1337 dev->enabled_ports = chip->enabled_ports;
1338 dev->duplex_reg = chip->duplex_reg;
1339 dev->vta_regs[0] = chip->vta_regs[0];
1340 dev->vta_regs[1] = chip->vta_regs[1];
1341 dev->vta_regs[2] = chip->vta_regs[2];
1342 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1343 sw_dev->ops = chip->sw_ops;
1344 sw_dev->cpu_port = chip->cpu_port;
1345 sw_dev->vlans = chip->vlans;
1346 break;
1347 }
1348 }
1349
1350 if (!sw_dev->name)
1351 return -EINVAL;
1352
1353 /* check which BCM5325x version we have */
1354 if (is5325(dev)) {
1355 u8 vc4;
1356
1357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1358
1359 /* check reserved bits */
1360 switch (vc4 & 3) {
1361 case 1:
1362 /* BCM5325E */
1363 break;
1364 case 3:
1365 /* BCM5325F - do not use port 4 */
1366 dev->enabled_ports &= ~BIT(4);
1367 break;
1368 default:
1369 /* On the BCM47XX SoCs this is the supported internal switch.*/
1370 #ifndef CONFIG_BCM47XX
1371 /* BCM5325M */
1372 return -EINVAL;
1373 #else
1374 break;
1375 #endif
1376 }
1377 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1378 u64 strap_value;
1379
1380 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1381 /* use second IMP port if GMII is enabled */
1382 if (strap_value & SV_GMII_CTRL_115)
1383 sw_dev->cpu_port = 5;
1384 }
1385
1386 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1387 sw_dev->ports = fls(dev->enabled_ports);
1388
1389 dev->ports = devm_kzalloc(dev->dev,
1390 sizeof(struct b53_port) * sw_dev->ports,
1391 GFP_KERNEL);
1392 if (!dev->ports)
1393 return -ENOMEM;
1394
1395 dev->vlans = devm_kzalloc(dev->dev,
1396 sizeof(struct b53_vlan) * sw_dev->vlans,
1397 GFP_KERNEL);
1398 if (!dev->vlans)
1399 return -ENOMEM;
1400
1401 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1402 if (!dev->buf)
1403 return -ENOMEM;
1404
1405 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1406 if (dev->reset_gpio >= 0) {
1407 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1408 GPIOF_OUT_INIT_HIGH, "robo_reset");
1409 if (ret)
1410 return ret;
1411 }
1412
1413 return b53_switch_reset(dev);
1414 }
1415
1416 struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,
1417 void *priv)
1418 {
1419 struct b53_device *dev;
1420
1421 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1422 if (!dev)
1423 return NULL;
1424
1425 dev->dev = base;
1426 dev->ops = ops;
1427 dev->priv = priv;
1428 mutex_init(&dev->reg_mutex);
1429
1430 return dev;
1431 }
1432 EXPORT_SYMBOL(b53_switch_alloc);
1433
1434 int b53_switch_detect(struct b53_device *dev)
1435 {
1436 u32 id32;
1437 u16 tmp;
1438 u8 id8;
1439 int ret;
1440
1441 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1442 if (ret)
1443 return ret;
1444
1445 switch (id8) {
1446 case 0:
1447 /*
1448 * BCM5325 and BCM5365 do not have this register so reads
1449 * return 0. But the read operation did succeed, so assume
1450 * this is one of them.
1451 *
1452 * Next check if we can write to the 5325's VTA register; for
1453 * 5365 it is read only.
1454 */
1455
1456 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1457 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1458
1459 if (tmp == 0xf)
1460 dev->chip_id = BCM5325_DEVICE_ID;
1461 else
1462 dev->chip_id = BCM5365_DEVICE_ID;
1463 break;
1464 case BCM5395_DEVICE_ID:
1465 case BCM5397_DEVICE_ID:
1466 case BCM5398_DEVICE_ID:
1467 dev->chip_id = id8;
1468 break;
1469 default:
1470 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1471 if (ret)
1472 return ret;
1473
1474 switch (id32) {
1475 case BCM53115_DEVICE_ID:
1476 case BCM53125_DEVICE_ID:
1477 case BCM53128_DEVICE_ID:
1478 case BCM53010_DEVICE_ID:
1479 case BCM53011_DEVICE_ID:
1480 case BCM53012_DEVICE_ID:
1481 case BCM53018_DEVICE_ID:
1482 case BCM53019_DEVICE_ID:
1483 dev->chip_id = id32;
1484 break;
1485 default:
1486 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1487 id8, id32);
1488 return -ENODEV;
1489 }
1490 }
1491
1492 if (dev->chip_id == BCM5325_DEVICE_ID)
1493 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1494 &dev->core_rev);
1495 else
1496 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1497 &dev->core_rev);
1498 }
1499 EXPORT_SYMBOL(b53_switch_detect);
1500
1501 int b53_switch_register(struct b53_device *dev)
1502 {
1503 int ret;
1504
1505 if (dev->pdata) {
1506 dev->chip_id = dev->pdata->chip_id;
1507 dev->enabled_ports = dev->pdata->enabled_ports;
1508 dev->sw_dev.alias = dev->pdata->alias;
1509 }
1510
1511 if (!dev->chip_id && b53_switch_detect(dev))
1512 return -EINVAL;
1513
1514 ret = b53_switch_init(dev);
1515 if (ret)
1516 return ret;
1517
1518 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1519
1520 return register_switch(&dev->sw_dev, NULL);
1521 }
1522 EXPORT_SYMBOL(b53_switch_register);
1523
1524 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1525 MODULE_DESCRIPTION("B53 switch library");
1526 MODULE_LICENSE("Dual BSD/GPL");
OpenWrt Source Repository