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[openwrt/openwrt.git] / target / linux / generic / files / crypto / ocf / kirkwood / mvHal / mv_hal / pci / mvPci.c
1 /*******************************************************************************
2 Copyright (C) Marvell International Ltd. and its affiliates
3
4 This software file (the "File") is owned and distributed by Marvell
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11
12 ********************************************************************************
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14
15 If you received this File from Marvell and you have entered into a commercial
16 license agreement (a "Commercial License") with Marvell, the File is licensed
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19 ********************************************************************************
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23 modify this File in accordance with the terms and conditions of the General
24 Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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30 WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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39 are permitted provided that the following conditions are met:
40
41 * Redistributions of source code must retain the above copyright notice,
42 this list of conditions and the following disclaimer.
43
44 * Redistributions in binary form must reproduce the above copyright
45 notice, this list of conditions and the following disclaimer in the
46 documentation and/or other materials provided with the distribution.
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48 * Neither the name of Marvell nor the names of its contributors may be
49 used to endorse or promote products derived from this software without
50 specific prior written permission.
51
52 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
53 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
54 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
55 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
56 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
58 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
59 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62
63 *******************************************************************************/
64 #include "pci/mvPci.h"
65
66 #include "ctrlEnv/mvCtrlEnvLib.h"
67
68 /* defines */
69 #ifdef MV_DEBUG
70 #define DB(x) x
71 #else
72 #define DB(x)
73 #endif
74
75
76
77 MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod)
78 {
79 if (MV_PCI_MOD_HOST == pciIfmod)
80 {
81
82 mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf));
83 mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf));
84
85 /* Local device master Enable */
86 mvPciMasterEnable(pciIf, MV_TRUE);
87
88 /* Local device slave Enable */
89 mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf),
90 mvPciLocalDevNumGet(pciIf), MV_TRUE);
91 }
92 /* enable CPU-2-PCI ordering */
93 MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN);
94 }
95
96 /*******************************************************************************
97 * mvPciCommandSet - Set PCI comman register value.
98 *
99 * DESCRIPTION:
100 * This function sets a given PCI interface with its command register
101 * value.
102 *
103 * INPUT:
104 * pciIf - PCI interface number.
105 * command - 32bit value to be written to comamnd register.
106 *
107 * OUTPUT:
108 * None.
109 *
110 * RETURN:
111 * MV_BAD_PARAM if pciIf is not in range otherwise MV_OK
112 *
113 *******************************************************************************/
114 MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command)
115 {
116 MV_U32 locBusNum, locDevNum, regVal;
117
118 locBusNum = mvPciLocalBusNumGet(pciIf);
119 locDevNum = mvPciLocalDevNumGet(pciIf);
120
121 /* Parameter checking */
122 if (pciIf >= mvCtrlPciMaxIfGet())
123 {
124 mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf);
125 return MV_BAD_PARAM;
126 }
127
128 /* Set command register */
129 MV_REG_WRITE(PCI_CMD_REG(pciIf), command);
130
131 /* Upodate device max outstanding split tarnsaction */
132 if ((command & PCR_CPU_TO_PCI_ORDER_EN) &&
133 (command & PCR_PCI_TO_CPU_ORDER_EN))
134 {
135 /* Read PCI-X command register */
136 regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND);
137
138 /* clear bits 22:20 */
139 regVal &= 0xff8fffff;
140
141 /* set reset value */
142 regVal |= (0x3 << 20);
143
144 /* Write back the value */
145 mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal);
146 }
147
148 return MV_OK;
149
150
151 }
152
153
154 /*******************************************************************************
155 * mvPciModeGet - Get PCI interface mode.
156 *
157 * DESCRIPTION:
158 * This function returns the given PCI interface mode.
159 *
160 * INPUT:
161 * pciIf - PCI interface number.
162 *
163 * OUTPUT:
164 * pPciMode - Pointer to PCI mode structure.
165 *
166 * RETURN:
167 * MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
168 *
169 *******************************************************************************/
170 MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode)
171 {
172 MV_U32 pciMode;
173
174 /* Parameter checking */
175 if (pciIf >= mvCtrlPciMaxIfGet())
176 {
177 mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf);
178 return MV_BAD_PARAM;
179 }
180 if (NULL == pPciMode)
181 {
182 mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n");
183 return MV_BAD_PARAM;
184 }
185
186 /* Read pci mode register */
187 pciMode = MV_REG_READ(PCI_MODE_REG(pciIf));
188
189 switch (pciMode & PMR_PCI_MODE_MASK)
190 {
191 case PMR_PCI_MODE_CONV:
192 pPciMode->pciType = MV_PCI_CONV;
193
194 if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN)
195 {
196 pPciMode->pciSpeed = 66000000; /* 66MHZ */
197 }
198 else
199 {
200 pPciMode->pciSpeed = 33000000; /* 33MHZ */
201 }
202
203 break;
204
205 case PMR_PCI_MODE_PCIX_66MHZ:
206 pPciMode->pciType = MV_PCIX;
207 pPciMode->pciSpeed = 66000000; /* 66MHZ */
208 break;
209
210 case PMR_PCI_MODE_PCIX_100MHZ:
211 pPciMode->pciType = MV_PCIX;
212 pPciMode->pciSpeed = 100000000; /* 100MHZ */
213 break;
214
215 case PMR_PCI_MODE_PCIX_133MHZ:
216 pPciMode->pciType = MV_PCIX;
217 pPciMode->pciSpeed = 133000000; /* 133MHZ */
218 break;
219
220 default:
221 {
222 mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n");
223 return MV_ERROR;
224 }
225 }
226
227 switch (pciMode & PMR_PCI_64_MASK)
228 {
229 case PMR_PCI_64_64BIT:
230 pPciMode->pciWidth = MV_PCI_64;
231 break;
232
233 case PMR_PCI_64_32BIT:
234 pPciMode->pciWidth = MV_PCI_32;
235 break;
236
237 default:
238 {
239 mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n");
240 return MV_ERROR;
241 }
242 }
243
244 return MV_OK;
245 }
246
247 /*******************************************************************************
248 * mvPciRetrySet - Set PCI retry counters
249 *
250 * DESCRIPTION:
251 * This function specifies the number of times the PCI controller
252 * retries a transaction before it quits.
253 * Applies to the PCI Master when acting as a requester.
254 * Applies to the PCI slave when acting as a completer (PCI-X mode).
255 * A 0x00 value means a "retry forever".
256 *
257 * INPUT:
258 * pciIf - PCI interface number.
259 * counter - Number of times PCI controller retry. Use counter value
260 * up to PRR_RETRY_CNTR_MAX.
261 *
262 * OUTPUT:
263 * None.
264 *
265 * RETURN:
266 * MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
267 *
268 *******************************************************************************/
269 MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter)
270 {
271 MV_U32 pciRetry;
272
273 /* Parameter checking */
274 if (pciIf >= mvCtrlPciMaxIfGet())
275 {
276 mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf);
277 return MV_BAD_PARAM;
278 }
279
280 if (counter >= PRR_RETRY_CNTR_MAX)
281 {
282 mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter);
283 return MV_BAD_PARAM;
284
285 }
286
287 /* Reading PCI retry register */
288 pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf));
289
290 pciRetry &= ~PRR_RETRY_CNTR_MASK;
291
292 pciRetry |= (counter << PRR_RETRY_CNTR_OFFS);
293
294 /* write new value */
295 MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry);
296
297 return MV_OK;
298 }
299
300
301 /*******************************************************************************
302 * mvPciDiscardTimerSet - Set PCI discard timer
303 *
304 * DESCRIPTION:
305 * This function set PCI discard timer.
306 * In conventional PCI mode:
307 * Specifies the number of PCLK cycles the PCI slave keeps a non-accessed
308 * read buffers (non-completed delayed read) before invalidate the buffer.
309 * Set to '0' to disable the timer. The PCI slave waits for delayed
310 * read completion forever.
311 * In PCI-X mode:
312 * Specifies the number of PCLK cycles the PCI master waits for split
313 * completion transaction, before it invalidates the pre-allocated read
314 * buffer.
315 * Set to '0' to disable the timer. The PCI master waits for split
316 * completion forever.
317 * NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK,
318 * unless using the "wait for ever" setting 0x0.
319 * NOTE: Must not be updated while there are pending read requests.
320 *
321 * INPUT:
322 * pciIf - PCI interface number.
323 * pClkCycles - Number of PCI clock cycles.
324 *
325 * OUTPUT:
326 * None.
327 *
328 * RETURN:
329 * MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
330 *
331 *******************************************************************************/
332 MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles)
333 {
334 MV_U32 pciDiscardTimer;
335
336 /* Parameter checking */
337 if (pciIf >= mvCtrlPciMaxIfGet())
338 {
339 mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n",
340 pciIf);
341 return MV_BAD_PARAM;
342 }
343
344 if (pClkCycles >= PDTR_TIMER_MIN)
345 {
346 mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n",
347 pClkCycles);
348 return MV_BAD_PARAM;
349
350 }
351
352 /* Read PCI Discard Timer */
353 pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf));
354
355 pciDiscardTimer &= ~PDTR_TIMER_MASK;
356
357 pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS);
358
359 /* Write new value */
360 MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer);
361
362 return MV_OK;
363
364 }
365
366 /* PCI Arbiter routines */
367
368 /*******************************************************************************
369 * mvPciArbEnable - PCI arbiter enable/disable
370 *
371 * DESCRIPTION:
372 * This fuction enable/disables a given PCI interface arbiter.
373 * NOTE: Arbiter setting can not be changed while in work. It should only
374 * be set once.
375 * INPUT:
376 * pciIf - PCI interface number.
377 * enable - Enable/disable parameter. If enable = MV_TRUE then enable.
378 *
379 * OUTPUT:
380 * None.
381 *
382 * RETURN:
383 * None.
384 *
385 *******************************************************************************/
386 MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable)
387 {
388 MV_U32 regVal;
389
390 /* Parameter checking */
391 if (pciIf >= mvCtrlPciMaxIfGet())
392 {
393 mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf);
394 return MV_ERROR;
395 }
396
397 /* Set PCI Arbiter Control register according to default configuration */
398 regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf));
399
400 /* Make sure arbiter disabled before changing its values */
401 MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE);
402
403 regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK;
404
405 regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */
406
407 if (MV_TRUE == enable)
408 {
409 regVal |= PACR_ARB_ENABLE;
410 }
411 else
412 {
413 regVal &= ~PACR_ARB_ENABLE;
414 }
415
416 /* Write to register */
417 MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal);
418
419 return MV_OK;
420 }
421
422
423 /*******************************************************************************
424 * mvPciArbParkDis - Disable arbiter parking on agent
425 *
426 * DESCRIPTION:
427 * This function disables the PCI arbiter from parking on the given agent
428 * list.
429 *
430 * INPUT:
431 * pciIf - PCI interface number.
432 * pciAgentMask - When a bit in the mask is set to '1', parking on
433 * the associated PCI master is disabled. Mask bit
434 * refers to bit 0 - 6. For example disable parking on PCI
435 * agent 3 set pciAgentMask 0x4 (bit 3 is set).
436 *
437 * OUTPUT:
438 * None.
439 *
440 * RETURN:
441 * None.
442 *
443 *******************************************************************************/
444 MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask)
445 {
446 MV_U32 pciArbiterCtrl;
447
448 /* Parameter checking */
449 if (pciIf >= mvCtrlPciMaxIfGet())
450 {
451 mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf);
452 return MV_ERROR;
453 }
454
455 /* Reading Arbiter Control register */
456 pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf));
457
458 /* Arbiter must be disabled before changing parking */
459 MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE);
460
461 /* do the change */
462 pciArbiterCtrl &= ~PACR_PARK_DIS_MASK;
463 pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS);
464
465 /* writing new value ( if th earbiter was enabled before the change */
466 /* here it will be reenabled */
467 MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl);
468
469 return MV_OK;
470 }
471
472
473 /*******************************************************************************
474 * mvPciArbBrokDetectSet - Set PCI arbiter broken detection
475 *
476 * DESCRIPTION:
477 * This function sets the maximum number of cycles that the arbiter
478 * waits for a PCI master to respond to its grant assertion. If a
479 * PCI agent fails to respond within this time, the PCI arbiter aborts
480 * the transaction and performs a new arbitration cycle.
481 * NOTE: Value must be greater than '1' for conventional PCI and
482 * greater than '5' for PCI-X.
483 *
484 * INPUT:
485 * pciIf - PCI interface number.
486 * pClkCycles - Number of PCI clock cycles. If equal to '0' the broken
487 * master detection is disabled.
488 *
489 * OUTPUT:
490 * None.
491 *
492 * RETURN:
493 * MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
494 *
495 *******************************************************************************/
496 MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles)
497 {
498 MV_U32 pciArbiterCtrl;
499 MV_U32 pciMode;
500
501 /* Parameter checking */
502 if (pciIf >= mvCtrlPciMaxIfGet())
503 {
504 mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n",
505 pciIf);
506 return MV_BAD_PARAM;
507 }
508
509 /* Checking PCI mode and if pClkCycles is legal value */
510 pciMode = MV_REG_READ(PCI_MODE_REG(pciIf));
511 pciMode &= PMR_PCI_MODE_MASK;
512
513 if (PMR_PCI_MODE_CONV == pciMode)
514 {
515 if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN)
516 return MV_ERROR;
517 }
518 else
519 {
520 if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN)
521 return MV_ERROR;
522 }
523
524 pClkCycles <<= PACR_BROKEN_VAL_OFFS;
525
526 /* Reading Arbiter Control register */
527 pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf));
528 pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK;
529 pciArbiterCtrl |= pClkCycles;
530
531 /* Arbiter must be disabled before changing broken detection */
532 MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE);
533
534 /* writing new value ( if th earbiter was enabled before the change */
535 /* here it will be reenabled */
536
537 MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl);
538
539 return MV_OK;
540 }
541
542 /* PCI configuration space read write */
543
544 /*******************************************************************************
545 * mvPciConfigRead - Read from configuration space
546 *
547 * DESCRIPTION:
548 * This function performs a 32 bit read from PCI configuration space.
549 * It supports both type 0 and type 1 of Configuration Transactions
550 * (local and over bridge). In order to read from local bus segment, use
551 * bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers
552 * will result configuration transaction of type 1 (over bridge).
553 *
554 * INPUT:
555 * pciIf - PCI interface number.
556 * bus - PCI segment bus number.
557 * dev - PCI device number.
558 * func - Function number.
559 * regOffs - Register offset.
560 *
561 * OUTPUT:
562 * None.
563 *
564 * RETURN:
565 * 32bit register data, 0xffffffff on error
566 *
567 *******************************************************************************/
568 MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
569 MV_U32 regOff)
570 {
571 MV_U32 pciData = 0;
572
573 /* Parameter checking */
574 if (PCI_DEFAULT_IF != pciIf)
575 {
576 if (pciIf >= mvCtrlPciMaxIfGet())
577 {
578 mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf);
579 return 0xFFFFFFFF;
580 }
581 }
582
583 if (dev >= MAX_PCI_DEVICES)
584 {
585 DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev));
586 return 0xFFFFFFFF;
587 }
588
589 if (func >= MAX_PCI_FUNCS)
590 {
591 DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func));
592 return 0xFFFFFFFF;
593 }
594
595 if (bus >= MAX_PCI_BUSSES)
596 {
597 DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus));
598 return MV_ERROR;
599 }
600
601
602 /* Creating PCI address to be passed */
603 pciData |= (bus << PCAR_BUS_NUM_OFFS);
604 pciData |= (dev << PCAR_DEVICE_NUM_OFFS);
605 pciData |= (func << PCAR_FUNC_NUM_OFFS);
606 pciData |= (regOff & PCAR_REG_NUM_MASK);
607
608 pciData |= PCAR_CONFIG_EN;
609
610 /* Write the address to the PCI configuration address register */
611 MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData);
612
613 /* In order to let the PCI controller absorbed the address of the read */
614 /* transaction we perform a validity check that the address was written */
615 if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf)))
616 {
617 return MV_ERROR;
618 }
619 /* Read the Data returned in the PCI Data register */
620 pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf));
621
622 return pciData;
623 }
624
625 /*******************************************************************************
626 * mvPciConfigWrite - Write to configuration space
627 *
628 * DESCRIPTION:
629 * This function performs a 32 bit write to PCI configuration space.
630 * It supports both type 0 and type 1 of Configuration Transactions
631 * (local and over bridge). In order to write to local bus segment, use
632 * bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers
633 * will result configuration transaction of type 1 (over bridge).
634 *
635 * INPUT:
636 * pciIf - PCI interface number.
637 * bus - PCI segment bus number.
638 * dev - PCI device number.
639 * func - Function number.
640 * regOffs - Register offset.
641 * data - 32bit data.
642 *
643 * OUTPUT:
644 * None.
645 *
646 * RETURN:
647 * MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
648 *
649 *******************************************************************************/
650 MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,
651 MV_U32 func, MV_U32 regOff, MV_U32 data)
652 {
653 MV_U32 pciData = 0;
654
655 /* Parameter checking */
656 if (PCI_DEFAULT_IF != pciIf)
657 {
658 if (pciIf >= mvCtrlPciMaxIfGet())
659 {
660 mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n",
661 pciIf);
662 return 0xFFFFFFFF;
663 }
664 }
665
666 if (dev >= MAX_PCI_DEVICES)
667 {
668 mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev);
669 return MV_BAD_PARAM;
670 }
671
672 if (func >= MAX_PCI_FUNCS)
673 {
674 mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func);
675 return MV_ERROR;
676 }
677
678 if (bus >= MAX_PCI_BUSSES)
679 {
680 mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus);
681 return MV_ERROR;
682 }
683
684 /* Creating PCI address to be passed */
685 pciData |= (bus << PCAR_BUS_NUM_OFFS);
686 pciData |= (dev << PCAR_DEVICE_NUM_OFFS);
687 pciData |= (func << PCAR_FUNC_NUM_OFFS);
688 pciData |= (regOff & PCAR_REG_NUM_MASK);
689
690 pciData |= PCAR_CONFIG_EN;
691
692 /* Write the address to the PCI configuration address register */
693 MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData);
694
695 /* In order to let the PCI controller absorbed the address of the read */
696 /* transaction we perform a validity check that the address was written */
697 if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf)))
698 {
699 return MV_ERROR;
700 }
701
702 /* Write the Data passed to the PCI Data register */
703 MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data);
704
705 return MV_OK;
706 }
707
708 /*******************************************************************************
709 * mvPciMasterEnable - Enable/disale PCI interface master transactions.
710 *
711 * DESCRIPTION:
712 * This function performs read modified write to PCI command status
713 * (offset 0x4) to set/reset bit 2. After this bit is set, the PCI
714 * master is allowed to gain ownership on the bus, otherwise it is
715 * incapable to do so.
716 *
717 * INPUT:
718 * pciIf - PCI interface number.
719 * enable - Enable/disable parameter.
720 *
721 * OUTPUT:
722 * None.
723 *
724 * RETURN:
725 * MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
726 *
727 *******************************************************************************/
728 MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable)
729 {
730 MV_U32 pciCommandStatus;
731 MV_U32 RegOffs;
732 MV_U32 localBus;
733 MV_U32 localDev;
734
735 /* Parameter checking */
736 if (pciIf >= mvCtrlPciMaxIfGet())
737 {
738 mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf);
739 return MV_ERROR;
740 }
741
742 localBus = mvPciLocalBusNumGet(pciIf);
743 localDev = mvPciLocalDevNumGet(pciIf);
744
745 RegOffs = PCI_STATUS_AND_COMMAND;
746
747 pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs);
748
749 if (MV_TRUE == enable)
750 {
751 pciCommandStatus |= PSCR_MASTER_EN;
752 }
753 else
754 {
755 pciCommandStatus &= ~PSCR_MASTER_EN;
756 }
757
758 mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus);
759
760 return MV_OK;
761 }
762
763
764 /*******************************************************************************
765 * mvPciSlaveEnable - Enable/disale PCI interface slave transactions.
766 *
767 * DESCRIPTION:
768 * This function performs read modified write to PCI command status
769 * (offset 0x4) to set/reset bit 0 and 1. After those bits are set,
770 * the PCI slave is allowed to respond to PCI IO space access (bit 0)
771 * and PCI memory space access (bit 1).
772 *
773 * INPUT:
774 * pciIf - PCI interface number.
775 * dev - PCI device number.
776 * enable - Enable/disable parameter.
777 *
778 * OUTPUT:
779 * None.
780 *
781 * RETURN:
782 * MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK
783 *
784 *******************************************************************************/
785 MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable)
786 {
787 MV_U32 pciCommandStatus;
788 MV_U32 RegOffs;
789
790 /* Parameter checking */
791 if (pciIf >= mvCtrlPciMaxIfGet())
792 {
793 mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf);
794 return MV_BAD_PARAM;
795 }
796 if (dev >= MAX_PCI_DEVICES)
797 {
798 mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev);
799 return MV_BAD_PARAM;
800
801 }
802
803 RegOffs = PCI_STATUS_AND_COMMAND;
804
805 pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs);
806
807 if (MV_TRUE == enable)
808 {
809 pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN);
810 }
811 else
812 {
813 pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN);
814 }
815
816 mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus);
817
818 return MV_OK;
819 }
820
821 /*******************************************************************************
822 * mvPciLocalBusNumSet - Set PCI interface local bus number.
823 *
824 * DESCRIPTION:
825 * This function sets given PCI interface its local bus number.
826 * Note: In case the PCI interface is PCI-X, the information is read-only.
827 *
828 * INPUT:
829 * pciIf - PCI interface number.
830 * busNum - Bus number.
831 *
832 * OUTPUT:
833 * None.
834 *
835 * RETURN:
836 * MV_NOT_ALLOWED in case PCI interface is PCI-X.
837 * MV_BAD_PARAM on bad parameters ,
838 * otherwise MV_OK
839 *
840 *******************************************************************************/
841 MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum)
842 {
843 MV_U32 pciP2PConfig;
844 MV_PCI_MODE pciMode;
845 MV_U32 localBus;
846 MV_U32 localDev;
847
848
849 /* Parameter checking */
850 if (pciIf >= mvCtrlPciMaxIfGet())
851 {
852 mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf);
853 return MV_BAD_PARAM;
854 }
855 if (busNum >= MAX_PCI_BUSSES)
856 {
857 mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum);
858 return MV_ERROR;
859
860 }
861
862 localBus = mvPciLocalBusNumGet(pciIf);
863 localDev = mvPciLocalDevNumGet(pciIf);
864
865
866 /* PCI interface mode */
867 mvPciModeGet(pciIf, &pciMode);
868
869 /* if PCI type is PCI-X then it is not allowed to change the dev number */
870 if (MV_PCIX == pciMode.pciType)
871 {
872 pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS );
873
874 pciP2PConfig &= ~PXS_BN_MASK;
875
876 pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK;
877
878 mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig );
879
880 }
881 else
882 {
883 pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf));
884
885 pciP2PConfig &= ~PPCR_BUS_NUM_MASK;
886
887 pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK;
888
889 MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig);
890
891 }
892
893
894 return MV_OK;
895 }
896
897
898 /*******************************************************************************
899 * mvPciLocalBusNumGet - Get PCI interface local bus number.
900 *
901 * DESCRIPTION:
902 * This function gets the local bus number of a given PCI interface.
903 *
904 * INPUT:
905 * pciIf - PCI interface number.
906 *
907 * OUTPUT:
908 * None.
909 *
910 * RETURN:
911 * Local bus number.0xffffffff on Error
912 *
913 *******************************************************************************/
914 MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf)
915 {
916 MV_U32 pciP2PConfig;
917
918 /* Parameter checking */
919 if (PCI_DEFAULT_IF != pciIf)
920 {
921 if (pciIf >= mvCtrlPciMaxIfGet())
922 {
923 mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n",
924 pciIf);
925 return 0xFFFFFFFF;
926 }
927 }
928
929 pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf));
930 pciP2PConfig &= PPCR_BUS_NUM_MASK;
931 return (pciP2PConfig >> PPCR_BUS_NUM_OFFS);
932 }
933
934
935 /*******************************************************************************
936 * mvPciLocalDevNumSet - Set PCI interface local device number.
937 *
938 * DESCRIPTION:
939 * This function sets given PCI interface its local device number.
940 * Note: In case the PCI interface is PCI-X, the information is read-only.
941 *
942 * INPUT:
943 * pciIf - PCI interface number.
944 * devNum - Device number.
945 *
946 * OUTPUT:
947 * None.
948 *
949 * RETURN:
950 * MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters ,
951 * otherwise MV_OK
952 *
953 *******************************************************************************/
954 MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum)
955 {
956 MV_U32 pciP2PConfig;
957 MV_PCI_MODE pciMode;
958 MV_U32 localBus;
959 MV_U32 localDev;
960
961 /* Parameter checking */
962 if (pciIf >= mvCtrlPciMaxIfGet())
963 {
964 mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf);
965 return MV_BAD_PARAM;
966 }
967 if (devNum >= MAX_PCI_DEVICES)
968 {
969 mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n",
970 devNum);
971 return MV_BAD_PARAM;
972
973 }
974
975 localBus = mvPciLocalBusNumGet(pciIf);
976 localDev = mvPciLocalDevNumGet(pciIf);
977
978 /* PCI interface mode */
979 mvPciModeGet(pciIf, &pciMode);
980
981 /* if PCI type is PCIX then it is not allowed to change the dev number */
982 if (MV_PCIX == pciMode.pciType)
983 {
984 pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS );
985
986 pciP2PConfig &= ~PXS_DN_MASK;
987
988 pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK;
989
990 mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig );
991 }
992 else
993 {
994 pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf));
995
996 pciP2PConfig &= ~PPCR_DEV_NUM_MASK;
997
998 pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK;
999
1000 MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig);
1001 }
1002
1003 return MV_OK;
1004 }
1005
1006 /*******************************************************************************
1007 * mvPciLocalDevNumGet - Get PCI interface local device number.
1008 *
1009 * DESCRIPTION:
1010 * This function gets the local device number of a given PCI interface.
1011 *
1012 * INPUT:
1013 * pciIf - PCI interface number.
1014 *
1015 * OUTPUT:
1016 * None.
1017 *
1018 * RETURN:
1019 * Local device number. 0xffffffff on Error
1020 *
1021 *******************************************************************************/
1022 MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf)
1023 {
1024 MV_U32 pciP2PConfig;
1025
1026 /* Parameter checking */
1027
1028 if (PCI_DEFAULT_IF != pciIf)
1029 {
1030 if (pciIf >= mvCtrlPciMaxIfGet())
1031 {
1032 mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n",
1033 pciIf);
1034 return 0xFFFFFFFF;
1035 }
1036 }
1037
1038 pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf));
1039
1040 pciP2PConfig &= PPCR_DEV_NUM_MASK;
1041
1042 return (pciP2PConfig >> PPCR_DEV_NUM_OFFS);
1043 }
1044
1045
1046
1047
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