1 /*******************************************************************************
2 Copyright (C) Marvell International Ltd. and its affiliates
4 This software file (the "File") is owned and distributed by Marvell
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10 Marvell copyright notice above.
12 ********************************************************************************
13 Marvell Commercial License Option
15 If you received this File from Marvell and you have entered into a commercial
16 license agreement (a "Commercial License") with Marvell, the File is licensed
17 to you under the terms of the applicable Commercial License.
19 ********************************************************************************
20 Marvell GPL License Option
22 If you received this File from Marvell, you may opt to use, redistribute and/or
23 modify this File in accordance with the terms and conditions of the General
24 Public License Version 2, June 1991 (the "GPL License"), a copy of which is
25 available along with the File in the license.txt file or by writing to the Free
26 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
27 on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
29 THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
30 WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
31 DISCLAIMED. The GPL License provides additional details about this warranty
33 ********************************************************************************
34 Marvell BSD License Option
36 If you received this File from Marvell, you may opt to use, redistribute and/or
37 modify this File under the following licensing terms.
38 Redistribution and use in source and binary forms, with or without modification,
39 are permitted provided that the following conditions are met:
41 * Redistributions of source code must retain the above copyright notice,
42 this list of conditions and the following disclaimer.
44 * Redistributions in binary form must reproduce the above copyright
45 notice, this list of conditions and the following disclaimer in the
46 documentation and/or other materials provided with the distribution.
48 * Neither the name of Marvell nor the names of its contributors may be
49 used to endorse or promote products derived from this software without
50 specific prior written permission.
52 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
53 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
54 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
55 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
56 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
58 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
59 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
61 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *******************************************************************************/
66 #define MV_ASMLANGUAGE
67 #include "mvSysHwConfig.h"
69 #include "boardEnv/mvBoardEnvSpec.h"
70 #include "ctrlEnv/sys/mvCpuIfRegs.h"
71 #include "mvDramIfConfig.h"
72 #include "mvDramIfRegs.h"
73 #include "pex/mvPexRegs.h"
74 #include "ctrlEnv/mvCtrlEnvSpec.h"
75 #include "ctrlEnv/mvCtrlEnvAsm.h"
80 #if defined(MV_STATIC_DRAM_ON_BOARD)
85 /******************************************************************************
90 *******************************************************************************/
91 #if defined(DB_MV78XX0) || defined(DB_MV88F632X)
92 /* DDR2 boards 512MB 333MHz */
93 #define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
94 #define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */
95 #define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
96 #define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
97 #define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */
98 #define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */
99 #define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */
100 #define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */
101 #define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
102 #define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
103 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */
104 #define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
105 #define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
106 #define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
108 #elif defined(RD_MV78XX0_AMC)
109 /* On board DDR2 512MB 400MHz CL5 */
110 #define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
111 #define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */
112 #define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
113 #define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
114 #define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
115 #define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */
116 #define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */
117 #define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */
118 #define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
119 #define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
120 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
121 #define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
122 #define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
123 #define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
125 #elif defined(RD_MV78XX0_H3C)
126 /* DDR2 boards 512MB 333MHz */
127 #define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
128 #define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */
129 #define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
130 #define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
131 #define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
132 #define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */
133 #define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */
134 #define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */
135 #define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
136 #define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
137 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
138 #define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
139 #define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
140 #define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
142 #elif defined(RD_MV78XX0_PCAC)
143 /* DDR2 boards 256MB 200MHz */
144 #define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */
145 #define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */
146 #define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
147 #define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
148 #define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
149 #define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */
150 #define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */
151 #define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */
152 #define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
153 #define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
154 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
155 #define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
156 #define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
157 #define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
160 /* DDR2 MV88F6281 boards 256MB 400MHz */
161 #define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */
162 #define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */
163 #define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */
164 #define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */
165 #define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */
166 #define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */
167 #define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */
168 #define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */
169 #define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */
170 #define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
171 #define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */
172 #define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */
173 #define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
174 #define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
177 .globl _mvDramIfStaticInit
180 mov r11, LR /* Save link register */
184 MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
185 orr r6, r6, #BIT4 /* Enable 2T mode */
186 bic r6, r6, #BIT6 /* clear ctrlPos */
187 MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
190 /*DDR SDRAM Initialization Control */
191 ldr r6, =DSICR_INIT_EN
192 MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
193 2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
194 and r6, r6, #DSICR_INIT_EN
198 /* If we boot from NAND jump to DRAM address */
201 str r5, [r6] /* We started executing from DRAM */
207 /* set all dram windows to 0 */
209 MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
210 MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1))
211 MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2))
212 MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3))
213 ldr r6, = STATIC_SDRAM0_BANK0_SIZE
214 MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
217 /* set all dram configuration in temp registers */
218 ldr r6, = STATIC_SDRAM0_BANK0_SIZE
219 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
220 ldr r6, = STATIC_SDRAM_CONFIG
221 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
222 ldr r6, = STATIC_SDRAM_MODE
223 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
224 ldr r6, = STATIC_DUNIT_CTRL_LOW
225 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
226 ldr r6, = STATIC_SDRAM_ADDR_CTRL
227 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
228 ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW
229 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
230 ldr r6, = STATIC_SDRAM_TIME_CTRL_HI
231 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
232 ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW
233 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
234 ldr r6, = STATIC_SDRAM_ODT_CTRL_HI
235 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
236 ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
237 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
238 ldr r6, = STATIC_SDRAM_EXT_MODE
239 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
240 ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO
241 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11)
242 ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI
243 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12)
245 ldr r6, = STATIC_DUNIT_CTRL_HI
246 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13)
253 bl _mvDramIfEccMemInit
257 mov PC, r11 /* r11 is saved link register */
259 #else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */
265 /*******************************************************************************
266 * mvDramIfBasicInit - Basic initialization of DRAM interface
269 * The function will initialize the DRAM for basic usage. The function
270 * will use the TWSI assembly API to extract DIMM parameters according
271 * to which DRAM interface will be initialized.
272 * The function referes to the following DRAM parameters:
273 * 1) DIMM is registered or not.
274 * 2) DIMM width detection.
278 * r3 - required size for initial DRAM.
287 * r4 holds I2C EEPROM address
288 * r5 holds SDRAM register base address
289 * r7 holds returned values
290 * r8 holds SDRAM various configuration registers value.
291 * r11 holds return function address.
292 *******************************************************************************/
293 /* Setting the offsets of the I2C registers */
294 #define DIMM_TYPE_OFFSET 2
295 #define NUM_OF_ROWS_OFFSET 3
296 #define NUM_OF_COLS_OFFSET 4
297 #define NUM_OF_RANKS 5
298 #define DIMM_CONFIG_TYPE 11
299 #define SDRAM_WIDTH_OFFSET 13
300 #define NUM_OF_BANKS_OFFSET 17
301 #define SUPPORTED_CL_OFFSET 18
302 #define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */
303 #define SDRAM_MODULES_ATTR_OFFSET 21
304 #define RANK_SIZE_OFFSET 31
306 #define DRAM_DEV_DENSITY_128M 128
307 #define DRAM_DEV_DENSITY_256M 256
308 #define DRAM_DEV_DENSITY_512M 512
309 #define DRAM_DEV_DENSITY_1G 1024
310 #define DRAM_DEV_DENSITY_2G 2048
312 #define DRAM_RANK_DENSITY_128M 0x20
313 #define DRAM_RANK_DENSITY_256M 0x40
314 #define DRAM_RANK_DENSITY_512M 0x80
315 #define DRAM_RANK_DENSITY_1G 0x1
316 #define DRAM_RANK_DENSITY_2G 0x2
318 .globl _mvDramIfBasicInit
322 mov r11, LR /* Save link register */
324 /* Set Dunit high control register */
325 MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
326 orr r6, r6, #BIT7 /* SDRAM__D2P_EN */
327 orr r6, r6, #BIT8 /* SDRAM__P2D_EN */
329 orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
330 orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
331 orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
333 MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
336 MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
337 orr r6, r6, #BIT4 /* Enable 2T mode */
338 bic r6, r6, #BIT6 /* clear ctrlPos */
339 MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
342 /*DDR SDRAM Initialization Control */
343 ldr r6, =DSICR_INIT_EN
344 MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
345 2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
346 and r6, r6, #DSICR_INIT_EN
352 str r5, [r8] /* We started executing from DRAM */
354 /* If we boot from NAND jump to DRAM address */
359 bl _i2cInit /* Initialize TWSI master */
361 /* Check if we have more then 1 dimm */
363 MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
365 bl _is_Second_Dimm_Exist
368 MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
370 bl _i2cInit /* Initialize TWSI master */
373 /* Get default SDRAM Config values */
374 MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
376 /* Get registered/non registered info from DIMM */
381 orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */
384 /* Get ECC/non ECC info from DIMM */
389 orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */
392 MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1)
394 /* Set maximum CL supported by DIMM */
397 /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */
399 rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */
402 ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */
403 ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/
404 ldr r8, =0x32 /* Assuming MAX CL = 3 */
405 cmp r6, #3 /* If CL = 3 break */
408 ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */
409 ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/
410 ldr r8, =0x42 /* Assuming MAX CL = 4 */
411 cmp r6, #4 /* If CL = 4 break */
414 ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */
415 ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/
416 ldr r8, =0x52 /* Assuming MAX CL = 5 */
417 cmp r6, #5 /* If CL = 5 break */
420 ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */
421 ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/
422 ldr r8, =0x62 /* Assuming MAX CL = 6 */
423 cmp r6, #6 /* If CL = 5 break */
426 /* This is an error. return */
427 b exit_ddrAutoConfig /* This is an error !! */
430 /* Get default SDRAM Mode values */
431 MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG)
432 bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */
434 MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2)
436 /* Set Dunit control register according to max CL detected */
437 MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1)
438 tst r6, #SDRAM_REGISTERED
444 /* Set SDRAM Extended Mode register for double DIMM */
445 /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
447 MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
448 ldr r5, =MSAR_SYSCLCK_MASK
450 ldr r5, =MSAR_SYSCLCK_333
457 MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
458 bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */
459 orr r6, r6, #BIT4 /* Enable 2T mode */
460 bic r6, r6, #BIT6 /* clear ctrlPos */
461 orr r6, r6, r7, LSL #20
462 MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3)
464 /* Set Dunit high control register */
465 MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
466 orr r6, r6, #BIT7 /* SDRAM__D2P_EN */
467 orr r6, r6, #BIT8 /* SDRAM__P2D_EN */
469 orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
470 orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
471 orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
473 MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13)
475 /* DIMM density configuration*/
476 /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */
478 /* Get bank 0 and 1 density */
483 mov r8, r8, LSR #20 /* Move density 20 bits to the right */
484 /* For example 0x10000000 --> 0x1000 */
486 mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1))
487 cmp r8, #DRAM_DEV_DENSITY_256M
488 beq get_bank_2_density
490 mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1))
491 cmp r8, #DRAM_DEV_DENSITY_512M
492 beq get_bank_2_density
494 mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1))
495 cmp r8, #DRAM_DEV_DENSITY_1G
496 beq get_bank_2_density
498 mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1))
499 cmp r8, #DRAM_DEV_DENSITY_2G
500 beq get_bank_2_density
502 /* This is an error. return */
506 /* Check for second dimm */
507 MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
511 /* Get bank 2 and 3 density */
516 mov r8, r8, LSR #20 /* Move density 20 bits to the right */
517 /* For example 0x10000000 --> 0x1000 */
519 orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3))
520 cmp r8, #DRAM_DEV_DENSITY_256M
523 and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
524 orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3))
525 cmp r8, #DRAM_DEV_DENSITY_512M
528 and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
529 orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3))
530 cmp r8, #DRAM_DEV_DENSITY_1G
533 and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
534 orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3))
535 cmp r8, #DRAM_DEV_DENSITY_2G
538 /* This is an error. return */
541 /* Get SDRAM width */
543 /* Get bank 0 and 1 width */
547 cmp r7, #8 /* x8 devices */
550 orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */
554 /* This is an error. return */
558 /* Check for second dimm */
559 MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
563 /* Get bank 2 and 3 width */
567 cmp r7, #8 /* x8 devices */
570 orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */
574 /* This is an error. return */
578 MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4)
580 /* Set SDRAM timing control low register */
581 ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT
582 /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */
583 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5)
585 /* Set SDRAM timing control high register */
586 ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT
588 MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
589 ldr r5, =MSAR_SYSCLCK_MASK
591 ldr r5, =MSAR_SYSCLCK_333
593 blt timingHighClock333
597 /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */
598 MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
600 /* Check for second dimm */
601 MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
605 /* Set SDRAM ODT control low register for double DIMM*/
606 ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV
607 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
609 /* Set DUNIT ODT control register for double DIMM */
610 ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV
611 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
614 /* Set SDRAM Extended Mode register for double DIMM */
615 /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
617 MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
618 ldr r5, =MSAR_SYSCLCK_MASK
620 ldr r5, =MSAR_SYSCLCK_267
622 beq slow_dram_clock_rtt
623 ldr r5, =MSAR_SYSCLCK_300
625 beq slow_dram_clock_rtt
626 ldr r5, =MSAR_SYSCLCK_333
628 beq fast_dram_clock_rtt
629 ldr r5, =MSAR_SYSCLCK_400
631 beq fast_dram_clock_rtt
633 b slow_dram_clock_rtt
636 ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV
637 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
641 ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV
642 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
646 /* Set SDRAM ODT control low register */
647 ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV
648 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
650 /* Set DUNIT ODT control register */
651 ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV
652 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
654 /* Set SDRAM Extended Mode register */
655 ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV
656 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
659 /* SDRAM ODT control high register is left as default */
660 MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
661 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8)
663 /*Read CL and set the DDR2 registers accordingly */
664 MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2)
665 and r6, r6, #SDRAM_CL_MASK
667 orr r4, r4, r6, LSL #4
668 orr r4, r4, r6, LSL #8
669 orr r4, r4, r6, LSL #12
673 /* Set SDRAM Ddr2 Timing Low register */
674 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11)
676 /* Set SDRAM Ddr2 Timing High register */
678 MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12)
681 /* Close all windows */
682 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
683 and r6, r6,#~SCSR_SIZE_MASK
685 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
686 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
687 and r6, r6,#~SCSR_SIZE_MASK
689 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
690 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
691 and r6, r6,#~SCSR_SIZE_MASK
693 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
694 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
695 and r6, r6,#~SCSR_SIZE_MASK
697 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
699 /* Set sdram bank 0 size and enable it */
701 bl _mvDramIfGetDimmSizeFromSpd
703 /* Check DRAM width */
704 MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
705 ldr r5, =SDRAM_DWIDTH_MASK
707 ldr r5, =SDRAM_DWIDTH_64BIT
710 /* Utilize only 32bit width */
713 /* Utilize only 16bit width */
717 /* Update first dimm size return value R8 */
718 MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0))
719 ldr r6, =~SCSR_SIZE_MASK
722 MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0))
724 /* Clear bank 2 size */
725 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
726 and r6, r6,#~SCSR_SIZE_MASK
727 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
729 /* Check for second dimm */
730 MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
734 /* Set sdram bank 2 size */
736 bl _mvDramIfGetDimmSizeFromSpd
738 /* Check DRAM width */
739 MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
740 ldr r5, =SDRAM_DWIDTH_MASK
742 ldr r5, =SDRAM_DWIDTH_64BIT
744 beq dram_64bit_width2
745 /* Utilize only 32bit width */
748 /* Utilize only 16bit width */
752 /* Update first dimm size return value R8 */
753 MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2))
754 ldr r6, =~SCSR_SIZE_MASK
757 MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2))
759 /* Close windows 1 and 3 */
760 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
762 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
763 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
765 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
767 /* Check dimm size for setting dram bank order */
768 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
769 MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2))
770 and r6, r6,#SCSR_SIZE_MASK
771 and r4, r4,#SCSR_SIZE_MASK
775 /* Bank 2 is biger then bank 0 */
777 MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2))
780 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
782 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
787 /* Init ECC on CS 2 */
789 bl _mvDramIfEccMemInit
791 mov PC, r11 /* r11 is saved link register */
796 MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
798 MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
803 /* Init ECC on CS 0 */
805 bl _mvDramIfEccMemInit
808 mov PC, r11 /* r11 is saved link register */
811 /***************************************************************************************/
812 /* r4 holds I2C EEPROM address
813 * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
814 * r8 holds SDRAM various configuration registers value.
815 * r13 holds Link register
817 /**************************/
819 mov r13, LR /* Save link register */
821 /* Read SPD rank size from DIMM0 */
822 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
827 /* Read SPD rank size from DIMM1 */
828 mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
831 mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
833 mov r8, r7 /* r8 save number of rows */
835 mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
837 add r8, r8, r7 /* r8 = number of rows + number of col */
840 mov r8, r7, LSL r8 /* r8 = (1 << r8) */
842 mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
846 mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
852 /**************************/
854 mov r13, LR /* Save link register */
856 /* Read SPD rank size from DIMM0 */
857 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
862 /* Read SPD rank size from DIMM1 */
863 mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
866 /* Get SDRAM width (SPD offset 13) */
867 mov r7, #SDRAM_WIDTH_OFFSET
868 bl _i2cRead /* result in r7 */
872 /**************************/
874 mov r13, LR /* Save link register */
876 /* Set maximum CL supported by DIMM */
877 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
878 mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
883 /**************************/
884 /* R8 - sdram configuration register.
885 * Return value in flag if no-registered then Z-flag is set
888 mov r13, LR /* Save link register */
890 /* Get registered/non registered info from DIMM */
891 tst r8, #SDRAM_DTYPE_DDR2
895 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
896 mov r7, #SDRAM_MODULES_ATTR_OFFSET
897 bl _i2cRead /* result in r7 */
903 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
904 mov r7, #DIMM_TYPE_INFO_OFFSET
905 bl _i2cRead /* result in r7 */
907 tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */
908 /* or Mini-RDIMM (0x10) */
913 /**************************/
914 /* Return value in flag if no-Ecc then Z-flag is set */
916 mov r13, LR /* Save link register */
918 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
919 mov r7, #DIMM_CONFIG_TYPE
920 bl _i2cRead /* result in r7 */
922 tst r7, #0x2 /* bit 1 -> Data ECC */
925 /**************************/
926 /* Return value in flag if no second DIMM then Z-flag is set */
927 _is_Second_Dimm_Exist:
928 mov r13, LR /* Save link register */
930 mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */
931 mov r7, #DIMM_TYPE_OFFSET
932 bl _i2cRead /* result in r7 */
934 tst r7, #0x8 /* bit3 is '1' -> DDR 2 */
937 /*******************************************************************************
938 * _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size
941 * The function will read the bank 0 dram size(SPD version 1.0 and above )
944 * r6 - dram bank number.
949 _mvDramIfGetDimmSizeFromSpd:
951 mov r13, LR /* Save link register */
953 /* Read SPD rank size from DIMM0 */
954 mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
959 /* Read SPD rank size from DIMM1 */
960 mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
963 mov r7, #RANK_SIZE_OFFSET /* offset 31 */
967 ldr r8, =(0x7 << SCSR_SIZE_OFFS)
968 cmp r7, #DRAM_RANK_DENSITY_128M
971 ldr r8, =(0xf << SCSR_SIZE_OFFS)
972 cmp r7, #DRAM_RANK_DENSITY_256M
975 ldr r8, =(0x1f << SCSR_SIZE_OFFS)
976 cmp r7, #DRAM_RANK_DENSITY_512M
979 ldr r8, =(0x3f << SCSR_SIZE_OFFS)
980 cmp r7, #DRAM_RANK_DENSITY_1G
983 ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */