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kernel: backport upstream mediatek WED changes
[openwrt/openwrt.git] / target / linux / generic / backport-6.1 / 752-20-v6.7-net-ethernet-mtk_wed-add-wed-3.0-reset-support.patch
1 From: Sujuan Chen <sujuan.chen@mediatek.com>
2 Date: Mon, 18 Sep 2023 12:29:19 +0200
3 Subject: [PATCH] net: ethernet: mtk_wed: add wed 3.0 reset support
4
5 Introduce support for resetting Wireless Ethernet Dispatcher 3.0
6 available on MT988 SoC.
7
8 Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
9 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
10 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
11 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
12 ---
13
14 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
15 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
16 @@ -148,6 +148,90 @@ mtk_wdma_read_reset(struct mtk_wed_devic
17 return wdma_r32(dev, MTK_WDMA_GLO_CFG);
18 }
19
20 +static void
21 +mtk_wdma_v3_rx_reset(struct mtk_wed_device *dev)
22 +{
23 + u32 status;
24 +
25 + if (!mtk_wed_is_v3_or_greater(dev->hw))
26 + return;
27 +
28 + wdma_clr(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
29 + wdma_clr(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
30 +
31 + if (read_poll_timeout(wdma_r32, status,
32 + !(status & MTK_WDMA_PREF_TX_CFG_PREF_BUSY),
33 + 0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG))
34 + dev_err(dev->hw->dev, "rx reset failed\n");
35 +
36 + if (read_poll_timeout(wdma_r32, status,
37 + !(status & MTK_WDMA_PREF_RX_CFG_PREF_BUSY),
38 + 0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG))
39 + dev_err(dev->hw->dev, "rx reset failed\n");
40 +
41 + wdma_clr(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
42 + wdma_clr(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
43 +
44 + if (read_poll_timeout(wdma_r32, status,
45 + !(status & MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY),
46 + 0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG))
47 + dev_err(dev->hw->dev, "rx reset failed\n");
48 +
49 + if (read_poll_timeout(wdma_r32, status,
50 + !(status & MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY),
51 + 0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG))
52 + dev_err(dev->hw->dev, "rx reset failed\n");
53 +
54 + /* prefetch FIFO */
55 + wdma_w32(dev, MTK_WDMA_PREF_RX_FIFO_CFG,
56 + MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR |
57 + MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR);
58 + wdma_clr(dev, MTK_WDMA_PREF_RX_FIFO_CFG,
59 + MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR |
60 + MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR);
61 +
62 + /* core FIFO */
63 + wdma_w32(dev, MTK_WDMA_XDMA_RX_FIFO_CFG,
64 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR |
65 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR |
66 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR |
67 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR |
68 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR |
69 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR |
70 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR);
71 + wdma_clr(dev, MTK_WDMA_XDMA_RX_FIFO_CFG,
72 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR |
73 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR |
74 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR |
75 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR |
76 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR |
77 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR |
78 + MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR);
79 +
80 + /* writeback FIFO */
81 + wdma_w32(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0),
82 + MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
83 + wdma_w32(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(1),
84 + MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
85 +
86 + wdma_clr(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0),
87 + MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
88 + wdma_clr(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(1),
89 + MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
90 +
91 + /* prefetch ring status */
92 + wdma_w32(dev, MTK_WDMA_PREF_SIDX_CFG,
93 + MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR);
94 + wdma_clr(dev, MTK_WDMA_PREF_SIDX_CFG,
95 + MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR);
96 +
97 + /* writeback ring status */
98 + wdma_w32(dev, MTK_WDMA_WRBK_SIDX_CFG,
99 + MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR);
100 + wdma_clr(dev, MTK_WDMA_WRBK_SIDX_CFG,
101 + MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR);
102 +}
103 +
104 static int
105 mtk_wdma_rx_reset(struct mtk_wed_device *dev)
106 {
107 @@ -160,6 +244,7 @@ mtk_wdma_rx_reset(struct mtk_wed_device
108 if (ret)
109 dev_err(dev->hw->dev, "rx reset failed\n");
110
111 + mtk_wdma_v3_rx_reset(dev);
112 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
113 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
114
115 @@ -192,6 +277,84 @@ mtk_wed_poll_busy(struct mtk_wed_device
116 }
117
118 static void
119 +mtk_wdma_v3_tx_reset(struct mtk_wed_device *dev)
120 +{
121 + u32 status;
122 +
123 + if (!mtk_wed_is_v3_or_greater(dev->hw))
124 + return;
125 +
126 + wdma_clr(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
127 + wdma_clr(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
128 +
129 + if (read_poll_timeout(wdma_r32, status,
130 + !(status & MTK_WDMA_PREF_TX_CFG_PREF_BUSY),
131 + 0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG))
132 + dev_err(dev->hw->dev, "tx reset failed\n");
133 +
134 + if (read_poll_timeout(wdma_r32, status,
135 + !(status & MTK_WDMA_PREF_RX_CFG_PREF_BUSY),
136 + 0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG))
137 + dev_err(dev->hw->dev, "tx reset failed\n");
138 +
139 + wdma_clr(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
140 + wdma_clr(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
141 +
142 + if (read_poll_timeout(wdma_r32, status,
143 + !(status & MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY),
144 + 0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG))
145 + dev_err(dev->hw->dev, "tx reset failed\n");
146 +
147 + if (read_poll_timeout(wdma_r32, status,
148 + !(status & MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY),
149 + 0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG))
150 + dev_err(dev->hw->dev, "tx reset failed\n");
151 +
152 + /* prefetch FIFO */
153 + wdma_w32(dev, MTK_WDMA_PREF_TX_FIFO_CFG,
154 + MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR |
155 + MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR);
156 + wdma_clr(dev, MTK_WDMA_PREF_TX_FIFO_CFG,
157 + MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR |
158 + MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR);
159 +
160 + /* core FIFO */
161 + wdma_w32(dev, MTK_WDMA_XDMA_TX_FIFO_CFG,
162 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR |
163 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR |
164 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR |
165 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR);
166 + wdma_clr(dev, MTK_WDMA_XDMA_TX_FIFO_CFG,
167 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR |
168 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR |
169 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR |
170 + MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR);
171 +
172 + /* writeback FIFO */
173 + wdma_w32(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0),
174 + MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
175 + wdma_w32(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(1),
176 + MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
177 +
178 + wdma_clr(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0),
179 + MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
180 + wdma_clr(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(1),
181 + MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
182 +
183 + /* prefetch ring status */
184 + wdma_w32(dev, MTK_WDMA_PREF_SIDX_CFG,
185 + MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR);
186 + wdma_clr(dev, MTK_WDMA_PREF_SIDX_CFG,
187 + MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR);
188 +
189 + /* writeback ring status */
190 + wdma_w32(dev, MTK_WDMA_WRBK_SIDX_CFG,
191 + MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR);
192 + wdma_clr(dev, MTK_WDMA_WRBK_SIDX_CFG,
193 + MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR);
194 +}
195 +
196 +static void
197 mtk_wdma_tx_reset(struct mtk_wed_device *dev)
198 {
199 u32 status, mask = MTK_WDMA_GLO_CFG_TX_DMA_BUSY;
200 @@ -202,6 +365,7 @@ mtk_wdma_tx_reset(struct mtk_wed_device
201 !(status & mask), 0, 10000))
202 dev_err(dev->hw->dev, "tx reset failed\n");
203
204 + mtk_wdma_v3_tx_reset(dev);
205 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
206 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
207
208 @@ -1405,13 +1569,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
209 if (ret)
210 return ret;
211
212 + if (dev->wlan.hw_rro) {
213 + wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_IND_CMD_EN);
214 + mtk_wed_poll_busy(dev, MTK_WED_RRO_RX_HW_STS,
215 + MTK_WED_RX_IND_CMD_BUSY);
216 + mtk_wed_reset(dev, MTK_WED_RESET_RRO_RX_TO_PG);
217 + }
218 +
219 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RX_DRV_EN);
220 ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
221 MTK_WED_WPDMA_RX_D_RX_DRV_BUSY);
222 + if (!ret && mtk_wed_is_v3_or_greater(dev->hw))
223 + ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
224 + MTK_WED_WPDMA_RX_D_PREF_BUSY);
225 if (ret) {
226 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
227 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_D_DRV);
228 } else {
229 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
230 + /* 1.a. disable prefetch HW */
231 + wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
232 + MTK_WED_WPDMA_RX_D_PREF_EN);
233 + mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
234 + MTK_WED_WPDMA_RX_D_PREF_BUSY);
235 + wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
236 + MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL);
237 + }
238 +
239 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
240 MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
241 MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
242 @@ -1439,23 +1623,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
243 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
244 }
245
246 + if (dev->wlan.hw_rro) {
247 + /* disable rro msdu page drv */
248 + wed_clr(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
249 + MTK_WED_RRO_MSDU_PG_DRV_EN);
250 +
251 + /* disable rro data drv */
252 + wed_clr(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_RX_D_DRV_EN);
253 +
254 + /* rro msdu page drv reset */
255 + wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
256 + MTK_WED_RRO_MSDU_PG_DRV_CLR);
257 + mtk_wed_poll_busy(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
258 + MTK_WED_RRO_MSDU_PG_DRV_CLR);
259 +
260 + /* rro data drv reset */
261 + wed_w32(dev, MTK_WED_RRO_RX_D_CFG(2),
262 + MTK_WED_RRO_RX_D_DRV_CLR);
263 + mtk_wed_poll_busy(dev, MTK_WED_RRO_RX_D_CFG(2),
264 + MTK_WED_RRO_RX_D_DRV_CLR);
265 + }
266 +
267 /* reset route qm */
268 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
269 ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
270 MTK_WED_CTRL_RX_ROUTE_QM_BUSY);
271 - if (ret)
272 + if (ret) {
273 mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
274 - else
275 - wed_set(dev, MTK_WED_RTQM_GLO_CFG,
276 - MTK_WED_RTQM_Q_RST);
277 + } else if (mtk_wed_is_v3_or_greater(dev->hw)) {
278 + wed_set(dev, MTK_WED_RTQM_RST, BIT(0));
279 + wed_clr(dev, MTK_WED_RTQM_RST, BIT(0));
280 + mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
281 + } else {
282 + wed_set(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
283 + }
284
285 /* reset tx wdma */
286 mtk_wdma_tx_reset(dev);
287
288 /* reset tx wdma drv */
289 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_TX_DRV_EN);
290 - mtk_wed_poll_busy(dev, MTK_WED_CTRL,
291 - MTK_WED_CTRL_WDMA_INT_AGENT_BUSY);
292 + if (mtk_wed_is_v3_or_greater(dev->hw))
293 + mtk_wed_poll_busy(dev, MTK_WED_WPDMA_STATUS,
294 + MTK_WED_WPDMA_STATUS_TX_DRV);
295 + else
296 + mtk_wed_poll_busy(dev, MTK_WED_CTRL,
297 + MTK_WED_CTRL_WDMA_INT_AGENT_BUSY);
298 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
299
300 /* reset wed rx dma */
301 @@ -1476,6 +1689,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
302 MTK_WED_CTRL_WED_RX_BM_BUSY);
303 mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
304
305 + if (dev->wlan.hw_rro) {
306 + wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_PG_BM_EN);
307 + mtk_wed_poll_busy(dev, MTK_WED_CTRL,
308 + MTK_WED_CTRL_WED_RX_PG_BM_BUSY);
309 + wed_set(dev, MTK_WED_RESET, MTK_WED_RESET_RX_PG_BM);
310 + wed_clr(dev, MTK_WED_RESET, MTK_WED_RESET_RX_PG_BM);
311 + }
312 +
313 /* wo change to enable state */
314 val = MTK_WED_WO_STATE_ENABLE;
315 ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
316 @@ -1493,6 +1714,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
317 false);
318 }
319 mtk_wed_free_rx_buffer(dev);
320 + mtk_wed_hwrro_free_buffer(dev);
321
322 return 0;
323 }
324 @@ -1526,15 +1748,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
325
326 /* 2. reset WDMA rx DMA */
327 busy = !!mtk_wdma_rx_reset(dev);
328 - wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
329 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
330 + val = MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE |
331 + wed_r32(dev, MTK_WED_WDMA_GLO_CFG);
332 + val &= ~MTK_WED_WDMA_GLO_CFG_RX_DRV_EN;
333 + wed_w32(dev, MTK_WED_WDMA_GLO_CFG, val);
334 + } else {
335 + wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
336 + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
337 + }
338 +
339 if (!busy)
340 busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_GLO_CFG,
341 MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY);
342 + if (!busy && mtk_wed_is_v3_or_greater(dev->hw))
343 + busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_RX_PREF_CFG,
344 + MTK_WED_WDMA_RX_PREF_BUSY);
345
346 if (busy) {
347 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
348 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);
349 } else {
350 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
351 + /* 1.a. disable prefetch HW */
352 + wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
353 + MTK_WED_WDMA_RX_PREF_EN);
354 + mtk_wed_poll_busy(dev, MTK_WED_WDMA_RX_PREF_CFG,
355 + MTK_WED_WDMA_RX_PREF_BUSY);
356 + wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
357 + MTK_WED_WDMA_RX_PREF_DDONE2_EN);
358 +
359 + /* 2. Reset dma index */
360 + wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
361 + MTK_WED_WDMA_RESET_IDX_RX_ALL);
362 + }
363 +
364 wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
365 MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
366 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
367 @@ -1550,8 +1798,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
368 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
369
370 for (i = 0; i < 100; i++) {
371 - val = wed_r32(dev, MTK_WED_TX_BM_INTF);
372 - if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)
373 + if (mtk_wed_is_v1(dev->hw))
374 + val = FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP,
375 + wed_r32(dev, MTK_WED_TX_BM_INTF));
376 + else
377 + val = FIELD_GET(MTK_WED_TX_TKID_INTF_TKFIFO_FDEP,
378 + wed_r32(dev, MTK_WED_TX_TKID_INTF));
379 + if (val == 0x40)
380 break;
381 }
382
383 @@ -1573,6 +1826,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
384 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
385 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
386 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
387 + if (mtk_wed_is_v3_or_greater(dev->hw))
388 + wed_w32(dev, MTK_WED_RX1_CTRL2, 0);
389 } else {
390 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
391 MTK_WED_WPDMA_RESET_IDX_TX |
392 @@ -1589,7 +1844,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
393 wed_w32(dev, MTK_WED_RESET_IDX, 0);
394 }
395
396 - mtk_wed_rx_reset(dev);
397 + if (mtk_wed_is_v3_or_greater(dev->hw)) {
398 + /* reset amsdu engine */
399 + wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
400 + mtk_wed_reset(dev, MTK_WED_RESET_TX_AMSDU);
401 + }
402 +
403 + if (mtk_wed_get_rx_capa(dev))
404 + mtk_wed_rx_reset(dev);
405 }
406
407 static int
408 @@ -1841,6 +2103,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
409 MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
410
411 wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
412 + wdma_set(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
413 }
414
415 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
416 @@ -1904,6 +2167,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
417 if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
418 return;
419
420 + if (reset) {
421 + wed_set(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
422 + MTK_WED_RRO_MSDU_PG_DRV_EN);
423 + return;
424 + }
425 +
426 wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_MSDU_PG_DRV_CLR);
427 wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
428 MTK_WED_RRO_MSDU_PG_DRV_CLR);
429 --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
430 +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
431 @@ -28,6 +28,8 @@ struct mtk_wdma_desc {
432 #define MTK_WED_RESET 0x008
433 #define MTK_WED_RESET_TX_BM BIT(0)
434 #define MTK_WED_RESET_RX_BM BIT(1)
435 +#define MTK_WED_RESET_RX_PG_BM BIT(2)
436 +#define MTK_WED_RESET_RRO_RX_TO_PG BIT(3)
437 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
438 #define MTK_WED_RESET_WPDMA_TX_DRV BIT(8)
439 #define MTK_WED_RESET_WPDMA_RX_DRV BIT(9)
440 @@ -106,6 +108,9 @@ struct mtk_wdma_desc {
441 #define MTK_WED_STATUS 0x060
442 #define MTK_WED_STATUS_TX GENMASK(15, 8)
443
444 +#define MTK_WED_WPDMA_STATUS 0x068
445 +#define MTK_WED_WPDMA_STATUS_TX_DRV GENMASK(15, 8)
446 +
447 #define MTK_WED_TX_BM_CTRL 0x080
448 #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0)
449 #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)
450 @@ -140,6 +145,9 @@ struct mtk_wdma_desc {
451 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16)
452 #define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28)
453
454 +#define MTK_WED_TX_TKID_INTF 0x0dc
455 +#define MTK_WED_TX_TKID_INTF_TKFIFO_FDEP GENMASK(25, 16)
456 +
457 #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3 GENMASK(7, 0)
458 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3 GENMASK(23, 16)
459
460 @@ -190,6 +198,7 @@ struct mtk_wdma_desc {
461 #define MTK_WED_RING_RX_DATA(_n) (0x420 + (_n) * 0x10)
462
463 #define MTK_WED_SCR0 0x3c0
464 +#define MTK_WED_RX1_CTRL2 0x418
465 #define MTK_WED_WPDMA_INT_TRIGGER 0x504
466 #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1)
467 #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4)
468 @@ -303,6 +312,7 @@ struct mtk_wdma_desc {
469
470 #define MTK_WED_WPDMA_RX_D_RST_IDX 0x760
471 #define MTK_WED_WPDMA_RX_D_RST_CRX_IDX GENMASK(17, 16)
472 +#define MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL BIT(20)
473 #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX GENMASK(25, 24)
474
475 #define MTK_WED_WPDMA_RX_GLO_CFG 0x76c
476 @@ -313,6 +323,7 @@ struct mtk_wdma_desc {
477
478 #define MTK_WED_WPDMA_RX_D_PREF_CFG 0x7b4
479 #define MTK_WED_WPDMA_RX_D_PREF_EN BIT(0)
480 +#define MTK_WED_WPDMA_RX_D_PREF_BUSY BIT(1)
481 #define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE GENMASK(12, 8)
482 #define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES GENMASK(21, 16)
483
484 @@ -334,11 +345,13 @@ struct mtk_wdma_desc {
485
486 #define MTK_WED_WDMA_RX_PREF_CFG 0x950
487 #define MTK_WED_WDMA_RX_PREF_EN BIT(0)
488 +#define MTK_WED_WDMA_RX_PREF_BUSY BIT(1)
489 #define MTK_WED_WDMA_RX_PREF_BURST_SIZE GENMASK(12, 8)
490 #define MTK_WED_WDMA_RX_PREF_LOW_THRES GENMASK(21, 16)
491 #define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR BIT(24)
492 #define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR BIT(25)
493 #define MTK_WED_WDMA_RX_PREF_DDONE2_EN BIT(26)
494 +#define MTK_WED_WDMA_RX_PREF_DDONE2_BUSY BIT(27)
495
496 #define MTK_WED_WDMA_RX_PREF_FIFO_CFG 0x95C
497 #define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR BIT(0)
498 @@ -367,6 +380,7 @@ struct mtk_wdma_desc {
499
500 #define MTK_WED_WDMA_RESET_IDX 0xa08
501 #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16)
502 +#define MTK_WED_WDMA_RESET_IDX_RX_ALL BIT(20)
503 #define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24)
504
505 #define MTK_WED_WDMA_INT_CLR 0xa24
506 @@ -437,21 +451,62 @@ struct mtk_wdma_desc {
507 #define MTK_WDMA_INT_MASK_RX_DELAY BIT(30)
508 #define MTK_WDMA_INT_MASK_RX_COHERENT BIT(31)
509
510 +#define MTK_WDMA_XDMA_TX_FIFO_CFG 0x238
511 +#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR BIT(0)
512 +#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR BIT(4)
513 +#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR BIT(8)
514 +#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR BIT(12)
515 +
516 +#define MTK_WDMA_XDMA_RX_FIFO_CFG 0x23c
517 +#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR BIT(0)
518 +#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR BIT(4)
519 +#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR BIT(8)
520 +#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR BIT(12)
521 +#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR BIT(15)
522 +#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR BIT(18)
523 +#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR BIT(21)
524 +
525 #define MTK_WDMA_INT_GRP1 0x250
526 #define MTK_WDMA_INT_GRP2 0x254
527
528 #define MTK_WDMA_PREF_TX_CFG 0x2d0
529 #define MTK_WDMA_PREF_TX_CFG_PREF_EN BIT(0)
530 +#define MTK_WDMA_PREF_TX_CFG_PREF_BUSY BIT(1)
531
532 #define MTK_WDMA_PREF_RX_CFG 0x2dc
533 #define MTK_WDMA_PREF_RX_CFG_PREF_EN BIT(0)
534 +#define MTK_WDMA_PREF_RX_CFG_PREF_BUSY BIT(1)
535 +
536 +#define MTK_WDMA_PREF_RX_FIFO_CFG 0x2e0
537 +#define MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR BIT(0)
538 +#define MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR BIT(16)
539 +
540 +#define MTK_WDMA_PREF_TX_FIFO_CFG 0x2d4
541 +#define MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR BIT(0)
542 +#define MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR BIT(16)
543 +
544 +#define MTK_WDMA_PREF_SIDX_CFG 0x2e4
545 +#define MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0)
546 +#define MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4)
547
548 #define MTK_WDMA_WRBK_TX_CFG 0x300
549 +#define MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY BIT(0)
550 #define MTK_WDMA_WRBK_TX_CFG_WRBK_EN BIT(30)
551
552 +#define MTK_WDMA_WRBK_TX_FIFO_CFG(_n) (0x304 + (_n) * 0x4)
553 +#define MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR BIT(0)
554 +
555 #define MTK_WDMA_WRBK_RX_CFG 0x344
556 +#define MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY BIT(0)
557 #define MTK_WDMA_WRBK_RX_CFG_WRBK_EN BIT(30)
558
559 +#define MTK_WDMA_WRBK_RX_FIFO_CFG(_n) (0x348 + (_n) * 0x4)
560 +#define MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR BIT(0)
561 +
562 +#define MTK_WDMA_WRBK_SIDX_CFG 0x388
563 +#define MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0)
564 +#define MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR GENMASK(5, 4)
565 +
566 #define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0)
567 #define MTK_PCIE_MIRROR_MAP_EN BIT(0)
568 #define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1)
569 @@ -465,6 +520,8 @@ struct mtk_wdma_desc {
570 #define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5)
571 #define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20)
572
573 +#define MTK_WED_RTQM_RST 0xb04
574 +
575 #define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT 0xb1c
576 #define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n) (0xb20 + (_n) * 0x4)
577 #define MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT 0xb28
578 @@ -653,6 +710,9 @@ struct mtk_wdma_desc {
579 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR BIT(17)
580 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG GENMASK(22, 18)
581
582 +#define MTK_WED_RRO_RX_HW_STS 0xf00
583 +#define MTK_WED_RX_IND_CMD_BUSY GENMASK(31, 0)
584 +
585 #define MTK_WED_RX_IND_CMD_CNT0 0xf20
586 #define MTK_WED_RX_IND_CMD_DBG_CNT_EN BIT(31)
587
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