target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch

   1 From 15a84d1c44ae8c1451c265ee60500588a24e8cd6 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Tue, 22 Aug 2023 17:32:03 +0100
   4 Subject: [PATCH 111/250] net: ethernet: mtk_eth_soc: add reset bits for MT7988
   5
   6 Add bits needed to reset the frame engine on MT7988.
   7
   8 Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
   9 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  10 Link: https://lore.kernel.org/r/89b6c38380e7a3800c1362aa7575600717bc7543.1692721443.git.daniel@makrotopia.org
  11 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  12 ---
  13  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 76 +++++++++++++++------
  14  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 16 +++--
  15  2 files changed, 68 insertions(+), 24 deletions(-)
  16
  17 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  18 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  19 @@ -3593,19 +3593,34 @@ static void mtk_hw_reset(struct mtk_eth
  20  {
  21         u32 val;
  22
  23 -       if (mtk_is_netsys_v2_or_greater(eth)) {
  24 +       if (mtk_is_netsys_v2_or_greater(eth))
  25                 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
  26 +
  27 +       if (mtk_is_netsys_v3_or_greater(eth)) {
  28 +               val = RSTCTRL_PPE0_V3;
  29 +
  30 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  31 +                       val |= RSTCTRL_PPE1_V3;
  32 +
  33 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
  34 +                       val |= RSTCTRL_PPE2;
  35 +
  36 +               val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
  37 +       } else if (mtk_is_netsys_v2_or_greater(eth)) {
  38                 val = RSTCTRL_PPE0_V2;
  39 +
  40 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  41 +                       val |= RSTCTRL_PPE1;
  42         } else {
  43                 val = RSTCTRL_PPE0;
  44         }
  45
  46 -       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  47 -               val |= RSTCTRL_PPE1;
  48 -
  49         ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
  50
  51 -       if (mtk_is_netsys_v2_or_greater(eth))
  52 +       if (mtk_is_netsys_v3_or_greater(eth))
  53 +               regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  54 +                            0x6f8ff);
  55 +       else if (mtk_is_netsys_v2_or_greater(eth))
  56                 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  57                              0x3ffffff);
  58  }
  59 @@ -3631,13 +3646,21 @@ static void mtk_hw_warm_reset(struct mtk
  60                 return;
  61         }
  62
  63 -       if (mtk_is_netsys_v2_or_greater(eth))
  64 +       if (mtk_is_netsys_v3_or_greater(eth)) {
  65 +               rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
  66 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  67 +                       rst_mask |= RSTCTRL_PPE1_V3;
  68 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
  69 +                       rst_mask |= RSTCTRL_PPE2;
  70 +
  71 +               rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
  72 +       } else if (mtk_is_netsys_v2_or_greater(eth)) {
  73                 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
  74 -       else
  75 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  76 +                       rst_mask |= RSTCTRL_PPE1;
  77 +       } else {
  78                 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
  79 -
  80 -       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  81 -               rst_mask |= RSTCTRL_PPE1;
  82 +       }
  83
  84         regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
  85
  86 @@ -3989,11 +4012,17 @@ static void mtk_prepare_for_reset(struct
  87         u32 val;
  88         int i;
  89
  90 -       /* disabe FE P3 and P4 */
  91 -       val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3;
  92 -       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  93 -               val |= MTK_FE_LINK_DOWN_P4;
  94 -       mtk_w32(eth, val, MTK_FE_GLO_CFG);
  95 +       /* set FE PPE ports link down */
  96 +       for (i = MTK_GMAC1_ID;
  97 +            i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
  98 +            i += 2) {
  99 +               val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
 100 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
 101 +                       val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
 102 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
 103 +                       val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
 104 +               mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
 105 +       }
 106
 107         /* adjust PPE configurations to prepare for reset */
 108         for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
 109 @@ -4054,11 +4083,18 @@ static void mtk_pending_work(struct work
 110                 }
 111         }
 112
 113 -       /* enabe FE P3 and P4 */
 114 -       val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3;
 115 -       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
 116 -               val &= ~MTK_FE_LINK_DOWN_P4;
 117 -       mtk_w32(eth, val, MTK_FE_GLO_CFG);
 118 +       /* set FE PPE ports link up */
 119 +       for (i = MTK_GMAC1_ID;
 120 +            i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
 121 +            i += 2) {
 122 +               val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
 123 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
 124 +                       val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
 125 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
 126 +                       val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
 127 +
 128 +               mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
 129 +       }
 130
 131         clear_bit(MTK_RESETTING, &eth->state);
 132
 133 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 134 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 135 @@ -76,9 +76,8 @@
 136  #define        MTK_HW_LRO_SDL_REMAIN_ROOM      1522
 137
 138  /* Frame Engine Global Configuration */
 139 -#define MTK_FE_GLO_CFG         0x00
 140 -#define MTK_FE_LINK_DOWN_P3    BIT(11)
 141 -#define MTK_FE_LINK_DOWN_P4    BIT(12)
 142 +#define MTK_FE_GLO_CFG(x)      (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00)
 143 +#define MTK_FE_LINK_DOWN_P(x)  BIT(((x) + 8) % 16)
 144
 145  /* Frame Engine Global Reset Register */
 146  #define MTK_RST_GL             0x04
 147 @@ -522,9 +521,15 @@
 148  /* ethernet reset control register */
 149  #define ETHSYS_RSTCTRL                 0x34
 150  #define RSTCTRL_FE                     BIT(6)
 151 +#define RSTCTRL_WDMA0                  BIT(24)
 152 +#define RSTCTRL_WDMA1                  BIT(25)
 153 +#define RSTCTRL_WDMA2                  BIT(26)
 154  #define RSTCTRL_PPE0                   BIT(31)
 155  #define RSTCTRL_PPE0_V2                        BIT(30)
 156  #define RSTCTRL_PPE1                   BIT(31)
 157 +#define RSTCTRL_PPE0_V3                        BIT(29)
 158 +#define RSTCTRL_PPE1_V3                        BIT(30)
 159 +#define RSTCTRL_PPE2                   BIT(31)
 160  #define RSTCTRL_ETH                    BIT(23)
 161
 162  /* ethernet reset check idle register */
 163 @@ -931,6 +936,7 @@ enum mkt_eth_capabilities {
 164         MTK_QDMA_BIT,
 165         MTK_SOC_MT7628_BIT,
 166         MTK_RSTCTRL_PPE1_BIT,
 167 +       MTK_RSTCTRL_PPE2_BIT,
 168         MTK_U3_COPHY_V2_BIT,
 169
 170         /* MUX BITS*/
 171 @@ -965,6 +971,7 @@ enum mkt_eth_capabilities {
 172  #define MTK_QDMA               BIT_ULL(MTK_QDMA_BIT)
 173  #define MTK_SOC_MT7628         BIT_ULL(MTK_SOC_MT7628_BIT)
 174  #define MTK_RSTCTRL_PPE1       BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
 175 +#define MTK_RSTCTRL_PPE2       BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
 176  #define MTK_U3_COPHY_V2                BIT_ULL(MTK_U3_COPHY_V2_BIT)
 177
 178  #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW          \
 179 @@ -1047,7 +1054,8 @@ enum mkt_eth_capabilities {
 180                       MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
 181                       MTK_RSTCTRL_PPE1)
 182
 183 -#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1)
 184 +#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
 185 +                     MTK_RSTCTRL_PPE2)
 186
 187  struct mtk_tx_dma_desc_info {
 188         dma_addr_t      addr;