target/linux/generic/backport-6.1/733-v6.2-07-net-mtk_eth_soc-move-PHY-power-up.patch

   1 From 6f38fffe2179dd29612aea2c67c46ed6682b4e46 Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Thu, 27 Oct 2022 14:11:08 +0100
   4 Subject: [PATCH 06/10] net: mtk_eth_soc: move PHY power up
   5
   6 The PHY power up is common to both configuration paths, so move it into
   7 the parent function. We need to do this for all serdes modes.
   8
   9 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  10 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  11 ---
  12  drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 ++++-------
  13  1 file changed, 4 insertions(+), 7 deletions(-)
  14
  15 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  16 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  17 @@ -45,9 +45,6 @@ static void mtk_pcs_setup_mode_an(struct
  18
  19         regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
  20                            SGMII_AN_RESTART, SGMII_AN_RESTART);
  21 -
  22 -       regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
  23 -                          SGMII_PHYA_PWD, 0);
  24  }
  25
  26  /* For 1000BASE-X and 2500BASE-X interface modes, which operate at a
  27 @@ -72,10 +69,6 @@ static void mtk_pcs_setup_mode_force(str
  28         regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
  29                            SGMII_IF_MODE_MASK & ~SGMII_DUPLEX_FULL,
  30                            SGMII_SPEED_1000);
  31 -
  32 -       /* Release PHYA power down state */
  33 -       regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
  34 -                          SGMII_PHYA_PWD, 0);
  35  }
  36
  37  static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
  38 @@ -91,6 +84,10 @@ static int mtk_pcs_config(struct phylink
  39         else if (phylink_autoneg_inband(mode))
  40                 mtk_pcs_setup_mode_an(mpcs);
  41
  42 +       /* Release PHYA power down state */
  43 +       regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
  44 +                          SGMII_PHYA_PWD, 0);
  45 +
  46         return 0;
  47  }
  48