target/linux/generic/backport-6.1/729-01-v6.1-net-ethernet-mtk_wed-introduce-wed-mcu-support.patch

   1 From: Sujuan Chen <sujuan.chen@mediatek.com>
   2 Date: Sat, 5 Nov 2022 23:36:18 +0100
   3 Subject: [PATCH] net: ethernet: mtk_wed: introduce wed mcu support
   4
   5 Introduce WED mcu support used to configure WED WO chip.
   6 This is a preliminary patch in order to add RX Wireless
   7 Ethernet Dispatch available on MT7986 SoC.
   8
   9 Tested-by: Daniel Golle <daniel@makrotopia.org>
  10 Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
  11 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  12 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
  13 Signed-off-by: David S. Miller <davem@davemloft.net>
  14 ---
  15  create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_mcu.c
  16  create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.h
  17
  18 --- a/drivers/net/ethernet/mediatek/Makefile
  19 +++ b/drivers/net/ethernet/mediatek/Makefile
  20 @@ -5,7 +5,7 @@
  21
  22  obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
  23  mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
  24 -mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o
  25 +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o
  26  ifdef CONFIG_DEBUG_FS
  27  mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
  28  endif
  29 --- /dev/null
  30 +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
  31 @@ -0,0 +1,359 @@
  32 +// SPDX-License-Identifier: GPL-2.0-only
  33 +/* Copyright (C) 2022 MediaTek Inc.
  34 + *
  35 + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
  36 + *        Sujuan Chen <sujuan.chen@mediatek.com>
  37 + */
  38 +
  39 +#include <linux/firmware.h>
  40 +#include <linux/of_address.h>
  41 +#include <linux/of_reserved_mem.h>
  42 +#include <linux/mfd/syscon.h>
  43 +#include <linux/soc/mediatek/mtk_wed.h>
  44 +
  45 +#include "mtk_wed_regs.h"
  46 +#include "mtk_wed_wo.h"
  47 +#include "mtk_wed.h"
  48 +
  49 +static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
  50 +{
  51 +       return readl(wo->boot.addr + reg);
  52 +}
  53 +
  54 +static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
  55 +{
  56 +       writel(val, wo->boot.addr + reg);
  57 +}
  58 +
  59 +static struct sk_buff *
  60 +mtk_wed_mcu_msg_alloc(const void *data, int data_len)
  61 +{
  62 +       int length = sizeof(struct mtk_wed_mcu_hdr) + data_len;
  63 +       struct sk_buff *skb;
  64 +
  65 +       skb = alloc_skb(length, GFP_KERNEL);
  66 +       if (!skb)
  67 +               return NULL;
  68 +
  69 +       memset(skb->head, 0, length);
  70 +       skb_reserve(skb, sizeof(struct mtk_wed_mcu_hdr));
  71 +       if (data && data_len)
  72 +               skb_put_data(skb, data, data_len);
  73 +
  74 +       return skb;
  75 +}
  76 +
  77 +static struct sk_buff *
  78 +mtk_wed_mcu_get_response(struct mtk_wed_wo *wo, unsigned long expires)
  79 +{
  80 +       if (!time_is_after_jiffies(expires))
  81 +               return NULL;
  82 +
  83 +       wait_event_timeout(wo->mcu.wait, !skb_queue_empty(&wo->mcu.res_q),
  84 +                          expires - jiffies);
  85 +       return skb_dequeue(&wo->mcu.res_q);
  86 +}
  87 +
  88 +void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb)
  89 +{
  90 +       skb_queue_tail(&wo->mcu.res_q, skb);
  91 +       wake_up(&wo->mcu.wait);
  92 +}
  93 +
  94 +void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
  95 +                                     struct sk_buff *skb)
  96 +{
  97 +       struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
  98 +
  99 +       switch (hdr->cmd) {
 100 +       case MTK_WED_WO_EVT_LOG_DUMP: {
 101 +               const char *msg = (const char *)(skb->data + sizeof(*hdr));
 102 +
 103 +               dev_notice(wo->hw->dev, "%s\n", msg);
 104 +               break;
 105 +       }
 106 +       case MTK_WED_WO_EVT_PROFILING: {
 107 +               struct mtk_wed_wo_log_info *info;
 108 +               u32 count = (skb->len - sizeof(*hdr)) / sizeof(*info);
 109 +               int i;
 110 +
 111 +               info = (struct mtk_wed_wo_log_info *)(skb->data + sizeof(*hdr));
 112 +               for (i = 0 ; i < count ; i++)
 113 +                       dev_notice(wo->hw->dev,
 114 +                                  "SN:%u latency: total=%u, rro:%u, mod:%u\n",
 115 +                                  le32_to_cpu(info[i].sn),
 116 +                                  le32_to_cpu(info[i].total),
 117 +                                  le32_to_cpu(info[i].rro),
 118 +                                  le32_to_cpu(info[i].mod));
 119 +               break;
 120 +       }
 121 +       case MTK_WED_WO_EVT_RXCNT_INFO:
 122 +               break;
 123 +       default:
 124 +               break;
 125 +       }
 126 +
 127 +       dev_kfree_skb(skb);
 128 +}
 129 +
 130 +static int
 131 +mtk_wed_mcu_skb_send_msg(struct mtk_wed_wo *wo, struct sk_buff *skb,
 132 +                        int id, int cmd, u16 *wait_seq, bool wait_resp)
 133 +{
 134 +       struct mtk_wed_mcu_hdr *hdr;
 135 +
 136 +       /* TODO: make it dynamic based on cmd */
 137 +       wo->mcu.timeout = 20 * HZ;
 138 +
 139 +       hdr = (struct mtk_wed_mcu_hdr *)skb_push(skb, sizeof(*hdr));
 140 +       hdr->cmd = cmd;
 141 +       hdr->length = cpu_to_le16(skb->len);
 142 +
 143 +       if (wait_resp && wait_seq) {
 144 +               u16 seq = ++wo->mcu.seq;
 145 +
 146 +               if (!seq)
 147 +                       seq = ++wo->mcu.seq;
 148 +               *wait_seq = seq;
 149 +
 150 +               hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_NEED_RSP);
 151 +               hdr->seq = cpu_to_le16(seq);
 152 +       }
 153 +       if (id == MTK_WED_MODULE_ID_WO)
 154 +               hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_FROM_TO_WO);
 155 +
 156 +       dev_kfree_skb(skb);
 157 +       return 0;
 158 +}
 159 +
 160 +static int
 161 +mtk_wed_mcu_parse_response(struct mtk_wed_wo *wo, struct sk_buff *skb,
 162 +                          int cmd, int seq)
 163 +{
 164 +       struct mtk_wed_mcu_hdr *hdr;
 165 +
 166 +       if (!skb) {
 167 +               dev_err(wo->hw->dev, "Message %08x (seq %d) timeout\n",
 168 +                       cmd, seq);
 169 +               return -ETIMEDOUT;
 170 +       }
 171 +
 172 +       hdr = (struct mtk_wed_mcu_hdr *)skb->data;
 173 +       if (le16_to_cpu(hdr->seq) != seq)
 174 +               return -EAGAIN;
 175 +
 176 +       skb_pull(skb, sizeof(*hdr));
 177 +       switch (cmd) {
 178 +       case MTK_WED_WO_CMD_RXCNT_INFO:
 179 +       default:
 180 +               break;
 181 +       }
 182 +
 183 +       return 0;
 184 +}
 185 +
 186 +int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
 187 +                        const void *data, int len, bool wait_resp)
 188 +{
 189 +       unsigned long expires;
 190 +       struct sk_buff *skb;
 191 +       u16 seq;
 192 +       int ret;
 193 +
 194 +       skb = mtk_wed_mcu_msg_alloc(data, len);
 195 +       if (!skb)
 196 +               return -ENOMEM;
 197 +
 198 +       mutex_lock(&wo->mcu.mutex);
 199 +
 200 +       ret = mtk_wed_mcu_skb_send_msg(wo, skb, id, cmd, &seq, wait_resp);
 201 +       if (ret || !wait_resp)
 202 +               goto unlock;
 203 +
 204 +       expires = jiffies + wo->mcu.timeout;
 205 +       do {
 206 +               skb = mtk_wed_mcu_get_response(wo, expires);
 207 +               ret = mtk_wed_mcu_parse_response(wo, skb, cmd, seq);
 208 +               dev_kfree_skb(skb);
 209 +       } while (ret == -EAGAIN);
 210 +
 211 +unlock:
 212 +       mutex_unlock(&wo->mcu.mutex);
 213 +
 214 +       return ret;
 215 +}
 216 +
 217 +static int
 218 +mtk_wed_get_memory_region(struct mtk_wed_wo *wo,
 219 +                         struct mtk_wed_wo_memory_region *region)
 220 +{
 221 +       struct reserved_mem *rmem;
 222 +       struct device_node *np;
 223 +       int index;
 224 +
 225 +       index = of_property_match_string(wo->hw->node, "memory-region-names",
 226 +                                        region->name);
 227 +       if (index < 0)
 228 +               return index;
 229 +
 230 +       np = of_parse_phandle(wo->hw->node, "memory-region", index);
 231 +       if (!np)
 232 +               return -ENODEV;
 233 +
 234 +       rmem = of_reserved_mem_lookup(np);
 235 +       of_node_put(np);
 236 +
 237 +       if (!rmem)
 238 +               return -ENODEV;
 239 +
 240 +       region->phy_addr = rmem->base;
 241 +       region->size = rmem->size;
 242 +       region->addr = devm_ioremap(wo->hw->dev, region->phy_addr, region->size);
 243 +
 244 +       return !region->addr ? -EINVAL : 0;
 245 +}
 246 +
 247 +static int
 248 +mtk_wed_mcu_run_firmware(struct mtk_wed_wo *wo, const struct firmware *fw,
 249 +                        struct mtk_wed_wo_memory_region *region)
 250 +{
 251 +       const u8 *first_region_ptr, *region_ptr, *trailer_ptr, *ptr = fw->data;
 252 +       const struct mtk_wed_fw_trailer *trailer;
 253 +       const struct mtk_wed_fw_region *fw_region;
 254 +
 255 +       trailer_ptr = fw->data + fw->size - sizeof(*trailer);
 256 +       trailer = (const struct mtk_wed_fw_trailer *)trailer_ptr;
 257 +       region_ptr = trailer_ptr - trailer->num_region * sizeof(*fw_region);
 258 +       first_region_ptr = region_ptr;
 259 +
 260 +       while (region_ptr < trailer_ptr) {
 261 +               u32 length;
 262 +
 263 +               fw_region = (const struct mtk_wed_fw_region *)region_ptr;
 264 +               length = le32_to_cpu(fw_region->len);
 265 +
 266 +               if (region->phy_addr != le32_to_cpu(fw_region->addr))
 267 +                       goto next;
 268 +
 269 +               if (region->size < length)
 270 +                       goto next;
 271 +
 272 +               if (first_region_ptr < ptr + length)
 273 +                       goto next;
 274 +
 275 +               if (region->shared && region->consumed)
 276 +                       return 0;
 277 +
 278 +               if (!region->shared || !region->consumed) {
 279 +                       memcpy_toio(region->addr, ptr, length);
 280 +                       region->consumed = true;
 281 +                       return 0;
 282 +               }
 283 +next:
 284 +               region_ptr += sizeof(*fw_region);
 285 +               ptr += length;
 286 +       }
 287 +
 288 +       return -EINVAL;
 289 +}
 290 +
 291 +static int
 292 +mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
 293 +{
 294 +       static struct mtk_wed_wo_memory_region mem_region[] = {
 295 +               [MTK_WED_WO_REGION_EMI] = {
 296 +                       .name = "wo-emi",
 297 +               },
 298 +               [MTK_WED_WO_REGION_ILM] = {
 299 +                       .name = "wo-ilm",
 300 +               },
 301 +               [MTK_WED_WO_REGION_DATA] = {
 302 +                       .name = "wo-data",
 303 +                       .shared = true,
 304 +               },
 305 +       };
 306 +       const struct mtk_wed_fw_trailer *trailer;
 307 +       const struct firmware *fw;
 308 +       const char *fw_name;
 309 +       u32 val, boot_cr;
 310 +       int ret, i;
 311 +
 312 +       /* load firmware region metadata */
 313 +       for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
 314 +               ret = mtk_wed_get_memory_region(wo, &mem_region[i]);
 315 +               if (ret)
 316 +                       return ret;
 317 +       }
 318 +
 319 +       wo->boot.name = "wo-boot";
 320 +       ret = mtk_wed_get_memory_region(wo, &wo->boot);
 321 +       if (ret)
 322 +               return ret;
 323 +
 324 +       /* set dummy cr */
 325 +       wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL,
 326 +               wo->hw->index + 1);
 327 +
 328 +       /* load firmware */
 329 +       fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1 : MT7986_FIRMWARE_WO0;
 330 +       ret = request_firmware(&fw, fw_name, wo->hw->dev);
 331 +       if (ret)
 332 +               return ret;
 333 +
 334 +       trailer = (void *)(fw->data + fw->size -
 335 +                          sizeof(struct mtk_wed_fw_trailer));
 336 +       dev_info(wo->hw->dev,
 337 +                "MTK WED WO Firmware Version: %.10s, Build Time: %.15s\n",
 338 +                trailer->fw_ver, trailer->build_date);
 339 +       dev_info(wo->hw->dev, "MTK WED WO Chip ID %02x Region %d\n",
 340 +                trailer->chip_id, trailer->num_region);
 341 +
 342 +       for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
 343 +               ret = mtk_wed_mcu_run_firmware(wo, fw, &mem_region[i]);
 344 +               if (ret)
 345 +                       goto out;
 346 +       }
 347 +
 348 +       /* set the start address */
 349 +       boot_cr = wo->hw->index ? MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR
 350 +                               : MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
 351 +       wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
 352 +       /* wo firmware reset */
 353 +       wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
 354 +
 355 +       val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR);
 356 +       val |= wo->hw->index ? MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK
 357 +                            : MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
 358 +       wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
 359 +out:
 360 +       release_firmware(fw);
 361 +
 362 +       return ret;
 363 +}
 364 +
 365 +static u32
 366 +mtk_wed_mcu_read_fw_dl(struct mtk_wed_wo *wo)
 367 +{
 368 +       return wed_r32(wo->hw->wed_dev,
 369 +                      MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL);
 370 +}
 371 +
 372 +int mtk_wed_mcu_init(struct mtk_wed_wo *wo)
 373 +{
 374 +       u32 val;
 375 +       int ret;
 376 +
 377 +       skb_queue_head_init(&wo->mcu.res_q);
 378 +       init_waitqueue_head(&wo->mcu.wait);
 379 +       mutex_init(&wo->mcu.mutex);
 380 +
 381 +       ret = mtk_wed_mcu_load_firmware(wo);
 382 +       if (ret)
 383 +               return ret;
 384 +
 385 +       return readx_poll_timeout(mtk_wed_mcu_read_fw_dl, wo, val, !val,
 386 +                                 100, MTK_FW_DL_TIMEOUT);
 387 +}
 388 +
 389 +MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
 390 +MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);
 391 --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
 392 +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
 393 @@ -152,6 +152,7 @@ struct mtk_wdma_desc {
 394
 395  #define MTK_WED_RING_RX(_n)                            (0x400 + (_n) * 0x10)
 396
 397 +#define MTK_WED_SCR0                                   0x3c0
 398  #define MTK_WED_WPDMA_INT_TRIGGER                      0x504
 399  #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE              BIT(1)
 400  #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE              GENMASK(5, 4)
 401 --- /dev/null
 402 +++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
 403 @@ -0,0 +1,150 @@
 404 +/* SPDX-License-Identifier: GPL-2.0-only */
 405 +/* Copyright (C) 2022 Lorenzo Bianconi <lorenzo@kernel.org>  */
 406 +
 407 +#ifndef __MTK_WED_WO_H
 408 +#define __MTK_WED_WO_H
 409 +
 410 +#include <linux/skbuff.h>
 411 +#include <linux/netdevice.h>
 412 +
 413 +struct mtk_wed_hw;
 414 +
 415 +struct mtk_wed_mcu_hdr {
 416 +       /* DW0 */
 417 +       u8 version;
 418 +       u8 cmd;
 419 +       __le16 length;
 420 +
 421 +       /* DW1 */
 422 +       __le16 seq;
 423 +       __le16 flag;
 424 +
 425 +       /* DW2 */
 426 +       __le32 status;
 427 +
 428 +       /* DW3 */
 429 +       u8 rsv[20];
 430 +};
 431 +
 432 +struct mtk_wed_wo_log_info {
 433 +       __le32 sn;
 434 +       __le32 total;
 435 +       __le32 rro;
 436 +       __le32 mod;
 437 +};
 438 +
 439 +enum mtk_wed_wo_event {
 440 +       MTK_WED_WO_EVT_LOG_DUMP         = 0x1,
 441 +       MTK_WED_WO_EVT_PROFILING        = 0x2,
 442 +       MTK_WED_WO_EVT_RXCNT_INFO       = 0x3,
 443 +};
 444 +
 445 +#define MTK_WED_MODULE_ID_WO           1
 446 +#define MTK_FW_DL_TIMEOUT              4000000 /* us */
 447 +#define MTK_WOCPU_TIMEOUT              2000000 /* us */
 448 +
 449 +enum {
 450 +       MTK_WED_WARP_CMD_FLAG_RSP               = BIT(0),
 451 +       MTK_WED_WARP_CMD_FLAG_NEED_RSP          = BIT(1),
 452 +       MTK_WED_WARP_CMD_FLAG_FROM_TO_WO        = BIT(2),
 453 +};
 454 +
 455 +enum {
 456 +       MTK_WED_WO_REGION_EMI,
 457 +       MTK_WED_WO_REGION_ILM,
 458 +       MTK_WED_WO_REGION_DATA,
 459 +       MTK_WED_WO_REGION_BOOT,
 460 +       __MTK_WED_WO_REGION_MAX,
 461 +};
 462 +
 463 +enum mtk_wed_dummy_cr_idx {
 464 +       MTK_WED_DUMMY_CR_FWDL,
 465 +       MTK_WED_DUMMY_CR_WO_STATUS,
 466 +};
 467 +
 468 +#define MT7986_FIRMWARE_WO0    "mediatek/mt7986_wo_0.bin"
 469 +#define MT7986_FIRMWARE_WO1    "mediatek/mt7986_wo_1.bin"
 470 +
 471 +#define MTK_WO_MCU_CFG_LS_BASE                         0
 472 +#define MTK_WO_MCU_CFG_LS_HW_VER_ADDR                  (MTK_WO_MCU_CFG_LS_BASE + 0x000)
 473 +#define MTK_WO_MCU_CFG_LS_FW_VER_ADDR                  (MTK_WO_MCU_CFG_LS_BASE + 0x004)
 474 +#define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR                        (MTK_WO_MCU_CFG_LS_BASE + 0x00c)
 475 +#define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR                        (MTK_WO_MCU_CFG_LS_BASE + 0x010)
 476 +#define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR                 (MTK_WO_MCU_CFG_LS_BASE + 0x014)
 477 +#define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR             (MTK_WO_MCU_CFG_LS_BASE + 0x018)
 478 +#define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR             (MTK_WO_MCU_CFG_LS_BASE + 0x01c)
 479 +#define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR                (MTK_WO_MCU_CFG_LS_BASE + 0x050)
 480 +#define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR            (MTK_WO_MCU_CFG_LS_BASE + 0x060)
 481 +#define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR            (MTK_WO_MCU_CFG_LS_BASE + 0x064)
 482 +
 483 +#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK    BIT(5)
 484 +#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK    BIT(0)
 485 +
 486 +struct mtk_wed_wo_memory_region {
 487 +       const char *name;
 488 +       void __iomem *addr;
 489 +       phys_addr_t phy_addr;
 490 +       u32 size;
 491 +       bool shared:1;
 492 +       bool consumed:1;
 493 +};
 494 +
 495 +struct mtk_wed_fw_region {
 496 +       __le32 decomp_crc;
 497 +       __le32 decomp_len;
 498 +       __le32 decomp_blk_sz;
 499 +       u8 rsv0[4];
 500 +       __le32 addr;
 501 +       __le32 len;
 502 +       u8 feature_set;
 503 +       u8 rsv1[15];
 504 +} __packed;
 505 +
 506 +struct mtk_wed_fw_trailer {
 507 +       u8 chip_id;
 508 +       u8 eco_code;
 509 +       u8 num_region;
 510 +       u8 format_ver;
 511 +       u8 format_flag;
 512 +       u8 rsv[2];
 513 +       char fw_ver[10];
 514 +       char build_date[15];
 515 +       u32 crc;
 516 +};
 517 +
 518 +struct mtk_wed_wo {
 519 +       struct mtk_wed_hw *hw;
 520 +       struct mtk_wed_wo_memory_region boot;
 521 +
 522 +       struct {
 523 +               struct mutex mutex;
 524 +               int timeout;
 525 +               u16 seq;
 526 +
 527 +               struct sk_buff_head res_q;
 528 +               wait_queue_head_t wait;
 529 +       } mcu;
 530 +};
 531 +
 532 +static inline int
 533 +mtk_wed_mcu_check_msg(struct mtk_wed_wo *wo, struct sk_buff *skb)
 534 +{
 535 +       struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
 536 +
 537 +       if (hdr->version)
 538 +               return -EINVAL;
 539 +
 540 +       if (skb->len < sizeof(*hdr) || skb->len != le16_to_cpu(hdr->length))
 541 +               return -EINVAL;
 542 +
 543 +       return 0;
 544 +}
 545 +
 546 +void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb);
 547 +void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
 548 +                                     struct sk_buff *skb);
 549 +int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
 550 +                        const void *data, int len, bool wait_resp);
 551 +int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
 552 +
 553 +#endif /* __MTK_WED_WO_H */
 554 --- a/include/linux/soc/mediatek/mtk_wed.h
 555 +++ b/include/linux/soc/mediatek/mtk_wed.h
 556 @@ -11,6 +11,35 @@
 557  struct mtk_wed_hw;
 558  struct mtk_wdma_desc;
 559
 560 +enum mtk_wed_wo_cmd {
 561 +       MTK_WED_WO_CMD_WED_CFG,
 562 +       MTK_WED_WO_CMD_WED_RX_STAT,
 563 +       MTK_WED_WO_CMD_RRO_SER,
 564 +       MTK_WED_WO_CMD_DBG_INFO,
 565 +       MTK_WED_WO_CMD_DEV_INFO,
 566 +       MTK_WED_WO_CMD_BSS_INFO,
 567 +       MTK_WED_WO_CMD_STA_REC,
 568 +       MTK_WED_WO_CMD_DEV_INFO_DUMP,
 569 +       MTK_WED_WO_CMD_BSS_INFO_DUMP,
 570 +       MTK_WED_WO_CMD_STA_REC_DUMP,
 571 +       MTK_WED_WO_CMD_BA_INFO_DUMP,
 572 +       MTK_WED_WO_CMD_FBCMD_Q_DUMP,
 573 +       MTK_WED_WO_CMD_FW_LOG_CTRL,
 574 +       MTK_WED_WO_CMD_LOG_FLUSH,
 575 +       MTK_WED_WO_CMD_CHANGE_STATE,
 576 +       MTK_WED_WO_CMD_CPU_STATS_ENABLE,
 577 +       MTK_WED_WO_CMD_CPU_STATS_DUMP,
 578 +       MTK_WED_WO_CMD_EXCEPTION_INIT,
 579 +       MTK_WED_WO_CMD_PROF_CTRL,
 580 +       MTK_WED_WO_CMD_STA_BA_DUMP,
 581 +       MTK_WED_WO_CMD_BA_CTRL_DUMP,
 582 +       MTK_WED_WO_CMD_RXCNT_CTRL,
 583 +       MTK_WED_WO_CMD_RXCNT_INFO,
 584 +       MTK_WED_WO_CMD_SET_CAP,
 585 +       MTK_WED_WO_CMD_CCIF_RING_DUMP,
 586 +       MTK_WED_WO_CMD_WED_END
 587 +};
 588 +
 589  enum mtk_wed_bus_tye {
 590         MTK_WED_BUS_PCIE,
 591         MTK_WED_BUS_AXI,