target/linux/generic/backport-5.15/834-v6.8-0007-nvmem-stm32-add-support-for-STM32MP25-BSEC-to-contro.patch

   1 From f0ac5b23039610619ca4a4805528553ecb6bc815 Mon Sep 17 00:00:00 2001
   2 From: Patrick Delaunay <patrick.delaunay@foss.st.com>
   3 Date: Fri, 15 Dec 2023 11:15:36 +0000
   4 Subject: [PATCH] nvmem: stm32: add support for STM32MP25 BSEC to control OTP
   5  data
   6
   7 On STM32MP25, OTP area may be read/written by using BSEC (boot, security
   8 and OTP control). The BSEC internal peripheral is only managed by the
   9 secure world.
  10
  11 The 12 Kbits of OTP (effective) are organized into the following regions:
  12 - lower OTP (OTP0 to OTP127) = 4096 lower OTP bits,
  13   bitwise (1-bit) programmable
  14 - mid OTP (OTP128 to OTP255) = 4096 middle OTP bits,
  15   bulk (32-bit) programmable
  16 - upper OTP (OTP256 to OTP383) = 4096 upper OTP bits,
  17   bulk (32-bit) programmable,
  18   only accessible when BSEC is in closed state.
  19
  20 As HWKEY and ECIES key are only accessible by ROM code;
  21 only 368 OTP words are managed in this driver (OTP0 to OTP267).
  22
  23 This patch adds the STM32MP25 configuration for reading and writing
  24 the OTP data using the OP-TEE BSEC TA services.
  25
  26 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
  27 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
  28 Link: https://lore.kernel.org/r/20231215111536.316972-11-srinivas.kandagatla@linaro.org
  29 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  30 ---
  31  drivers/nvmem/stm32-romem.c | 16 ++++++++++++++++
  32  1 file changed, 16 insertions(+)
  33
  34 --- a/drivers/nvmem/stm32-romem.c
  35 +++ b/drivers/nvmem/stm32-romem.c
  36 @@ -269,6 +269,19 @@ static const struct stm32_romem_cfg stm3
  37         .ta = true,
  38  };
  39
  40 +/*
  41 + * STM32MP25 BSEC OTP: 3 regions of 32-bits data words
  42 + *   lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable
  43 + *   mid OTP (OTP128 to OTP255), bulk (32-bit) programmable
  44 + *   upper OTP (OTP256 to OTP383), bulk (32-bit) programmable
  45 + *              but no access to HWKEY and ECIES key: limited at OTP367
  46 + */
  47 +static const struct stm32_romem_cfg stm32mp25_bsec_cfg = {
  48 +       .size = 368 * 4,
  49 +       .lower = 127,
  50 +       .ta = true,
  51 +};
  52 +
  53  static const struct of_device_id stm32_romem_of_match[] __maybe_unused = {
  54         { .compatible = "st,stm32f4-otp", }, {
  55                 .compatible = "st,stm32mp15-bsec",
  56 @@ -276,6 +289,9 @@ static const struct of_device_id stm32_r
  57         }, {
  58                 .compatible = "st,stm32mp13-bsec",
  59                 .data = (void *)&stm32mp13_bsec_cfg,
  60 +       }, {
  61 +               .compatible = "st,stm32mp25-bsec",
  62 +               .data = (void *)&stm32mp25_bsec_cfg,
  63         },
  64         { /* sentinel */ },
  65  };