1 From f07788079f515ca4a681c5f595bdad19cfbd7b1d Mon Sep 17 00:00:00 2001
2 From: Arnd Bergmann <arnd@arndb.de>
3 Date: Sat, 3 Dec 2022 11:54:25 +0100
4 Subject: [PATCH] ata: ahci: fix enum constants for gcc-13
6 gcc-13 slightly changes the type of constant expressions that are defined
7 in an enum, which triggers a compile time sanity check in libata:
9 linux/drivers/ata/libahci.c: In function 'ahci_led_store':
10 linux/include/linux/compiler_types.h:357:45: error: call to '__compiletime_assert_302' declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)
11 357 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
13 The new behavior is that sizeof() returns the same value for the
14 constant as it does for the enum type, which is generally more sensible
17 The problem in libata is that it contains a single enum definition for
18 lots of unrelated constants, some of which are large positive (unsigned)
19 integers like 0xffffffff, while others like (1<<31) are interpreted as
20 negative integers, and this forces the enum type to become 64 bit wide
21 even though most constants would still fit into a signed 32-bit 'int'.
23 Fix this by changing the entire enum definition to use BIT(x) in place
24 of (1<<x), which results in all values being seen as 'unsigned' and
25 fitting into an unsigned 32-bit type.
27 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107917
28 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107405
29 Reported-by: Luis Machado <luis.machado@arm.com>
30 Cc: linux-ide@vger.kernel.org
31 Cc: Damien Le Moal <damien.lemoal@opensource.wdc.com>
32 Cc: stable@vger.kernel.org
33 Cc: Randy Dunlap <rdunlap@infradead.org>
34 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
35 Tested-by: Luis Machado <luis.machado@arm.com>
36 Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
38 drivers/ata/ahci.h | 245 +++++++++++++++++++++++----------------------
39 1 file changed, 123 insertions(+), 122 deletions(-)
41 --- a/drivers/ata/ahci.h
42 +++ b/drivers/ata/ahci.h
44 #include <linux/libata.h>
45 #include <linux/phy/phy.h>
46 #include <linux/regulator/consumer.h>
47 +#include <linux/bits.h>
49 /* Enclosure Management Control */
50 #define EM_CTRL_MSG_TYPE 0x000f0000
51 @@ -54,12 +55,12 @@ enum {
52 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
54 (AHCI_RX_FIS_SZ * 16),
55 - AHCI_IRQ_ON_SG = (1 << 31),
56 - AHCI_CMD_ATAPI = (1 << 5),
57 - AHCI_CMD_WRITE = (1 << 6),
58 - AHCI_CMD_PREFETCH = (1 << 7),
59 - AHCI_CMD_RESET = (1 << 8),
60 - AHCI_CMD_CLR_BUSY = (1 << 10),
61 + AHCI_IRQ_ON_SG = BIT(31),
62 + AHCI_CMD_ATAPI = BIT(5),
63 + AHCI_CMD_WRITE = BIT(6),
64 + AHCI_CMD_PREFETCH = BIT(7),
65 + AHCI_CMD_RESET = BIT(8),
66 + AHCI_CMD_CLR_BUSY = BIT(10),
68 RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
69 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
70 @@ -77,37 +78,37 @@ enum {
71 HOST_CAP2 = 0x24, /* host capabilities, extended */
74 - HOST_RESET = (1 << 0), /* reset controller; self-clear */
75 - HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
76 - HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */
77 - HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
78 + HOST_RESET = BIT(0), /* reset controller; self-clear */
79 + HOST_IRQ_EN = BIT(1), /* global IRQ enable */
80 + HOST_MRSM = BIT(2), /* MSI Revert to Single Message */
81 + HOST_AHCI_EN = BIT(31), /* AHCI enabled */
84 - HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
85 - HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
86 - HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
87 - HOST_CAP_PART = (1 << 13), /* Partial state capable */
88 - HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
89 - HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
90 - HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
91 - HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
92 - HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
93 - HOST_CAP_CLO = (1 << 24), /* Command List Override support */
94 - HOST_CAP_LED = (1 << 25), /* Supports activity LED */
95 - HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
96 - HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
97 - HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
98 - HOST_CAP_SNTF = (1 << 29), /* SNotification register */
99 - HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
100 - HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
101 + HOST_CAP_SXS = BIT(5), /* Supports External SATA */
102 + HOST_CAP_EMS = BIT(6), /* Enclosure Management support */
103 + HOST_CAP_CCC = BIT(7), /* Command Completion Coalescing */
104 + HOST_CAP_PART = BIT(13), /* Partial state capable */
105 + HOST_CAP_SSC = BIT(14), /* Slumber state capable */
106 + HOST_CAP_PIO_MULTI = BIT(15), /* PIO multiple DRQ support */
107 + HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
108 + HOST_CAP_PMP = BIT(17), /* Port Multiplier support */
109 + HOST_CAP_ONLY = BIT(18), /* Supports AHCI mode only */
110 + HOST_CAP_CLO = BIT(24), /* Command List Override support */
111 + HOST_CAP_LED = BIT(25), /* Supports activity LED */
112 + HOST_CAP_ALPM = BIT(26), /* Aggressive Link PM support */
113 + HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
114 + HOST_CAP_MPS = BIT(28), /* Mechanical presence switch */
115 + HOST_CAP_SNTF = BIT(29), /* SNotification register */
116 + HOST_CAP_NCQ = BIT(30), /* Native Command Queueing */
117 + HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */
120 - HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
121 - HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
122 - HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
123 - HOST_CAP2_SDS = (1 << 3), /* Support device sleep */
124 - HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */
125 - HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */
126 + HOST_CAP2_BOH = BIT(0), /* BIOS/OS handoff supported */
127 + HOST_CAP2_NVMHCI = BIT(1), /* NVMHCI supported */
128 + HOST_CAP2_APST = BIT(2), /* Automatic partial to slumber */
129 + HOST_CAP2_SDS = BIT(3), /* Support device sleep */
130 + HOST_CAP2_SADM = BIT(4), /* Support aggressive DevSlp */
131 + HOST_CAP2_DESO = BIT(5), /* DevSlp from slumber only */
133 /* registers for each SATA port */
134 PORT_LST_ADDR = 0x00, /* command list DMA addr */
135 @@ -129,24 +130,24 @@ enum {
136 PORT_DEVSLP = 0x44, /* device sleep */
138 /* PORT_IRQ_{STAT,MASK} bits */
139 - PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
140 - PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
141 - PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
142 - PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
143 - PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
144 - PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
145 - PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
146 - PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
148 - PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
149 - PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
150 - PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
151 - PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
152 - PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
153 - PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
154 - PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
155 - PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
156 - PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
157 + PORT_IRQ_COLD_PRES = BIT(31), /* cold presence detect */
158 + PORT_IRQ_TF_ERR = BIT(30), /* task file error */
159 + PORT_IRQ_HBUS_ERR = BIT(29), /* host bus fatal error */
160 + PORT_IRQ_HBUS_DATA_ERR = BIT(28), /* host bus data error */
161 + PORT_IRQ_IF_ERR = BIT(27), /* interface fatal error */
162 + PORT_IRQ_IF_NONFATAL = BIT(26), /* interface non-fatal error */
163 + PORT_IRQ_OVERFLOW = BIT(24), /* xfer exhausted available S/G */
164 + PORT_IRQ_BAD_PMP = BIT(23), /* incorrect port multiplier */
166 + PORT_IRQ_PHYRDY = BIT(22), /* PhyRdy changed */
167 + PORT_IRQ_DEV_ILCK = BIT(7), /* device interlock */
168 + PORT_IRQ_CONNECT = BIT(6), /* port connect change status */
169 + PORT_IRQ_SG_DONE = BIT(5), /* descriptor processed */
170 + PORT_IRQ_UNK_FIS = BIT(4), /* unknown FIS rx'd */
171 + PORT_IRQ_SDB_FIS = BIT(3), /* Set Device Bits FIS rx'd */
172 + PORT_IRQ_DMAS_FIS = BIT(2), /* DMA Setup FIS rx'd */
173 + PORT_IRQ_PIOS_FIS = BIT(1), /* PIO Setup FIS rx'd */
174 + PORT_IRQ_D2H_REG_FIS = BIT(0), /* D2H Register FIS rx'd */
176 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
178 @@ -162,34 +163,34 @@ enum {
179 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
182 - PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
183 - PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
184 - PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
185 - PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
186 - PORT_CMD_ESP = (1 << 21), /* External Sata Port */
187 - PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */
188 - PORT_CMD_PMP = (1 << 17), /* PMP attached */
189 - PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
190 - PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
191 - PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
192 - PORT_CMD_CLO = (1 << 3), /* Command list override */
193 - PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
194 - PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
195 - PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
197 - PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
198 - PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
199 - PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
200 - PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
201 + PORT_CMD_ASP = BIT(27), /* Aggressive Slumber/Partial */
202 + PORT_CMD_ALPE = BIT(26), /* Aggressive Link PM enable */
203 + PORT_CMD_ATAPI = BIT(24), /* Device is ATAPI */
204 + PORT_CMD_FBSCP = BIT(22), /* FBS Capable Port */
205 + PORT_CMD_ESP = BIT(21), /* External Sata Port */
206 + PORT_CMD_HPCP = BIT(18), /* HotPlug Capable Port */
207 + PORT_CMD_PMP = BIT(17), /* PMP attached */
208 + PORT_CMD_LIST_ON = BIT(15), /* cmd list DMA engine running */
209 + PORT_CMD_FIS_ON = BIT(14), /* FIS DMA engine running */
210 + PORT_CMD_FIS_RX = BIT(4), /* Enable FIS receive DMA engine */
211 + PORT_CMD_CLO = BIT(3), /* Command list override */
212 + PORT_CMD_POWER_ON = BIT(2), /* Power up device */
213 + PORT_CMD_SPIN_UP = BIT(1), /* Spin up device */
214 + PORT_CMD_START = BIT(0), /* Enable port DMA engine */
216 + PORT_CMD_ICC_MASK = (0xfu << 28), /* i/f ICC state mask */
217 + PORT_CMD_ICC_ACTIVE = (0x1u << 28), /* Put i/f in active state */
218 + PORT_CMD_ICC_PARTIAL = (0x2u << 28), /* Put i/f in partial state */
219 + PORT_CMD_ICC_SLUMBER = (0x6u << 28), /* Put i/f in slumber state */
222 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
223 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
224 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
225 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
226 - PORT_FBS_SDE = (1 << 2), /* FBS single device error */
227 - PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
228 - PORT_FBS_EN = (1 << 0), /* Enable FBS */
229 + PORT_FBS_SDE = BIT(2), /* FBS single device error */
230 + PORT_FBS_DEC = BIT(1), /* FBS device error clear */
231 + PORT_FBS_EN = BIT(0), /* Enable FBS */
233 /* PORT_DEVSLP bits */
234 PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
235 @@ -197,50 +198,50 @@ enum {
236 PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
237 PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
238 PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
239 - PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */
240 - PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */
241 + PORT_DEVSLP_DSP = BIT(1), /* DevSlp present */
242 + PORT_DEVSLP_ADSE = BIT(0), /* Aggressive DevSlp enable */
244 /* hpriv->flags bits */
246 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
248 - AHCI_HFLAG_NO_NCQ = (1 << 0),
249 - AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
250 - AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
251 - AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
252 - AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
253 - AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
254 - AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
255 - AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
256 - AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
257 - AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
258 - AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
259 + AHCI_HFLAG_NO_NCQ = BIT(0),
260 + AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT(1), /* ignore IRQ_IF_ERR */
261 + AHCI_HFLAG_IGN_SERR_INTERNAL = BIT(2), /* ignore SERR_INTERNAL */
262 + AHCI_HFLAG_32BIT_ONLY = BIT(3), /* force 32bit */
263 + AHCI_HFLAG_MV_PATA = BIT(4), /* PATA port */
264 + AHCI_HFLAG_NO_MSI = BIT(5), /* no PCI MSI */
265 + AHCI_HFLAG_NO_PMP = BIT(6), /* no PMP */
266 + AHCI_HFLAG_SECT255 = BIT(8), /* max 255 sectors */
267 + AHCI_HFLAG_YES_NCQ = BIT(9), /* force NCQ cap on */
268 + AHCI_HFLAG_NO_SUSPEND = BIT(10), /* don't suspend */
269 + AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT(11), /* treat SRST timeout as
271 - AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
272 - AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
273 - AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
274 - AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on
275 + AHCI_HFLAG_NO_SNTF = BIT(12), /* no sntf */
276 + AHCI_HFLAG_NO_FPDMA_AA = BIT(13), /* no FPDMA AA */
277 + AHCI_HFLAG_YES_FBS = BIT(14), /* force FBS cap on */
278 + AHCI_HFLAG_DELAY_ENGINE = BIT(15), /* do not start engine on
279 port start (wait until
280 error-handling stage) */
281 - AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */
282 - AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */
283 + AHCI_HFLAG_NO_DEVSLP = BIT(17), /* no device sleep */
284 + AHCI_HFLAG_NO_FBS = BIT(18), /* no FBS */
286 #ifdef CONFIG_PCI_MSI
287 - AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */
288 + AHCI_HFLAG_MULTI_MSI = BIT(20), /* per-port MSI(-X) */
290 /* compile out MSI infrastructure */
291 AHCI_HFLAG_MULTI_MSI = 0,
293 - AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */
294 - AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */
295 - AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
296 + AHCI_HFLAG_WAKE_BEFORE_STOP = BIT(22), /* wake before DMA stop */
297 + AHCI_HFLAG_YES_ALPM = BIT(23), /* force ALPM cap on */
298 + AHCI_HFLAG_NO_WRITE_TO_RO = BIT(24), /* don't write to read
300 - AHCI_HFLAG_IS_MOBILE = (1 << 25), /* mobile chipset, use
301 + AHCI_HFLAG_IS_MOBILE = BIT(25), /* mobile chipset, use
302 SATA_MOBILE_LPM_POLICY
303 as default lpm_policy */
304 - AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
305 + AHCI_HFLAG_SUSPEND_PHYS = BIT(26), /* handle PHYs during
307 - AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */
308 + AHCI_HFLAG_NO_SXS = BIT(28), /* SXS not supported */
312 @@ -256,22 +257,22 @@ enum {
316 - EM_CTL_RST = (1 << 9), /* Reset */
317 - EM_CTL_TM = (1 << 8), /* Transmit Message */
318 - EM_CTL_MR = (1 << 0), /* Message Received */
319 - EM_CTL_ALHD = (1 << 26), /* Activity LED */
320 - EM_CTL_XMT = (1 << 25), /* Transmit Only */
321 - EM_CTL_SMB = (1 << 24), /* Single Message Buffer */
322 - EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */
323 - EM_CTL_SES = (1 << 18), /* SES-2 messages supported */
324 - EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */
325 - EM_CTL_LED = (1 << 16), /* LED messages supported */
326 + EM_CTL_RST = BIT(9), /* Reset */
327 + EM_CTL_TM = BIT(8), /* Transmit Message */
328 + EM_CTL_MR = BIT(0), /* Message Received */
329 + EM_CTL_ALHD = BIT(26), /* Activity LED */
330 + EM_CTL_XMT = BIT(25), /* Transmit Only */
331 + EM_CTL_SMB = BIT(24), /* Single Message Buffer */
332 + EM_CTL_SGPIO = BIT(19), /* SGPIO messages supported */
333 + EM_CTL_SES = BIT(18), /* SES-2 messages supported */
334 + EM_CTL_SAFTE = BIT(17), /* SAF-TE messages supported */
335 + EM_CTL_LED = BIT(16), /* LED messages supported */
337 /* em message type */
338 - EM_MSG_TYPE_LED = (1 << 0), /* LED */
339 - EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */
340 - EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */
341 - EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */
342 + EM_MSG_TYPE_LED = BIT(0), /* LED */
343 + EM_MSG_TYPE_SAFTE = BIT(1), /* SAF-TE */
344 + EM_MSG_TYPE_SES2 = BIT(2), /* SES-2 */
345 + EM_MSG_TYPE_SGPIO = BIT(3), /* SGPIO */
348 struct ahci_cmd_hdr {
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