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mtd: fix build with GCC 14
[openwrt/openwrt.git] / target / linux / generic / backport-5.15 / 791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch
1 From 70479a40954cf353e87a486997a3477108c75aa9 Mon Sep 17 00:00:00 2001
2 From: Frank <Frank.Sae@motor-comm.com>
3 Date: Fri, 28 Oct 2022 17:26:21 +0800
4 Subject: [PATCH] net: phy: Add driver for Motorcomm yt8521 gigabit ethernet
5 phy
6
7 Add a driver for the motorcomm yt8521 gigabit ethernet phy. We have verified
8 the driver on StarFive VisionFive development board, which is developed by
9 Shanghai StarFive Technology Co., Ltd.. On the board, yt8521 gigabit ethernet
10 phy works in utp mode, RGMII interface, supports 1000M/100M/10M speeds, and
11 wol(magic package).
12
13 Signed-off-by: Frank <Frank.Sae@motor-comm.com>
14 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
15 Signed-off-by: David S. Miller <davem@davemloft.net>
16 ---
17 MAINTAINERS | 1 +
18 drivers/net/phy/Kconfig | 2 +-
19 drivers/net/phy/motorcomm.c | 1635 ++++++++++++++++++++++++++++++++++-
20 3 files changed, 1635 insertions(+), 3 deletions(-)
21
22 --- a/MAINTAINERS
23 +++ b/MAINTAINERS
24 @@ -12694,6 +12694,7 @@ F: include/uapi/linux/meye.h
25
26 MOTORCOMM PHY DRIVER
27 M: Peter Geis <pgwipeout@gmail.com>
28 +M: Frank <Frank.Sae@motor-comm.com>
29 L: netdev@vger.kernel.org
30 S: Maintained
31 F: drivers/net/phy/motorcomm.c
32 --- a/drivers/net/phy/Kconfig
33 +++ b/drivers/net/phy/Kconfig
34 @@ -242,7 +242,7 @@ config MOTORCOMM_PHY
35 tristate "Motorcomm PHYs"
36 help
37 Enables support for Motorcomm network PHYs.
38 - Currently supports the YT8511 gigabit PHY.
39 + Currently supports the YT8511, YT8521 Gigabit Ethernet PHYs.
40
41 config NATIONAL_PHY
42 tristate "National Semiconductor PHYs"
43 --- a/drivers/net/phy/motorcomm.c
44 +++ b/drivers/net/phy/motorcomm.c
45 @@ -1,15 +1,106 @@
46 // SPDX-License-Identifier: GPL-2.0+
47 /*
48 - * Driver for Motorcomm PHYs
49 + * Motorcomm 8511/8521 PHY driver.
50 *
51 * Author: Peter Geis <pgwipeout@gmail.com>
52 + * Author: Frank <Frank.Sae@motor-comm.com>
53 */
54
55 +#include <linux/etherdevice.h>
56 #include <linux/kernel.h>
57 #include <linux/module.h>
58 #include <linux/phy.h>
59
60 #define PHY_ID_YT8511 0x0000010a
61 +#define PHY_ID_YT8521 0x0000011A
62 +
63 +/* YT8521 Register Overview
64 + * UTP Register space | FIBER Register space
65 + * ------------------------------------------------------------
66 + * | UTP MII | FIBER MII |
67 + * | UTP MMD | |
68 + * | UTP Extended | FIBER Extended |
69 + * ------------------------------------------------------------
70 + * | Common Extended |
71 + * ------------------------------------------------------------
72 + */
73 +
74 +/* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */
75 +
76 +/* Specific Function Control Register */
77 +#define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10
78 +
79 +/* 2b00 Manual MDI configuration
80 + * 2b01 Manual MDIX configuration
81 + * 2b10 Reserved
82 + * 2b11 Enable automatic crossover for all modes *default*
83 + */
84 +#define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5))
85 +#define YTPHY_SFCR_CROSSOVER_EN BIT(3)
86 +#define YTPHY_SFCR_SQE_TEST_EN BIT(2)
87 +#define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1)
88 +#define YTPHY_SFCR_JABBER_DIS BIT(0)
89 +
90 +/* Specific Status Register */
91 +#define YTPHY_SPECIFIC_STATUS_REG 0x11
92 +#define YTPHY_SSR_SPEED_MODE_OFFSET 14
93 +
94 +#define YTPHY_SSR_SPEED_MODE_MASK (BIT(15) | BIT(14))
95 +#define YTPHY_SSR_SPEED_10M 0x0
96 +#define YTPHY_SSR_SPEED_100M 0x1
97 +#define YTPHY_SSR_SPEED_1000M 0x2
98 +#define YTPHY_SSR_DUPLEX_OFFSET 13
99 +#define YTPHY_SSR_DUPLEX BIT(13)
100 +#define YTPHY_SSR_PAGE_RECEIVED BIT(12)
101 +#define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11)
102 +#define YTPHY_SSR_LINK BIT(10)
103 +#define YTPHY_SSR_MDIX_CROSSOVER BIT(6)
104 +#define YTPHY_SSR_DOWNGRADE BIT(5)
105 +#define YTPHY_SSR_TRANSMIT_PAUSE BIT(3)
106 +#define YTPHY_SSR_RECEIVE_PAUSE BIT(2)
107 +#define YTPHY_SSR_POLARITY BIT(1)
108 +#define YTPHY_SSR_JABBER BIT(0)
109 +
110 +/* Interrupt enable Register */
111 +#define YTPHY_INTERRUPT_ENABLE_REG 0x12
112 +#define YTPHY_IER_WOL BIT(6)
113 +
114 +/* Interrupt Status Register */
115 +#define YTPHY_INTERRUPT_STATUS_REG 0x13
116 +#define YTPHY_ISR_AUTONEG_ERR BIT(15)
117 +#define YTPHY_ISR_SPEED_CHANGED BIT(14)
118 +#define YTPHY_ISR_DUPLEX_CHANGED BIT(13)
119 +#define YTPHY_ISR_PAGE_RECEIVED BIT(12)
120 +#define YTPHY_ISR_LINK_FAILED BIT(11)
121 +#define YTPHY_ISR_LINK_SUCCESSED BIT(10)
122 +#define YTPHY_ISR_WOL BIT(6)
123 +#define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5)
124 +#define YTPHY_ISR_SERDES_LINK_FAILED BIT(3)
125 +#define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2)
126 +#define YTPHY_ISR_POLARITY_CHANGED BIT(1)
127 +#define YTPHY_ISR_JABBER_HAPPENED BIT(0)
128 +
129 +/* Speed Auto Downgrade Control Register */
130 +#define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14
131 +#define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5)
132 +
133 +/* If these bits are set to 3, the PHY attempts five times ( 3(set value) +
134 + * additional 2) before downgrading, default 0x3
135 + */
136 +#define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2)
137 +
138 +/* Rx Error Counter Register */
139 +#define YTPHY_RX_ERROR_COUNTER_REG 0x15
140 +
141 +/* Extended Register's Address Offset Register */
142 +#define YTPHY_PAGE_SELECT 0x1E
143 +
144 +/* Extended Register's Data Register */
145 +#define YTPHY_PAGE_DATA 0x1F
146 +
147 +/* FIBER Auto-Negotiation link partner ability */
148 +#define YTPHY_FLPA_PAUSE (0x3 << 7)
149 +#define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7)
150
151 #define YT8511_PAGE_SELECT 0x1e
152 #define YT8511_PAGE 0x1f
153 @@ -38,6 +129,352 @@
154 #define YT8511_DELAY_FE_TX_EN (0xf << 12)
155 #define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
156
157 +/* Extended register is different from MMD Register and MII Register.
158 + * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to
159 + * operate extended register.
160 + * Extended Register start
161 + */
162 +
163 +/* Phy gmii clock gating Register */
164 +#define YT8521_CLOCK_GATING_REG 0xC
165 +#define YT8521_CGR_RX_CLK_EN BIT(12)
166 +
167 +#define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27
168 +#define YT8521_ESC1R_SLEEP_SW BIT(15)
169 +#define YT8521_ESC1R_PLLON_SLP BIT(14)
170 +
171 +/* Phy fiber Link timer cfg2 Register */
172 +#define YT8521_LINK_TIMER_CFG2_REG 0xA5
173 +#define YT8521_LTCR_EN_AUTOSEN BIT(15)
174 +
175 +/* 0xA000, 0xA001, 0xA003 ,and 0xA006 ~ 0xA00A are common ext registers
176 + * of yt8521 phy. There is no need to switch reg space when operating these
177 + * registers.
178 + */
179 +
180 +#define YT8521_REG_SPACE_SELECT_REG 0xA000
181 +#define YT8521_RSSR_SPACE_MASK BIT(1)
182 +#define YT8521_RSSR_FIBER_SPACE (0x1 << 1)
183 +#define YT8521_RSSR_UTP_SPACE (0x0 << 1)
184 +#define YT8521_RSSR_TO_BE_ARBITRATED (0xFF)
185 +
186 +#define YT8521_CHIP_CONFIG_REG 0xA001
187 +#define YT8521_CCR_SW_RST BIT(15)
188 +
189 +#define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0))
190 +#define YT8521_CCR_MODE_UTP_TO_RGMII 0
191 +#define YT8521_CCR_MODE_FIBER_TO_RGMII 1
192 +#define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2
193 +#define YT8521_CCR_MODE_UTP_TO_SGMII 3
194 +#define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4
195 +#define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5
196 +#define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6
197 +#define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7
198 +
199 +/* 3 phy polling modes,poll mode combines utp and fiber mode*/
200 +#define YT8521_MODE_FIBER 0x1
201 +#define YT8521_MODE_UTP 0x2
202 +#define YT8521_MODE_POLL 0x3
203 +
204 +#define YT8521_RGMII_CONFIG1_REG 0xA003
205 +
206 +/* TX Gig-E Delay is bits 3:0, default 0x1
207 + * TX Fast-E Delay is bits 7:4, default 0xf
208 + * RX Delay is bits 13:10, default 0x0
209 + * Delay = 150ps * N
210 + * On = 2250ps, off = 0ps
211 + */
212 +#define YT8521_RC1R_RX_DELAY_MASK (0xF << 10)
213 +#define YT8521_RC1R_RX_DELAY_EN (0xF << 10)
214 +#define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10)
215 +#define YT8521_RC1R_FE_TX_DELAY_MASK (0xF << 4)
216 +#define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4)
217 +#define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4)
218 +#define YT8521_RC1R_GE_TX_DELAY_MASK (0xF << 0)
219 +#define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0)
220 +#define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0)
221 +
222 +#define YTPHY_MISC_CONFIG_REG 0xA006
223 +#define YTPHY_MCR_FIBER_SPEED_MASK BIT(0)
224 +#define YTPHY_MCR_FIBER_1000BX (0x1 << 0)
225 +#define YTPHY_MCR_FIBER_100FX (0x0 << 0)
226 +
227 +/* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */
228 +#define YTPHY_WOL_MACADDR2_REG 0xA007
229 +#define YTPHY_WOL_MACADDR1_REG 0xA008
230 +#define YTPHY_WOL_MACADDR0_REG 0xA009
231 +
232 +#define YTPHY_WOL_CONFIG_REG 0xA00A
233 +#define YTPHY_WCR_INTR_SEL BIT(6)
234 +#define YTPHY_WCR_ENABLE BIT(3)
235 +
236 +/* 2b00 84ms
237 + * 2b01 168ms *default*
238 + * 2b10 336ms
239 + * 2b11 672ms
240 + */
241 +#define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1))
242 +#define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1))
243 +
244 +/* 1b0 Interrupt and WOL events is level triggered and active LOW *default*
245 + * 1b1 Interrupt and WOL events is pulse triggered and active LOW
246 + */
247 +#define YTPHY_WCR_TYPE_PULSE BIT(0)
248 +
249 +/* Extended Register end */
250 +
251 +struct yt8521_priv {
252 + /* combo_advertising is used for case of YT8521 in combo mode,
253 + * this means that yt8521 may work in utp or fiber mode which depends
254 + * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED).
255 + */
256 + __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising);
257 +
258 + /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/
259 + u8 polling_mode;
260 + u8 strap_mode; /* 8 working modes */
261 + /* current reg page of yt8521 phy:
262 + * YT8521_RSSR_UTP_SPACE
263 + * YT8521_RSSR_FIBER_SPACE
264 + * YT8521_RSSR_TO_BE_ARBITRATED
265 + */
266 + u8 reg_page;
267 +};
268 +
269 +/**
270 + * ytphy_read_ext() - read a PHY's extended register
271 + * @phydev: a pointer to a &struct phy_device
272 + * @regnum: register number to read
273 + *
274 + * NOTE:The caller must have taken the MDIO bus lock.
275 + *
276 + * returns the value of regnum reg or negative error code
277 + */
278 +static int ytphy_read_ext(struct phy_device *phydev, u16 regnum)
279 +{
280 + int ret;
281 +
282 + ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
283 + if (ret < 0)
284 + return ret;
285 +
286 + return __phy_read(phydev, YTPHY_PAGE_DATA);
287 +}
288 +
289 +/**
290 + * ytphy_read_ext_with_lock() - read a PHY's extended register
291 + * @phydev: a pointer to a &struct phy_device
292 + * @regnum: register number to read
293 + *
294 + * returns the value of regnum reg or negative error code
295 + */
296 +static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum)
297 +{
298 + int ret;
299 +
300 + phy_lock_mdio_bus(phydev);
301 + ret = ytphy_read_ext(phydev, regnum);
302 + phy_unlock_mdio_bus(phydev);
303 +
304 + return ret;
305 +}
306 +
307 +/**
308 + * ytphy_write_ext() - write a PHY's extended register
309 + * @phydev: a pointer to a &struct phy_device
310 + * @regnum: register number to write
311 + * @val: value to write to @regnum
312 + *
313 + * NOTE:The caller must have taken the MDIO bus lock.
314 + *
315 + * returns 0 or negative error code
316 + */
317 +static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val)
318 +{
319 + int ret;
320 +
321 + ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
322 + if (ret < 0)
323 + return ret;
324 +
325 + return __phy_write(phydev, YTPHY_PAGE_DATA, val);
326 +}
327 +
328 +/**
329 + * ytphy_write_ext_with_lock() - write a PHY's extended register
330 + * @phydev: a pointer to a &struct phy_device
331 + * @regnum: register number to write
332 + * @val: value to write to @regnum
333 + *
334 + * returns 0 or negative error code
335 + */
336 +static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum,
337 + u16 val)
338 +{
339 + int ret;
340 +
341 + phy_lock_mdio_bus(phydev);
342 + ret = ytphy_write_ext(phydev, regnum, val);
343 + phy_unlock_mdio_bus(phydev);
344 +
345 + return ret;
346 +}
347 +
348 +/**
349 + * ytphy_modify_ext() - bits modify a PHY's extended register
350 + * @phydev: a pointer to a &struct phy_device
351 + * @regnum: register number to write
352 + * @mask: bit mask of bits to clear
353 + * @set: bit mask of bits to set
354 + *
355 + * NOTE: Convenience function which allows a PHY's extended register to be
356 + * modified as new register value = (old register value & ~mask) | set.
357 + * The caller must have taken the MDIO bus lock.
358 + *
359 + * returns 0 or negative error code
360 + */
361 +static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask,
362 + u16 set)
363 +{
364 + int ret;
365 +
366 + ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum);
367 + if (ret < 0)
368 + return ret;
369 +
370 + return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set);
371 +}
372 +
373 +/**
374 + * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register
375 + * @phydev: a pointer to a &struct phy_device
376 + * @regnum: register number to write
377 + * @mask: bit mask of bits to clear
378 + * @set: bit mask of bits to set
379 + *
380 + * NOTE: Convenience function which allows a PHY's extended register to be
381 + * modified as new register value = (old register value & ~mask) | set.
382 + *
383 + * returns 0 or negative error code
384 + */
385 +static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum,
386 + u16 mask, u16 set)
387 +{
388 + int ret;
389 +
390 + phy_lock_mdio_bus(phydev);
391 + ret = ytphy_modify_ext(phydev, regnum, mask, set);
392 + phy_unlock_mdio_bus(phydev);
393 +
394 + return ret;
395 +}
396 +
397 +/**
398 + * ytphy_get_wol() - report whether wake-on-lan is enabled
399 + * @phydev: a pointer to a &struct phy_device
400 + * @wol: a pointer to a &struct ethtool_wolinfo
401 + *
402 + * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg.
403 + */
404 +static void ytphy_get_wol(struct phy_device *phydev,
405 + struct ethtool_wolinfo *wol)
406 +{
407 + int wol_config;
408 +
409 + wol->supported = WAKE_MAGIC;
410 + wol->wolopts = 0;
411 +
412 + wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
413 + if (wol_config < 0)
414 + return;
415 +
416 + if (wol_config & YTPHY_WCR_ENABLE)
417 + wol->wolopts |= WAKE_MAGIC;
418 +}
419 +
420 +/**
421 + * ytphy_set_wol() - turn wake-on-lan on or off
422 + * @phydev: a pointer to a &struct phy_device
423 + * @wol: a pointer to a &struct ethtool_wolinfo
424 + *
425 + * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG
426 + * and YTPHY_WOL_MACADDR0_REG are common ext reg. The
427 + * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register.
428 + *
429 + * returns 0 or negative errno code
430 + */
431 +static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
432 +{
433 + struct net_device *p_attached_dev;
434 + const u16 mac_addr_reg[] = {
435 + YTPHY_WOL_MACADDR2_REG,
436 + YTPHY_WOL_MACADDR1_REG,
437 + YTPHY_WOL_MACADDR0_REG,
438 + };
439 + const u8 *mac_addr;
440 + int old_page;
441 + int ret = 0;
442 + u16 mask;
443 + u16 val;
444 + u8 i;
445 +
446 + if (wol->wolopts & WAKE_MAGIC) {
447 + p_attached_dev = phydev->attached_dev;
448 + if (!p_attached_dev)
449 + return -ENODEV;
450 +
451 + mac_addr = (const u8 *)p_attached_dev->dev_addr;
452 + if (!is_valid_ether_addr(mac_addr))
453 + return -EINVAL;
454 +
455 + /* lock mdio bus then switch to utp reg space */
456 + old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
457 + if (old_page < 0)
458 + goto err_restore_page;
459 +
460 + /* Store the device address for the magic packet */
461 + for (i = 0; i < 3; i++) {
462 + ret = ytphy_write_ext(phydev, mac_addr_reg[i],
463 + ((mac_addr[i * 2] << 8)) |
464 + (mac_addr[i * 2 + 1]));
465 + if (ret < 0)
466 + goto err_restore_page;
467 + }
468 +
469 + /* Enable WOL feature */
470 + mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL;
471 + val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
472 + val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS;
473 + ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val);
474 + if (ret < 0)
475 + goto err_restore_page;
476 +
477 + /* Enable WOL interrupt */
478 + ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0,
479 + YTPHY_IER_WOL);
480 + if (ret < 0)
481 + goto err_restore_page;
482 +
483 + } else {
484 + old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
485 + if (old_page < 0)
486 + goto err_restore_page;
487 +
488 + /* Disable WOL feature */
489 + mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL;
490 + ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0);
491 +
492 + /* Disable WOL interrupt */
493 + ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG,
494 + YTPHY_IER_WOL, 0);
495 + if (ret < 0)
496 + goto err_restore_page;
497 + }
498 +
499 +err_restore_page:
500 + return phy_restore_page(phydev, old_page, ret);
501 +}
502 +
503 static int yt8511_read_page(struct phy_device *phydev)
504 {
505 return __phy_read(phydev, YT8511_PAGE_SELECT);
506 @@ -111,6 +548,1181 @@ err_restore_page:
507 return phy_restore_page(phydev, oldpage, ret);
508 }
509
510 +/**
511 + * yt8521_read_page() - read reg page
512 + * @phydev: a pointer to a &struct phy_device
513 + *
514 + * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/
515 + * YT8521_RSSR_UTP_SPACE) or negative errno code
516 + */
517 +static int yt8521_read_page(struct phy_device *phydev)
518 +{
519 + int old_page;
520 +
521 + old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG);
522 + if (old_page < 0)
523 + return old_page;
524 +
525 + if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
526 + return YT8521_RSSR_FIBER_SPACE;
527 +
528 + return YT8521_RSSR_UTP_SPACE;
529 +};
530 +
531 +/**
532 + * yt8521_write_page() - write reg page
533 + * @phydev: a pointer to a &struct phy_device
534 + * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write.
535 + *
536 + * returns 0 or negative errno code
537 + */
538 +static int yt8521_write_page(struct phy_device *phydev, int page)
539 +{
540 + int mask = YT8521_RSSR_SPACE_MASK;
541 + int set;
542 +
543 + if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE)
544 + set = YT8521_RSSR_FIBER_SPACE;
545 + else
546 + set = YT8521_RSSR_UTP_SPACE;
547 +
548 + return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set);
549 +};
550 +
551 +/**
552 + * yt8521_probe() - read chip config then set suitable polling_mode
553 + * @phydev: a pointer to a &struct phy_device
554 + *
555 + * returns 0 or negative errno code
556 + */
557 +static int yt8521_probe(struct phy_device *phydev)
558 +{
559 + struct device *dev = &phydev->mdio.dev;
560 + struct yt8521_priv *priv;
561 + int chip_config;
562 + int ret;
563 +
564 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
565 + if (!priv)
566 + return -ENOMEM;
567 +
568 + phydev->priv = priv;
569 +
570 + chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
571 + if (chip_config < 0)
572 + return chip_config;
573 +
574 + priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK;
575 + switch (priv->strap_mode) {
576 + case YT8521_CCR_MODE_FIBER_TO_RGMII:
577 + case YT8521_CCR_MODE_SGPHY_TO_RGMAC:
578 + case YT8521_CCR_MODE_SGMAC_TO_RGPHY:
579 + priv->polling_mode = YT8521_MODE_FIBER;
580 + priv->reg_page = YT8521_RSSR_FIBER_SPACE;
581 + phydev->port = PORT_FIBRE;
582 + break;
583 + case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII:
584 + case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO:
585 + case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE:
586 + priv->polling_mode = YT8521_MODE_POLL;
587 + priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
588 + phydev->port = PORT_NONE;
589 + break;
590 + case YT8521_CCR_MODE_UTP_TO_SGMII:
591 + case YT8521_CCR_MODE_UTP_TO_RGMII:
592 + priv->polling_mode = YT8521_MODE_UTP;
593 + priv->reg_page = YT8521_RSSR_UTP_SPACE;
594 + phydev->port = PORT_TP;
595 + break;
596 + }
597 + /* set default reg space */
598 + if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
599 + ret = ytphy_write_ext_with_lock(phydev,
600 + YT8521_REG_SPACE_SELECT_REG,
601 + priv->reg_page);
602 + if (ret < 0)
603 + return ret;
604 + }
605 +
606 + return 0;
607 +}
608 +
609 +/**
610 + * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp
611 + * @phydev: a pointer to a &struct phy_device
612 + *
613 + * NOTE:The caller must have taken the MDIO bus lock.
614 + *
615 + * returns 0 or negative errno code
616 + */
617 +static int ytphy_utp_read_lpa(struct phy_device *phydev)
618 +{
619 + int lpa, lpagb;
620 +
621 + if (phydev->autoneg == AUTONEG_ENABLE) {
622 + if (!phydev->autoneg_complete) {
623 + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
624 + 0);
625 + mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
626 + return 0;
627 + }
628 +
629 + if (phydev->is_gigabit_capable) {
630 + lpagb = __phy_read(phydev, MII_STAT1000);
631 + if (lpagb < 0)
632 + return lpagb;
633 +
634 + if (lpagb & LPA_1000MSFAIL) {
635 + int adv = __phy_read(phydev, MII_CTRL1000);
636 +
637 + if (adv < 0)
638 + return adv;
639 +
640 + if (adv & CTL1000_ENABLE_MASTER)
641 + phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
642 + else
643 + phydev_err(phydev, "Master/Slave resolution failed\n");
644 + return -ENOLINK;
645 + }
646 +
647 + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
648 + lpagb);
649 + }
650 +
651 + lpa = __phy_read(phydev, MII_LPA);
652 + if (lpa < 0)
653 + return lpa;
654 +
655 + mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
656 + } else {
657 + linkmode_zero(phydev->lp_advertising);
658 + }
659 +
660 + return 0;
661 +}
662 +
663 +/**
664 + * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber
665 + * mode, adjust speed and duplex.
666 + * @phydev: a pointer to a &struct phy_device
667 + * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG
668 + * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode)
669 + *
670 + * NOTE:The caller must have taken the MDIO bus lock.
671 + *
672 + * returns 0
673 + */
674 +static int yt8521_adjust_status(struct phy_device *phydev, int status,
675 + bool is_utp)
676 +{
677 + int speed_mode, duplex;
678 + int speed;
679 + int err;
680 + int lpa;
681 +
682 + if (is_utp)
683 + duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET;
684 + else
685 + duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */
686 +
687 + speed_mode = (status & YTPHY_SSR_SPEED_MODE_MASK) >>
688 + YTPHY_SSR_SPEED_MODE_OFFSET;
689 +
690 + switch (speed_mode) {
691 + case YTPHY_SSR_SPEED_10M:
692 + if (is_utp)
693 + speed = SPEED_10;
694 + else
695 + /* for fiber, it will never run here, default to
696 + * SPEED_UNKNOWN
697 + */
698 + speed = SPEED_UNKNOWN;
699 + break;
700 + case YTPHY_SSR_SPEED_100M:
701 + speed = SPEED_100;
702 + break;
703 + case YTPHY_SSR_SPEED_1000M:
704 + speed = SPEED_1000;
705 + break;
706 + default:
707 + speed = SPEED_UNKNOWN;
708 + break;
709 + }
710 +
711 + phydev->speed = speed;
712 + phydev->duplex = duplex;
713 +
714 + if (is_utp) {
715 + err = ytphy_utp_read_lpa(phydev);
716 + if (err < 0)
717 + return err;
718 +
719 + phy_resolve_aneg_pause(phydev);
720 + } else {
721 + lpa = __phy_read(phydev, MII_LPA);
722 + if (lpa < 0)
723 + return lpa;
724 +
725 + /* only support 1000baseX Full */
726 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
727 + phydev->lp_advertising, lpa & LPA_1000XFULL);
728 +
729 + if (!(lpa & YTPHY_FLPA_PAUSE)) {
730 + phydev->pause = 0;
731 + phydev->asym_pause = 0;
732 + } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) {
733 + phydev->pause = 1;
734 + phydev->asym_pause = 1;
735 + } else {
736 + phydev->pause = 1;
737 + phydev->asym_pause = 0;
738 + }
739 + }
740 +
741 + return 0;
742 +}
743 +
744 +/**
745 + * yt8521_read_status_paged() - determines the speed and duplex of one page
746 + * @phydev: a pointer to a &struct phy_device
747 + * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
748 + * operate.
749 + *
750 + * returns 1 (utp or fiber link),0 (no link) or negative errno code
751 + */
752 +static int yt8521_read_status_paged(struct phy_device *phydev, int page)
753 +{
754 + int fiber_latch_val;
755 + int fiber_curr_val;
756 + int old_page;
757 + int ret = 0;
758 + int status;
759 + int link;
760 +
761 + linkmode_zero(phydev->lp_advertising);
762 + phydev->duplex = DUPLEX_UNKNOWN;
763 + phydev->speed = SPEED_UNKNOWN;
764 + phydev->asym_pause = 0;
765 + phydev->pause = 0;
766 +
767 + /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber
768 + * respectively. but for utp/fiber combo mode, reg space should be
769 + * arbitrated based on media priority. by default, utp takes
770 + * priority. reg space should be properly set before read
771 + * YTPHY_SPECIFIC_STATUS_REG.
772 + */
773 +
774 + page &= YT8521_RSSR_SPACE_MASK;
775 + old_page = phy_select_page(phydev, page);
776 + if (old_page < 0)
777 + goto err_restore_page;
778 +
779 + /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex
780 + * of the PHY is actually using.
781 + */
782 + ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
783 + if (ret < 0)
784 + goto err_restore_page;
785 +
786 + status = ret;
787 + link = !!(status & YTPHY_SSR_LINK);
788 +
789 + /* When PHY is in fiber mode, speed transferred from 1000Mbps to
790 + * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so
791 + * we need check MII_BMSR to identify such case.
792 + */
793 + if (page == YT8521_RSSR_FIBER_SPACE) {
794 + ret = __phy_read(phydev, MII_BMSR);
795 + if (ret < 0)
796 + goto err_restore_page;
797 +
798 + fiber_latch_val = ret;
799 + ret = __phy_read(phydev, MII_BMSR);
800 + if (ret < 0)
801 + goto err_restore_page;
802 +
803 + fiber_curr_val = ret;
804 + if (link && fiber_latch_val != fiber_curr_val) {
805 + link = 0;
806 + phydev_info(phydev,
807 + "%s, fiber link down detect, latch = %04x, curr = %04x\n",
808 + __func__, fiber_latch_val, fiber_curr_val);
809 + }
810 + } else {
811 + /* Read autonegotiation status */
812 + ret = __phy_read(phydev, MII_BMSR);
813 + if (ret < 0)
814 + goto err_restore_page;
815 +
816 + phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0;
817 + }
818 +
819 + if (link) {
820 + if (page == YT8521_RSSR_UTP_SPACE)
821 + yt8521_adjust_status(phydev, status, true);
822 + else
823 + yt8521_adjust_status(phydev, status, false);
824 + }
825 + return phy_restore_page(phydev, old_page, link);
826 +
827 +err_restore_page:
828 + return phy_restore_page(phydev, old_page, ret);
829 +}
830 +
831 +/**
832 + * yt8521_read_status() - determines the negotiated speed and duplex
833 + * @phydev: a pointer to a &struct phy_device
834 + *
835 + * returns 0 or negative errno code
836 + */
837 +static int yt8521_read_status(struct phy_device *phydev)
838 +{
839 + struct yt8521_priv *priv = phydev->priv;
840 + int link_fiber = 0;
841 + int link_utp;
842 + int link;
843 + int ret;
844 +
845 + if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
846 + link = yt8521_read_status_paged(phydev, priv->reg_page);
847 + if (link < 0)
848 + return link;
849 + } else {
850 + /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is
851 + * needed. by default, utp is higher priority.
852 + */
853 +
854 + link_utp = yt8521_read_status_paged(phydev,
855 + YT8521_RSSR_UTP_SPACE);
856 + if (link_utp < 0)
857 + return link_utp;
858 +
859 + if (!link_utp) {
860 + link_fiber = yt8521_read_status_paged(phydev,
861 + YT8521_RSSR_FIBER_SPACE);
862 + if (link_fiber < 0)
863 + return link_fiber;
864 + }
865 +
866 + link = link_utp || link_fiber;
867 + }
868 +
869 + if (link) {
870 + if (phydev->link == 0) {
871 + /* arbitrate reg space based on linkup media type. */
872 + if (priv->polling_mode == YT8521_MODE_POLL &&
873 + priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
874 + if (link_fiber)
875 + priv->reg_page =
876 + YT8521_RSSR_FIBER_SPACE;
877 + else
878 + priv->reg_page = YT8521_RSSR_UTP_SPACE;
879 +
880 + ret = ytphy_write_ext_with_lock(phydev,
881 + YT8521_REG_SPACE_SELECT_REG,
882 + priv->reg_page);
883 + if (ret < 0)
884 + return ret;
885 +
886 + phydev->port = link_fiber ? PORT_FIBRE : PORT_TP;
887 +
888 + phydev_info(phydev, "%s, link up, media: %s\n",
889 + __func__,
890 + (phydev->port == PORT_TP) ?
891 + "UTP" : "Fiber");
892 + }
893 + }
894 + phydev->link = 1;
895 + } else {
896 + if (phydev->link == 1) {
897 + phydev_info(phydev, "%s, link down, media: %s\n",
898 + __func__, (phydev->port == PORT_TP) ?
899 + "UTP" : "Fiber");
900 +
901 + /* When in YT8521_MODE_POLL mode, need prepare for next
902 + * arbitration.
903 + */
904 + if (priv->polling_mode == YT8521_MODE_POLL) {
905 + priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED;
906 + phydev->port = PORT_NONE;
907 + }
908 + }
909 +
910 + phydev->link = 0;
911 + }
912 +
913 + return 0;
914 +}
915 +
916 +/**
917 + * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page
918 + * @phydev: the phy_device struct
919 + * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate
920 + * @mask: bit mask of bits to clear
921 + * @set: bit mask of bits to set
922 + *
923 + * NOTE: Convenience function which allows a PHY's BMCR register to be
924 + * modified as new register value = (old register value & ~mask) | set.
925 + * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
926 + * has MII_BMCR. poll mode combines utp and faber,so need do both.
927 + * If it is reset, it will wait for completion.
928 + *
929 + * returns 0 or negative errno code
930 + */
931 +static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page,
932 + u16 mask, u16 set)
933 +{
934 + int max_cnt = 500; /* the max wait time of reset ~ 500 ms */
935 + int old_page;
936 + int ret = 0;
937 +
938 + old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
939 + if (old_page < 0)
940 + goto err_restore_page;
941 +
942 + ret = __phy_modify(phydev, MII_BMCR, mask, set);
943 + if (ret < 0)
944 + goto err_restore_page;
945 +
946 + /* If it is reset, need to wait for the reset to complete */
947 + if (set == BMCR_RESET) {
948 + while (max_cnt--) {
949 + usleep_range(1000, 1100);
950 + ret = __phy_read(phydev, MII_BMCR);
951 + if (ret < 0)
952 + goto err_restore_page;
953 +
954 + if (!(ret & BMCR_RESET))
955 + return phy_restore_page(phydev, old_page, 0);
956 + }
957 + }
958 +
959 +err_restore_page:
960 + return phy_restore_page(phydev, old_page, ret);
961 +}
962 +
963 +/**
964 + * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register
965 + * @phydev: the phy_device struct
966 + * @mask: bit mask of bits to clear
967 + * @set: bit mask of bits to set
968 + *
969 + * NOTE: Convenience function which allows a PHY's BMCR register to be
970 + * modified as new register value = (old register value & ~mask) | set.
971 + * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space
972 + * has MII_BMCR. poll mode combines utp and faber,so need do both.
973 + *
974 + * returns 0 or negative errno code
975 + */
976 +static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask,
977 + u16 set)
978 +{
979 + struct yt8521_priv *priv = phydev->priv;
980 + int ret;
981 +
982 + if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
983 + ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask,
984 + set);
985 + if (ret < 0)
986 + return ret;
987 + } else {
988 + ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE,
989 + mask, set);
990 + if (ret < 0)
991 + return ret;
992 +
993 + ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE,
994 + mask, set);
995 + if (ret < 0)
996 + return ret;
997 + }
998 + return 0;
999 +}
1000 +
1001 +/**
1002 + * yt8521_soft_reset() - called to issue a PHY software reset
1003 + * @phydev: a pointer to a &struct phy_device
1004 + *
1005 + * returns 0 or negative errno code
1006 + */
1007 +static int yt8521_soft_reset(struct phy_device *phydev)
1008 +{
1009 + return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET);
1010 +}
1011 +
1012 +/**
1013 + * yt8521_suspend() - suspend the hardware
1014 + * @phydev: a pointer to a &struct phy_device
1015 + *
1016 + * returns 0 or negative errno code
1017 + */
1018 +static int yt8521_suspend(struct phy_device *phydev)
1019 +{
1020 + int wol_config;
1021 +
1022 + /* YTPHY_WOL_CONFIG_REG is common ext reg */
1023 + wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1024 + if (wol_config < 0)
1025 + return wol_config;
1026 +
1027 + /* if wol enable, do nothing */
1028 + if (wol_config & YTPHY_WCR_ENABLE)
1029 + return 0;
1030 +
1031 + return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN);
1032 +}
1033 +
1034 +/**
1035 + * yt8521_resume() - resume the hardware
1036 + * @phydev: a pointer to a &struct phy_device
1037 + *
1038 + * returns 0 or negative errno code
1039 + */
1040 +static int yt8521_resume(struct phy_device *phydev)
1041 +{
1042 + int ret;
1043 + int wol_config;
1044 +
1045 + /* disable auto sleep */
1046 + ret = ytphy_modify_ext_with_lock(phydev,
1047 + YT8521_EXTREG_SLEEP_CONTROL1_REG,
1048 + YT8521_ESC1R_SLEEP_SW, 0);
1049 + if (ret < 0)
1050 + return ret;
1051 +
1052 + wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG);
1053 + if (wol_config < 0)
1054 + return wol_config;
1055 +
1056 + /* if wol enable, do nothing */
1057 + if (wol_config & YTPHY_WCR_ENABLE)
1058 + return 0;
1059 +
1060 + return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0);
1061 +}
1062 +
1063 +/**
1064 + * yt8521_config_init() - called to initialize the PHY
1065 + * @phydev: a pointer to a &struct phy_device
1066 + *
1067 + * returns 0 or negative errno code
1068 + */
1069 +static int yt8521_config_init(struct phy_device *phydev)
1070 +{
1071 + int old_page;
1072 + int ret = 0;
1073 + u16 val;
1074 +
1075 + old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
1076 + if (old_page < 0)
1077 + goto err_restore_page;
1078 +
1079 + switch (phydev->interface) {
1080 + case PHY_INTERFACE_MODE_RGMII:
1081 + val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_GE_TX_DELAY_DIS;
1082 + val |= YT8521_RC1R_RX_DELAY_DIS;
1083 + break;
1084 + case PHY_INTERFACE_MODE_RGMII_RXID:
1085 + val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_GE_TX_DELAY_DIS;
1086 + val |= YT8521_RC1R_RX_DELAY_EN;
1087 + break;
1088 + case PHY_INTERFACE_MODE_RGMII_TXID:
1089 + val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_GE_TX_DELAY_EN;
1090 + val |= YT8521_RC1R_RX_DELAY_DIS;
1091 + break;
1092 + case PHY_INTERFACE_MODE_RGMII_ID:
1093 + val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_GE_TX_DELAY_EN;
1094 + val |= YT8521_RC1R_RX_DELAY_EN;
1095 + break;
1096 + case PHY_INTERFACE_MODE_SGMII:
1097 + break;
1098 + default: /* do not support other modes */
1099 + ret = -EOPNOTSUPP;
1100 + goto err_restore_page;
1101 + }
1102 +
1103 + /* set rgmii delay mode */
1104 + if (phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1105 + ret = ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG,
1106 + (YT8521_RC1R_RX_DELAY_MASK |
1107 + YT8521_RC1R_FE_TX_DELAY_MASK |
1108 + YT8521_RC1R_GE_TX_DELAY_MASK),
1109 + val);
1110 + if (ret < 0)
1111 + goto err_restore_page;
1112 + }
1113 +
1114 + /* disable auto sleep */
1115 + ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
1116 + YT8521_ESC1R_SLEEP_SW, 0);
1117 + if (ret < 0)
1118 + goto err_restore_page;
1119 +
1120 + /* enable RXC clock when no wire plug */
1121 + ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
1122 + YT8521_CGR_RX_CLK_EN, 0);
1123 + if (ret < 0)
1124 + goto err_restore_page;
1125 +
1126 +err_restore_page:
1127 + return phy_restore_page(phydev, old_page, ret);
1128 +}
1129 +
1130 +/**
1131 + * yt8521_prepare_fiber_features() - A small helper function that setup
1132 + * fiber's features.
1133 + * @phydev: a pointer to a &struct phy_device
1134 + * @dst: a pointer to store fiber's features
1135 + */
1136 +static void yt8521_prepare_fiber_features(struct phy_device *phydev,
1137 + unsigned long *dst)
1138 +{
1139 + linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst);
1140 + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst);
1141 + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst);
1142 + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst);
1143 +}
1144 +
1145 +/**
1146 + * yt8521_fiber_setup_forced - configures/forces speed from @phydev
1147 + * @phydev: target phy_device struct
1148 + *
1149 + * NOTE:The caller must have taken the MDIO bus lock.
1150 + *
1151 + * returns 0 or negative errno code
1152 + */
1153 +static int yt8521_fiber_setup_forced(struct phy_device *phydev)
1154 +{
1155 + u16 val;
1156 + int ret;
1157 +
1158 + if (phydev->speed == SPEED_1000)
1159 + val = YTPHY_MCR_FIBER_1000BX;
1160 + else if (phydev->speed == SPEED_100)
1161 + val = YTPHY_MCR_FIBER_100FX;
1162 + else
1163 + return -EINVAL;
1164 +
1165 + ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
1166 + if (ret < 0)
1167 + return ret;
1168 +
1169 + /* disable Fiber auto sensing */
1170 + ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1171 + YT8521_LTCR_EN_AUTOSEN, 0);
1172 + if (ret < 0)
1173 + return ret;
1174 +
1175 + ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG,
1176 + YTPHY_MCR_FIBER_SPEED_MASK, val);
1177 + if (ret < 0)
1178 + return ret;
1179 +
1180 + return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1181 + YT8521_CCR_SW_RST, 0);
1182 +}
1183 +
1184 +/**
1185 + * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation
1186 + * @phydev: target phy_device struct
1187 + * @restart: whether aneg restart is requested
1188 + *
1189 + * NOTE:The caller must have taken the MDIO bus lock.
1190 + *
1191 + * returns 0 or negative errno code
1192 + */
1193 +static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
1194 +{
1195 + int ret;
1196 +
1197 + if (!restart) {
1198 + /* Advertisement hasn't changed, but maybe aneg was never on to
1199 + * begin with? Or maybe phy was isolated?
1200 + */
1201 + ret = __phy_read(phydev, MII_BMCR);
1202 + if (ret < 0)
1203 + return ret;
1204 +
1205 + if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
1206 + restart = true;
1207 + }
1208 + /* Enable and Restart Autonegotiation
1209 + * Don't isolate the PHY if we're negotiating
1210 + */
1211 + if (restart)
1212 + return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
1213 + BMCR_ANENABLE | BMCR_ANRESTART);
1214 +
1215 + return 0;
1216 +}
1217 +
1218 +/**
1219 + * yt8521_fiber_config_aneg - restart auto-negotiation or write
1220 + * YTPHY_MISC_CONFIG_REG.
1221 + * @phydev: target phy_device struct
1222 + *
1223 + * NOTE:The caller must have taken the MDIO bus lock.
1224 + *
1225 + * returns 0 or negative errno code
1226 + */
1227 +static int yt8521_fiber_config_aneg(struct phy_device *phydev)
1228 +{
1229 + int err, changed = 0;
1230 + int bmcr;
1231 + u16 adv;
1232 +
1233 + if (phydev->autoneg != AUTONEG_ENABLE)
1234 + return yt8521_fiber_setup_forced(phydev);
1235 +
1236 + /* enable Fiber auto sensing */
1237 + err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG,
1238 + 0, YT8521_LTCR_EN_AUTOSEN);
1239 + if (err < 0)
1240 + return err;
1241 +
1242 + err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
1243 + YT8521_CCR_SW_RST, 0);
1244 + if (err < 0)
1245 + return err;
1246 +
1247 + bmcr = __phy_read(phydev, MII_BMCR);
1248 + if (bmcr < 0)
1249 + return bmcr;
1250 +
1251 + /* When it is coming from fiber forced mode, add bmcr power down
1252 + * and power up to let aneg work fine.
1253 + */
1254 + if (!(bmcr & BMCR_ANENABLE)) {
1255 + __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
1256 + usleep_range(1000, 1100);
1257 + __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
1258 + }
1259 +
1260 + adv = linkmode_adv_to_mii_adv_x(phydev->advertising,
1261 + ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
1262 +
1263 + /* Setup fiber advertisement */
1264 + err = __phy_modify_changed(phydev, MII_ADVERTISE,
1265 + ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
1266 + ADVERTISE_1000XPAUSE |
1267 + ADVERTISE_1000XPSE_ASYM,
1268 + adv);
1269 + if (err < 0)
1270 + return err;
1271 +
1272 + if (err > 0)
1273 + changed = 1;
1274 +
1275 + return ytphy_check_and_restart_aneg(phydev, changed);
1276 +}
1277 +
1278 +/**
1279 + * ytphy_setup_master_slave
1280 + * @phydev: target phy_device struct
1281 + *
1282 + * NOTE: The caller must have taken the MDIO bus lock.
1283 + *
1284 + * returns 0 or negative errno code
1285 + */
1286 +static int ytphy_setup_master_slave(struct phy_device *phydev)
1287 +{
1288 + u16 ctl = 0;
1289 +
1290 + if (!phydev->is_gigabit_capable)
1291 + return 0;
1292 +
1293 + switch (phydev->master_slave_set) {
1294 + case MASTER_SLAVE_CFG_MASTER_PREFERRED:
1295 + ctl |= CTL1000_PREFER_MASTER;
1296 + break;
1297 + case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
1298 + break;
1299 + case MASTER_SLAVE_CFG_MASTER_FORCE:
1300 + ctl |= CTL1000_AS_MASTER;
1301 + fallthrough;
1302 + case MASTER_SLAVE_CFG_SLAVE_FORCE:
1303 + ctl |= CTL1000_ENABLE_MASTER;
1304 + break;
1305 + case MASTER_SLAVE_CFG_UNKNOWN:
1306 + case MASTER_SLAVE_CFG_UNSUPPORTED:
1307 + return 0;
1308 + default:
1309 + phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1310 + return -EOPNOTSUPP;
1311 + }
1312 +
1313 + return __phy_modify_changed(phydev, MII_CTRL1000,
1314 + (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
1315 + CTL1000_PREFER_MASTER), ctl);
1316 +}
1317 +
1318 +/**
1319 + * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters
1320 + * @phydev: target phy_device struct
1321 + *
1322 + * NOTE: Writes MII_ADVERTISE with the appropriate values,
1323 + * after sanitizing the values to make sure we only advertise
1324 + * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
1325 + * hasn't changed, and > 0 if it has changed.
1326 + * The caller must have taken the MDIO bus lock.
1327 + *
1328 + * returns 0 or negative errno code
1329 + */
1330 +static int ytphy_utp_config_advert(struct phy_device *phydev)
1331 +{
1332 + int err, bmsr, changed = 0;
1333 + u32 adv;
1334 +
1335 + /* Only allow advertising what this PHY supports */
1336 + linkmode_and(phydev->advertising, phydev->advertising,
1337 + phydev->supported);
1338 +
1339 + adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
1340 +
1341 + /* Setup standard advertisement */
1342 + err = __phy_modify_changed(phydev, MII_ADVERTISE,
1343 + ADVERTISE_ALL | ADVERTISE_100BASE4 |
1344 + ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
1345 + adv);
1346 + if (err < 0)
1347 + return err;
1348 + if (err > 0)
1349 + changed = 1;
1350 +
1351 + bmsr = __phy_read(phydev, MII_BMSR);
1352 + if (bmsr < 0)
1353 + return bmsr;
1354 +
1355 + /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
1356 + * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
1357 + * logical 1.
1358 + */
1359 + if (!(bmsr & BMSR_ESTATEN))
1360 + return changed;
1361 +
1362 + adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1363 +
1364 + err = __phy_modify_changed(phydev, MII_CTRL1000,
1365 + ADVERTISE_1000FULL | ADVERTISE_1000HALF,
1366 + adv);
1367 + if (err < 0)
1368 + return err;
1369 + if (err > 0)
1370 + changed = 1;
1371 +
1372 + return changed;
1373 +}
1374 +
1375 +/**
1376 + * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR
1377 + * @phydev: target phy_device struct
1378 + * @changed: whether autoneg is requested
1379 + *
1380 + * NOTE: If auto-negotiation is enabled, we configure the
1381 + * advertising, and then restart auto-negotiation. If it is not
1382 + * enabled, then we write the BMCR.
1383 + * The caller must have taken the MDIO bus lock.
1384 + *
1385 + * returns 0 or negative errno code
1386 + */
1387 +static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed)
1388 +{
1389 + int err;
1390 + u16 ctl;
1391 +
1392 + err = ytphy_setup_master_slave(phydev);
1393 + if (err < 0)
1394 + return err;
1395 + else if (err)
1396 + changed = true;
1397 +
1398 + if (phydev->autoneg != AUTONEG_ENABLE) {
1399 + /* configures/forces speed/duplex from @phydev */
1400 +
1401 + ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex);
1402 +
1403 + return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK |
1404 + BMCR_ISOLATE | BMCR_PDOWN), ctl);
1405 + }
1406 +
1407 + err = ytphy_utp_config_advert(phydev);
1408 + if (err < 0) /* error */
1409 + return err;
1410 + else if (err)
1411 + changed = true;
1412 +
1413 + return ytphy_check_and_restart_aneg(phydev, changed);
1414 +}
1415 +
1416 +/**
1417 + * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg
1418 + * of one page
1419 + * @phydev: a pointer to a &struct phy_device
1420 + * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1421 + * operate.
1422 + *
1423 + * returns 0 or negative errno code
1424 + */
1425 +static int yt8521_config_aneg_paged(struct phy_device *phydev, int page)
1426 +{
1427 + __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported);
1428 + struct yt8521_priv *priv = phydev->priv;
1429 + int old_page;
1430 + int ret = 0;
1431 +
1432 + page &= YT8521_RSSR_SPACE_MASK;
1433 +
1434 + old_page = phy_select_page(phydev, page);
1435 + if (old_page < 0)
1436 + goto err_restore_page;
1437 +
1438 + /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
1439 + * phydev->advertising should be updated.
1440 + */
1441 + if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) {
1442 + linkmode_zero(fiber_supported);
1443 + yt8521_prepare_fiber_features(phydev, fiber_supported);
1444 +
1445 + /* prepare fiber_supported, then setup advertising. */
1446 + if (page == YT8521_RSSR_FIBER_SPACE) {
1447 + linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
1448 + fiber_supported);
1449 + linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
1450 + fiber_supported);
1451 + linkmode_and(phydev->advertising,
1452 + priv->combo_advertising, fiber_supported);
1453 + } else {
1454 + /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */
1455 + linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1456 + fiber_supported);
1457 + linkmode_andnot(phydev->advertising,
1458 + priv->combo_advertising,
1459 + fiber_supported);
1460 + }
1461 + }
1462 +
1463 + if (page == YT8521_RSSR_FIBER_SPACE)
1464 + ret = yt8521_fiber_config_aneg(phydev);
1465 + else
1466 + ret = ytphy_utp_config_aneg(phydev, false);
1467 +
1468 +err_restore_page:
1469 + return phy_restore_page(phydev, old_page, ret);
1470 +}
1471 +
1472 +/**
1473 + * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged
1474 + * @phydev: a pointer to a &struct phy_device
1475 + *
1476 + * returns 0 or negative errno code
1477 + */
1478 +static int yt8521_config_aneg(struct phy_device *phydev)
1479 +{
1480 + struct yt8521_priv *priv = phydev->priv;
1481 + int ret;
1482 +
1483 + if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1484 + ret = yt8521_config_aneg_paged(phydev, priv->reg_page);
1485 + if (ret < 0)
1486 + return ret;
1487 + } else {
1488 + /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED,
1489 + * phydev->advertising need to be saved at first run.
1490 + * Because it contains the advertising which supported by both
1491 + * mac and yt8521(utp and fiber).
1492 + */
1493 + if (linkmode_empty(priv->combo_advertising)) {
1494 + linkmode_copy(priv->combo_advertising,
1495 + phydev->advertising);
1496 + }
1497 +
1498 + ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE);
1499 + if (ret < 0)
1500 + return ret;
1501 +
1502 + ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE);
1503 + if (ret < 0)
1504 + return ret;
1505 +
1506 + /* we don't known which will be link, so restore
1507 + * phydev->advertising as default value.
1508 + */
1509 + linkmode_copy(phydev->advertising, priv->combo_advertising);
1510 + }
1511 + return 0;
1512 +}
1513 +
1514 +/**
1515 + * yt8521_aneg_done_paged() - determines the auto negotiation result of one
1516 + * page.
1517 + * @phydev: a pointer to a &struct phy_device
1518 + * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1519 + * operate.
1520 + *
1521 + * returns 0(no link)or 1(fiber or utp link) or negative errno code
1522 + */
1523 +static int yt8521_aneg_done_paged(struct phy_device *phydev, int page)
1524 +{
1525 + int old_page;
1526 + int ret = 0;
1527 + int link;
1528 +
1529 + old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK);
1530 + if (old_page < 0)
1531 + goto err_restore_page;
1532 +
1533 + ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG);
1534 + if (ret < 0)
1535 + goto err_restore_page;
1536 +
1537 + link = !!(ret & YTPHY_SSR_LINK);
1538 + ret = link;
1539 +
1540 +err_restore_page:
1541 + return phy_restore_page(phydev, old_page, ret);
1542 +}
1543 +
1544 +/**
1545 + * yt8521_aneg_done() - determines the auto negotiation result
1546 + * @phydev: a pointer to a &struct phy_device
1547 + *
1548 + * returns 0(no link)or 1(fiber or utp link) or negative errno code
1549 + */
1550 +static int yt8521_aneg_done(struct phy_device *phydev)
1551 +{
1552 + struct yt8521_priv *priv = phydev->priv;
1553 + int link_fiber = 0;
1554 + int link_utp;
1555 + int link;
1556 +
1557 + if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1558 + link = yt8521_aneg_done_paged(phydev, priv->reg_page);
1559 + } else {
1560 + link_utp = yt8521_aneg_done_paged(phydev,
1561 + YT8521_RSSR_UTP_SPACE);
1562 + if (link_utp < 0)
1563 + return link_utp;
1564 +
1565 + if (!link_utp) {
1566 + link_fiber = yt8521_aneg_done_paged(phydev,
1567 + YT8521_RSSR_FIBER_SPACE);
1568 + if (link_fiber < 0)
1569 + return link_fiber;
1570 + }
1571 + link = link_fiber || link_utp;
1572 + phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n",
1573 + __func__, link_fiber, link_utp);
1574 + }
1575 +
1576 + return link;
1577 +}
1578 +
1579 +/**
1580 + * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers
1581 + * @phydev: target phy_device struct
1582 + *
1583 + * NOTE: Reads the PHY's abilities and populates
1584 + * phydev->supported accordingly.
1585 + * The caller must have taken the MDIO bus lock.
1586 + *
1587 + * returns 0 or negative errno code
1588 + */
1589 +static int ytphy_utp_read_abilities(struct phy_device *phydev)
1590 +{
1591 + int val;
1592 +
1593 + linkmode_set_bit_array(phy_basic_ports_array,
1594 + ARRAY_SIZE(phy_basic_ports_array),
1595 + phydev->supported);
1596 +
1597 + val = __phy_read(phydev, MII_BMSR);
1598 + if (val < 0)
1599 + return val;
1600 +
1601 + linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
1602 + val & BMSR_ANEGCAPABLE);
1603 +
1604 + linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
1605 + val & BMSR_100FULL);
1606 + linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
1607 + val & BMSR_100HALF);
1608 + linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
1609 + val & BMSR_10FULL);
1610 + linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
1611 + val & BMSR_10HALF);
1612 +
1613 + if (val & BMSR_ESTATEN) {
1614 + val = __phy_read(phydev, MII_ESTATUS);
1615 + if (val < 0)
1616 + return val;
1617 +
1618 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1619 + phydev->supported, val & ESTATUS_1000_TFULL);
1620 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1621 + phydev->supported, val & ESTATUS_1000_THALF);
1622 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1623 + phydev->supported, val & ESTATUS_1000_XFULL);
1624 + }
1625 +
1626 + return 0;
1627 +}
1628 +
1629 +/**
1630 + * yt8521_get_features_paged() - read supported link modes for one page
1631 + * @phydev: a pointer to a &struct phy_device
1632 + * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to
1633 + * operate.
1634 + *
1635 + * returns 0 or negative errno code
1636 + */
1637 +static int yt8521_get_features_paged(struct phy_device *phydev, int page)
1638 +{
1639 + int old_page;
1640 + int ret = 0;
1641 +
1642 + page &= YT8521_RSSR_SPACE_MASK;
1643 + old_page = phy_select_page(phydev, page);
1644 + if (old_page < 0)
1645 + goto err_restore_page;
1646 +
1647 + if (page == YT8521_RSSR_FIBER_SPACE) {
1648 + linkmode_zero(phydev->supported);
1649 + yt8521_prepare_fiber_features(phydev, phydev->supported);
1650 + } else {
1651 + ret = ytphy_utp_read_abilities(phydev);
1652 + if (ret < 0)
1653 + goto err_restore_page;
1654 + }
1655 +
1656 +err_restore_page:
1657 + return phy_restore_page(phydev, old_page, ret);
1658 +}
1659 +
1660 +/**
1661 + * yt8521_get_features - switch reg space then call yt8521_get_features_paged
1662 + * @phydev: target phy_device struct
1663 + *
1664 + * returns 0 or negative errno code
1665 + */
1666 +static int yt8521_get_features(struct phy_device *phydev)
1667 +{
1668 + struct yt8521_priv *priv = phydev->priv;
1669 + int ret;
1670 +
1671 + if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) {
1672 + ret = yt8521_get_features_paged(phydev, priv->reg_page);
1673 + } else {
1674 + ret = yt8521_get_features_paged(phydev,
1675 + YT8521_RSSR_UTP_SPACE);
1676 + if (ret < 0)
1677 + return ret;
1678 +
1679 + /* add fiber's features to phydev->supported */
1680 + yt8521_prepare_fiber_features(phydev, phydev->supported);
1681 + }
1682 + return ret;
1683 +}
1684 +
1685 static struct phy_driver motorcomm_phy_drvs[] = {
1686 {
1687 PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
1688 @@ -121,16 +1733,35 @@ static struct phy_driver motorcomm_phy_d
1689 .read_page = yt8511_read_page,
1690 .write_page = yt8511_write_page,
1691 },
1692 + {
1693 + PHY_ID_MATCH_EXACT(PHY_ID_YT8521),
1694 + .name = "YT8521 Gigabit Ethernet",
1695 + .get_features = yt8521_get_features,
1696 + .probe = yt8521_probe,
1697 + .read_page = yt8521_read_page,
1698 + .write_page = yt8521_write_page,
1699 + .get_wol = ytphy_get_wol,
1700 + .set_wol = ytphy_set_wol,
1701 + .config_aneg = yt8521_config_aneg,
1702 + .aneg_done = yt8521_aneg_done,
1703 + .config_init = yt8521_config_init,
1704 + .read_status = yt8521_read_status,
1705 + .soft_reset = yt8521_soft_reset,
1706 + .suspend = yt8521_suspend,
1707 + .resume = yt8521_resume,
1708 + },
1709 };
1710
1711 module_phy_driver(motorcomm_phy_drvs);
1712
1713 -MODULE_DESCRIPTION("Motorcomm PHY driver");
1714 +MODULE_DESCRIPTION("Motorcomm 8511/8521 PHY driver");
1715 MODULE_AUTHOR("Peter Geis");
1716 +MODULE_AUTHOR("Frank");
1717 MODULE_LICENSE("GPL");
1718
1719 static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
1720 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
1721 + { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) },
1722 { /* sentinal */ }
1723 };
1724
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