target/linux/generic/backport-5.15/766-v5.18-14-net-dsa-qca8k-cache-lo-and-hi-for-mdio-write.patch

   1 From 2481d206fae7884cd07014fd1318e63af35e99eb Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Wed, 2 Feb 2022 01:03:33 +0100
   4 Subject: [PATCH 14/16] net: dsa: qca8k: cache lo and hi for mdio write
   5
   6 From Documentation, we can cache lo and hi the same way we do with the
   7 page. This massively reduce the mdio write as 3/4 of the time as we only
   8 require to write the lo or hi part for a mdio write.
   9
  10 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  11 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  12 Signed-off-by: David S. Miller <davem@davemloft.net>
  13 ---
  14  drivers/net/dsa/qca8k.c | 61 +++++++++++++++++++++++++++++++++--------
  15  drivers/net/dsa/qca8k.h |  5 ++++
  16  2 files changed, 54 insertions(+), 12 deletions(-)
  17
  18 --- a/drivers/net/dsa/qca8k.c
  19 +++ b/drivers/net/dsa/qca8k.c
  20 @@ -89,6 +89,44 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
  21  }
  22
  23  static int
  24 +qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo)
  25 +{
  26 +       u16 *cached_lo = &priv->mdio_cache.lo;
  27 +       struct mii_bus *bus = priv->bus;
  28 +       int ret;
  29 +
  30 +       if (lo == *cached_lo)
  31 +               return 0;
  32 +
  33 +       ret = bus->write(bus, phy_id, regnum, lo);
  34 +       if (ret < 0)
  35 +               dev_err_ratelimited(&bus->dev,
  36 +                                   "failed to write qca8k 32bit lo register\n");
  37 +
  38 +       *cached_lo = lo;
  39 +       return 0;
  40 +}
  41 +
  42 +static int
  43 +qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi)
  44 +{
  45 +       u16 *cached_hi = &priv->mdio_cache.hi;
  46 +       struct mii_bus *bus = priv->bus;
  47 +       int ret;
  48 +
  49 +       if (hi == *cached_hi)
  50 +               return 0;
  51 +
  52 +       ret = bus->write(bus, phy_id, regnum, hi);
  53 +       if (ret < 0)
  54 +               dev_err_ratelimited(&bus->dev,
  55 +                                   "failed to write qca8k 32bit hi register\n");
  56 +
  57 +       *cached_hi = hi;
  58 +       return 0;
  59 +}
  60 +
  61 +static int
  62  qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  63  {
  64         int ret;
  65 @@ -111,7 +149,7 @@ qca8k_mii_read32(struct mii_bus *bus, in
  66  }
  67
  68  static void
  69 -qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
  70 +qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)
  71  {
  72         u16 lo, hi;
  73         int ret;
  74 @@ -119,12 +157,9 @@ qca8k_mii_write32(struct mii_bus *bus, i
  75         lo = val & 0xffff;
  76         hi = (u16)(val >> 16);
  77
  78 -       ret = bus->write(bus, phy_id, regnum, lo);
  79 +       ret = qca8k_set_lo(priv, phy_id, regnum, lo);
  80         if (ret >= 0)
  81 -               ret = bus->write(bus, phy_id, regnum + 1, hi);
  82 -       if (ret < 0)
  83 -               dev_err_ratelimited(&bus->dev,
  84 -                                   "failed to write qca8k 32bit register\n");
  85 +               ret = qca8k_set_hi(priv, phy_id, regnum + 1, hi);
  86  }
  87
  88  static int
  89 @@ -400,7 +435,7 @@ qca8k_regmap_write(void *ctx, uint32_t r
  90         if (ret < 0)
  91                 goto exit;
  92
  93 -       qca8k_mii_write32(bus, 0x10 | r2, r1, val);
  94 +       qca8k_mii_write32(priv, 0x10 | r2, r1, val);
  95
  96  exit:
  97         mutex_unlock(&bus->mdio_lock);
  98 @@ -433,7 +468,7 @@ qca8k_regmap_update_bits(void *ctx, uint
  99
 100         val &= ~mask;
 101         val |= write_val;
 102 -       qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 103 +       qca8k_mii_write32(priv, 0x10 | r2, r1, val);
 104
 105  exit:
 106         mutex_unlock(&bus->mdio_lock);
 107 @@ -1117,14 +1152,14 @@ qca8k_mdio_write(struct qca8k_priv *priv
 108         if (ret)
 109                 goto exit;
 110
 111 -       qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 112 +       qca8k_mii_write32(priv, 0x10 | r2, r1, val);
 113
 114         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 115                                    QCA8K_MDIO_MASTER_BUSY);
 116
 117  exit:
 118         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 119 -       qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 120 +       qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
 121
 122         mutex_unlock(&bus->mdio_lock);
 123
 124 @@ -1154,7 +1189,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
 125         if (ret)
 126                 goto exit;
 127
 128 -       qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 129 +       qca8k_mii_write32(priv, 0x10 | r2, r1, val);
 130
 131         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 132                                    QCA8K_MDIO_MASTER_BUSY);
 133 @@ -1165,7 +1200,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
 134
 135  exit:
 136         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 137 -       qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 138 +       qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
 139
 140         mutex_unlock(&bus->mdio_lock);
 141
 142 @@ -3057,6 +3092,8 @@ qca8k_sw_probe(struct mdio_device *mdiod
 143         }
 144
 145         priv->mdio_cache.page = 0xffff;
 146 +       priv->mdio_cache.lo = 0xffff;
 147 +       priv->mdio_cache.hi = 0xffff;
 148
 149         /* Check the detected switch id */
 150         ret = qca8k_read_switch_id(priv);
 151 --- a/drivers/net/dsa/qca8k.h
 152 +++ b/drivers/net/dsa/qca8k.h
 153 @@ -369,6 +369,11 @@ struct qca8k_mdio_cache {
 154   * mdio writes
 155   */
 156         u16 page;
 157 +/* lo and hi can also be cached and from Documentation we can skip one
 158 + * extra mdio write if lo or hi is didn't change.
 159 + */
 160 +       u16 lo;
 161 +       u16 hi;
 162  };
 163
 164  struct qca8k_priv {