projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gpio-nct5104d: fix compilation with kernel 6.6
[openwrt/openwrt.git] / target / linux / generic / backport-5.15 / 737-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch
1 From d2213db3f49bce8e7a87c8de05b9a091f78f654e Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Tue, 14 Nov 2023 15:08:41 +0100
4 Subject: [PATCH 1/3] net: phy: aquantia: move to separate directory
5
6 Move aquantia PHY driver to separate driectory in preparation for
7 firmware loading support to keep things tidy.
8
9 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
10 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
11 Signed-off-by: David S. Miller <davem@davemloft.net>
12 ---
13 drivers/net/phy/Kconfig | 5 +----
14 drivers/net/phy/Makefile | 6 +-----
15 drivers/net/phy/aquantia/Kconfig | 5 +++++
16 drivers/net/phy/aquantia/Makefile | 6 ++++++
17 drivers/net/phy/{ => aquantia}/aquantia.h | 0
18 drivers/net/phy/{ => aquantia}/aquantia_hwmon.c | 0
19 drivers/net/phy/{ => aquantia}/aquantia_main.c | 0
20 7 files changed, 13 insertions(+), 9 deletions(-)
21 create mode 100644 drivers/net/phy/aquantia/Kconfig
22 create mode 100644 drivers/net/phy/aquantia/Makefile
23 rename drivers/net/phy/{ => aquantia}/aquantia.h (100%)
24 rename drivers/net/phy/{ => aquantia}/aquantia_hwmon.c (100%)
25 rename drivers/net/phy/{ => aquantia}/aquantia_main.c (100%)
26
27 --- a/drivers/net/phy/Kconfig
28 +++ b/drivers/net/phy/Kconfig
29 @@ -83,10 +83,7 @@ config ADIN_PHY
30 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
31 Ethernet PHY
32
33 -config AQUANTIA_PHY
34 - tristate "Aquantia PHYs"
35 - help
36 - Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
37 +source "drivers/net/phy/aquantia/Kconfig"
38
39 config AX88796B_PHY
40 tristate "Asix PHYs"
41 --- a/drivers/net/phy/Makefile
42 +++ b/drivers/net/phy/Makefile
43 @@ -32,11 +32,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
44
45 obj-$(CONFIG_ADIN_PHY) += adin.o
46 obj-$(CONFIG_AMD_PHY) += amd.o
47 -aquantia-objs += aquantia_main.o
48 -ifdef CONFIG_HWMON
49 -aquantia-objs += aquantia_hwmon.o
50 -endif
51 -obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
52 +obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
53 obj-$(CONFIG_AT803X_PHY) += at803x.o
54 obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
55 obj-$(CONFIG_BCM54140_PHY) += bcm54140.o
56 --- /dev/null
57 +++ b/drivers/net/phy/aquantia/Kconfig
58 @@ -0,0 +1,5 @@
59 +# SPDX-License-Identifier: GPL-2.0-only
60 +config AQUANTIA_PHY
61 + tristate "Aquantia PHYs"
62 + help
63 + Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
64 --- /dev/null
65 +++ b/drivers/net/phy/aquantia/Makefile
66 @@ -0,0 +1,6 @@
67 +# SPDX-License-Identifier: GPL-2.0
68 +aquantia-objs += aquantia_main.o
69 +ifdef CONFIG_HWMON
70 +aquantia-objs += aquantia_hwmon.o
71 +endif
72 +obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
73 --- a/drivers/net/phy/aquantia.h
74 +++ /dev/null
75 @@ -1,16 +0,0 @@
76 -/* SPDX-License-Identifier: GPL-2.0 */
77 -/* HWMON driver for Aquantia PHY
78 - *
79 - * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
80 - * Author: Andrew Lunn <andrew@lunn.ch>
81 - * Author: Heiner Kallweit <hkallweit1@gmail.com>
82 - */
83 -
84 -#include <linux/device.h>
85 -#include <linux/phy.h>
86 -
87 -#if IS_REACHABLE(CONFIG_HWMON)
88 -int aqr_hwmon_probe(struct phy_device *phydev);
89 -#else
90 -static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
91 -#endif
92 --- /dev/null
93 +++ b/drivers/net/phy/aquantia/aquantia.h
94 @@ -0,0 +1,16 @@
95 +/* SPDX-License-Identifier: GPL-2.0 */
96 +/* HWMON driver for Aquantia PHY
97 + *
98 + * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
99 + * Author: Andrew Lunn <andrew@lunn.ch>
100 + * Author: Heiner Kallweit <hkallweit1@gmail.com>
101 + */
102 +
103 +#include <linux/device.h>
104 +#include <linux/phy.h>
105 +
106 +#if IS_REACHABLE(CONFIG_HWMON)
107 +int aqr_hwmon_probe(struct phy_device *phydev);
108 +#else
109 +static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
110 +#endif
111 --- /dev/null
112 +++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
113 @@ -0,0 +1,250 @@
114 +// SPDX-License-Identifier: GPL-2.0
115 +/* HWMON driver for Aquantia PHY
116 + *
117 + * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
118 + * Author: Andrew Lunn <andrew@lunn.ch>
119 + * Author: Heiner Kallweit <hkallweit1@gmail.com>
120 + */
121 +
122 +#include <linux/phy.h>
123 +#include <linux/device.h>
124 +#include <linux/ctype.h>
125 +#include <linux/hwmon.h>
126 +
127 +#include "aquantia.h"
128 +
129 +/* Vendor specific 1, MDIO_MMD_VEND2 */
130 +#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
131 +#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
132 +#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
133 +#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
134 +#define VEND1_THERMAL_STAT1 0xc820
135 +#define VEND1_THERMAL_STAT2 0xc821
136 +#define VEND1_THERMAL_STAT2_VALID BIT(0)
137 +#define VEND1_GENERAL_STAT1 0xc830
138 +#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
139 +#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
140 +#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
141 +#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
142 +
143 +#if IS_REACHABLE(CONFIG_HWMON)
144 +
145 +static umode_t aqr_hwmon_is_visible(const void *data,
146 + enum hwmon_sensor_types type,
147 + u32 attr, int channel)
148 +{
149 + if (type != hwmon_temp)
150 + return 0;
151 +
152 + switch (attr) {
153 + case hwmon_temp_input:
154 + case hwmon_temp_min_alarm:
155 + case hwmon_temp_max_alarm:
156 + case hwmon_temp_lcrit_alarm:
157 + case hwmon_temp_crit_alarm:
158 + return 0444;
159 + case hwmon_temp_min:
160 + case hwmon_temp_max:
161 + case hwmon_temp_lcrit:
162 + case hwmon_temp_crit:
163 + return 0644;
164 + default:
165 + return 0;
166 + }
167 +}
168 +
169 +static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
170 +{
171 + int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
172 +
173 + if (temp < 0)
174 + return temp;
175 +
176 + /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
177 + *value = (s16)temp * 1000 / 256;
178 +
179 + return 0;
180 +}
181 +
182 +static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
183 +{
184 + int temp;
185 +
186 + if (value >= 128000 || value < -128000)
187 + return -ERANGE;
188 +
189 + temp = value * 256 / 1000;
190 +
191 + /* temp is in s16 range and we're interested in lower 16 bits only */
192 + return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
193 +}
194 +
195 +static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
196 +{
197 + int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
198 +
199 + if (val < 0)
200 + return val;
201 +
202 + return !!(val & bit);
203 +}
204 +
205 +static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
206 +{
207 + int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
208 +
209 + if (val < 0)
210 + return val;
211 +
212 + *value = val;
213 +
214 + return 0;
215 +}
216 +
217 +static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
218 + u32 attr, int channel, long *value)
219 +{
220 + struct phy_device *phydev = dev_get_drvdata(dev);
221 + int reg;
222 +
223 + if (type != hwmon_temp)
224 + return -EOPNOTSUPP;
225 +
226 + switch (attr) {
227 + case hwmon_temp_input:
228 + reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
229 + VEND1_THERMAL_STAT2_VALID);
230 + if (reg < 0)
231 + return reg;
232 + if (!reg)
233 + return -EBUSY;
234 +
235 + return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
236 +
237 + case hwmon_temp_lcrit:
238 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
239 + value);
240 + case hwmon_temp_min:
241 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
242 + value);
243 + case hwmon_temp_max:
244 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
245 + value);
246 + case hwmon_temp_crit:
247 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
248 + value);
249 + case hwmon_temp_lcrit_alarm:
250 + return aqr_hwmon_status1(phydev,
251 + VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
252 + value);
253 + case hwmon_temp_min_alarm:
254 + return aqr_hwmon_status1(phydev,
255 + VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
256 + value);
257 + case hwmon_temp_max_alarm:
258 + return aqr_hwmon_status1(phydev,
259 + VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
260 + value);
261 + case hwmon_temp_crit_alarm:
262 + return aqr_hwmon_status1(phydev,
263 + VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
264 + value);
265 + default:
266 + return -EOPNOTSUPP;
267 + }
268 +}
269 +
270 +static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
271 + u32 attr, int channel, long value)
272 +{
273 + struct phy_device *phydev = dev_get_drvdata(dev);
274 +
275 + if (type != hwmon_temp)
276 + return -EOPNOTSUPP;
277 +
278 + switch (attr) {
279 + case hwmon_temp_lcrit:
280 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
281 + value);
282 + case hwmon_temp_min:
283 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
284 + value);
285 + case hwmon_temp_max:
286 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
287 + value);
288 + case hwmon_temp_crit:
289 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
290 + value);
291 + default:
292 + return -EOPNOTSUPP;
293 + }
294 +}
295 +
296 +static const struct hwmon_ops aqr_hwmon_ops = {
297 + .is_visible = aqr_hwmon_is_visible,
298 + .read = aqr_hwmon_read,
299 + .write = aqr_hwmon_write,
300 +};
301 +
302 +static u32 aqr_hwmon_chip_config[] = {
303 + HWMON_C_REGISTER_TZ,
304 + 0,
305 +};
306 +
307 +static const struct hwmon_channel_info aqr_hwmon_chip = {
308 + .type = hwmon_chip,
309 + .config = aqr_hwmon_chip_config,
310 +};
311 +
312 +static u32 aqr_hwmon_temp_config[] = {
313 + HWMON_T_INPUT |
314 + HWMON_T_MAX | HWMON_T_MIN |
315 + HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
316 + HWMON_T_CRIT | HWMON_T_LCRIT |
317 + HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
318 + 0,
319 +};
320 +
321 +static const struct hwmon_channel_info aqr_hwmon_temp = {
322 + .type = hwmon_temp,
323 + .config = aqr_hwmon_temp_config,
324 +};
325 +
326 +static const struct hwmon_channel_info *aqr_hwmon_info[] = {
327 + &aqr_hwmon_chip,
328 + &aqr_hwmon_temp,
329 + NULL,
330 +};
331 +
332 +static const struct hwmon_chip_info aqr_hwmon_chip_info = {
333 + .ops = &aqr_hwmon_ops,
334 + .info = aqr_hwmon_info,
335 +};
336 +
337 +int aqr_hwmon_probe(struct phy_device *phydev)
338 +{
339 + struct device *dev = &phydev->mdio.dev;
340 + struct device *hwmon_dev;
341 + char *hwmon_name;
342 + int i, j;
343 +
344 + hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
345 + if (!hwmon_name)
346 + return -ENOMEM;
347 +
348 + for (i = j = 0; hwmon_name[i]; i++) {
349 + if (isalnum(hwmon_name[i])) {
350 + if (i != j)
351 + hwmon_name[j] = hwmon_name[i];
352 + j++;
353 + }
354 + }
355 + hwmon_name[j] = '\0';
356 +
357 + hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
358 + phydev, &aqr_hwmon_chip_info, NULL);
359 +
360 + return PTR_ERR_OR_ZERO(hwmon_dev);
361 +}
362 +
363 +#endif
364 --- /dev/null
365 +++ b/drivers/net/phy/aquantia/aquantia_main.c
366 @@ -0,0 +1,844 @@
367 +// SPDX-License-Identifier: GPL-2.0
368 +/*
369 + * Driver for Aquantia PHY
370 + *
371 + * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
372 + *
373 + * Copyright 2015 Freescale Semiconductor, Inc.
374 + */
375 +
376 +#include <linux/kernel.h>
377 +#include <linux/module.h>
378 +#include <linux/delay.h>
379 +#include <linux/bitfield.h>
380 +#include <linux/phy.h>
381 +
382 +#include "aquantia.h"
383 +
384 +#define PHY_ID_AQ1202 0x03a1b445
385 +#define PHY_ID_AQ2104 0x03a1b460
386 +#define PHY_ID_AQR105 0x03a1b4a2
387 +#define PHY_ID_AQR106 0x03a1b4d0
388 +#define PHY_ID_AQR107 0x03a1b4e0
389 +#define PHY_ID_AQCS109 0x03a1b5c2
390 +#define PHY_ID_AQR405 0x03a1b4b0
391 +#define PHY_ID_AQR113C 0x31c31c12
392 +
393 +#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
394 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
395 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
396 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
397 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
398 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
399 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
400 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
401 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
402 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
403 +
404 +#define MDIO_AN_VEND_PROV 0xc400
405 +#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
406 +#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
407 +#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
408 +#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
409 +#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
410 +#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
411 +#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
412 +
413 +#define MDIO_AN_TX_VEND_STATUS1 0xc800
414 +#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
415 +#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
416 +#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
417 +#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
418 +#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
419 +#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
420 +#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
421 +#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
422 +
423 +#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
424 +#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
425 +
426 +#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
427 +#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
428 +
429 +#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
430 +#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
431 +
432 +#define MDIO_AN_RX_LP_STAT1 0xe820
433 +#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
434 +#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
435 +#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
436 +#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
437 +#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
438 +
439 +#define MDIO_AN_RX_LP_STAT4 0xe823
440 +#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
441 +#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
442 +
443 +#define MDIO_AN_RX_VEND_STAT3 0xe832
444 +#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
445 +
446 +/* MDIO_MMD_C22EXT */
447 +#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
448 +#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
449 +#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
450 +#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
451 +#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
452 +#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
453 +#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
454 +#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
455 +#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
456 +#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
457 +
458 +/* Vendor specific 1, MDIO_MMD_VEND1 */
459 +#define VEND1_GLOBAL_FW_ID 0x0020
460 +#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
461 +#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
462 +
463 +#define VEND1_GLOBAL_GEN_STAT2 0xc831
464 +#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
465 +
466 +/* The following registers all have similar layouts; first the registers... */
467 +#define VEND1_GLOBAL_CFG_10M 0x0310
468 +#define VEND1_GLOBAL_CFG_100M 0x031b
469 +#define VEND1_GLOBAL_CFG_1G 0x031c
470 +#define VEND1_GLOBAL_CFG_2_5G 0x031d
471 +#define VEND1_GLOBAL_CFG_5G 0x031e
472 +#define VEND1_GLOBAL_CFG_10G 0x031f
473 +/* ...and now the fields */
474 +#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
475 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
476 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
477 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
478 +
479 +#define VEND1_GLOBAL_RSVD_STAT1 0xc885
480 +#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
481 +#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
482 +
483 +#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
484 +#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
485 +#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
486 +
487 +#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
488 +#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
489 +
490 +#define VEND1_GLOBAL_INT_STD_MASK 0xff00
491 +#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
492 +#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
493 +#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
494 +#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
495 +#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
496 +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
497 +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
498 +#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
499 +#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
500 +#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
501 +#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
502 +
503 +#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
504 +#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
505 +#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
506 +#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
507 +#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
508 +#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
509 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
510 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
511 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
512 +
513 +/* Sleep and timeout for checking if the Processor-Intensive
514 + * MDIO operation is finished
515 + */
516 +#define AQR107_OP_IN_PROG_SLEEP 1000
517 +#define AQR107_OP_IN_PROG_TIMEOUT 100000
518 +
519 +struct aqr107_hw_stat {
520 + const char *name;
521 + int reg;
522 + int size;
523 +};
524 +
525 +#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
526 +static const struct aqr107_hw_stat aqr107_hw_stats[] = {
527 + SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
528 + SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
529 + SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
530 + SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
531 + SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
532 + SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
533 + SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
534 + SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
535 + SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
536 + SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
537 +};
538 +#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
539 +
540 +struct aqr107_priv {
541 + u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
542 +};
543 +
544 +static int aqr107_get_sset_count(struct phy_device *phydev)
545 +{
546 + return AQR107_SGMII_STAT_SZ;
547 +}
548 +
549 +static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
550 +{
551 + int i;
552 +
553 + for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
554 + strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
555 + ETH_GSTRING_LEN);
556 +}
557 +
558 +static u64 aqr107_get_stat(struct phy_device *phydev, int index)
559 +{
560 + const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
561 + int len_l = min(stat->size, 16);
562 + int len_h = stat->size - len_l;
563 + u64 ret;
564 + int val;
565 +
566 + val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
567 + if (val < 0)
568 + return U64_MAX;
569 +
570 + ret = val & GENMASK(len_l - 1, 0);
571 + if (len_h) {
572 + val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
573 + if (val < 0)
574 + return U64_MAX;
575 +
576 + ret += (val & GENMASK(len_h - 1, 0)) << 16;
577 + }
578 +
579 + return ret;
580 +}
581 +
582 +static void aqr107_get_stats(struct phy_device *phydev,
583 + struct ethtool_stats *stats, u64 *data)
584 +{
585 + struct aqr107_priv *priv = phydev->priv;
586 + u64 val;
587 + int i;
588 +
589 + for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
590 + val = aqr107_get_stat(phydev, i);
591 + if (val == U64_MAX)
592 + phydev_err(phydev, "Reading HW Statistics failed for %s\n",
593 + aqr107_hw_stats[i].name);
594 + else
595 + priv->sgmii_stats[i] += val;
596 +
597 + data[i] = priv->sgmii_stats[i];
598 + }
599 +}
600 +
601 +static int aqr_config_aneg(struct phy_device *phydev)
602 +{
603 + bool changed = false;
604 + u16 reg;
605 + int ret;
606 +
607 + if (phydev->autoneg == AUTONEG_DISABLE)
608 + return genphy_c45_pma_setup_forced(phydev);
609 +
610 + ret = genphy_c45_an_config_aneg(phydev);
611 + if (ret < 0)
612 + return ret;
613 + if (ret > 0)
614 + changed = true;
615 +
616 + /* Clause 45 has no standardized support for 1000BaseT, therefore
617 + * use vendor registers for this mode.
618 + */
619 + reg = 0;
620 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
621 + phydev->advertising))
622 + reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
623 +
624 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
625 + phydev->advertising))
626 + reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
627 +
628 + /* Handle the case when the 2.5G and 5G speeds are not advertised */
629 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
630 + phydev->advertising))
631 + reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
632 +
633 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
634 + phydev->advertising))
635 + reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
636 +
637 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
638 + MDIO_AN_VEND_PROV_1000BASET_HALF |
639 + MDIO_AN_VEND_PROV_1000BASET_FULL |
640 + MDIO_AN_VEND_PROV_2500BASET_FULL |
641 + MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
642 + if (ret < 0)
643 + return ret;
644 + if (ret > 0)
645 + changed = true;
646 +
647 + return genphy_c45_check_and_restart_aneg(phydev, changed);
648 +}
649 +
650 +static int aqr_config_intr(struct phy_device *phydev)
651 +{
652 + bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
653 + int err;
654 +
655 + if (en) {
656 + /* Clear any pending interrupts before enabling them */
657 + err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
658 + if (err < 0)
659 + return err;
660 + }
661 +
662 + err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
663 + en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
664 + if (err < 0)
665 + return err;
666 +
667 + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
668 + en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
669 + if (err < 0)
670 + return err;
671 +
672 + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
673 + en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
674 + VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
675 + if (err < 0)
676 + return err;
677 +
678 + if (!en) {
679 + /* Clear any pending interrupts after we have disabled them */
680 + err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
681 + if (err < 0)
682 + return err;
683 + }
684 +
685 + return 0;
686 +}
687 +
688 +static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
689 +{
690 + int irq_status;
691 +
692 + irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
693 + MDIO_AN_TX_VEND_INT_STATUS2);
694 + if (irq_status < 0) {
695 + phy_error(phydev);
696 + return IRQ_NONE;
697 + }
698 +
699 + if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
700 + return IRQ_NONE;
701 +
702 + phy_trigger_machine(phydev);
703 +
704 + return IRQ_HANDLED;
705 +}
706 +
707 +static int aqr_read_status(struct phy_device *phydev)
708 +{
709 + int val;
710 +
711 + if (phydev->autoneg == AUTONEG_ENABLE) {
712 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
713 + if (val < 0)
714 + return val;
715 +
716 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
717 + phydev->lp_advertising,
718 + val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
719 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
720 + phydev->lp_advertising,
721 + val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
722 + }
723 +
724 + return genphy_c45_read_status(phydev);
725 +}
726 +
727 +static int aqr107_read_rate(struct phy_device *phydev)
728 +{
729 + u32 config_reg;
730 + int val;
731 +
732 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
733 + if (val < 0)
734 + return val;
735 +
736 + if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
737 + phydev->duplex = DUPLEX_FULL;
738 + else
739 + phydev->duplex = DUPLEX_HALF;
740 +
741 + switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
742 + case MDIO_AN_TX_VEND_STATUS1_10BASET:
743 + phydev->speed = SPEED_10;
744 + config_reg = VEND1_GLOBAL_CFG_10M;
745 + break;
746 + case MDIO_AN_TX_VEND_STATUS1_100BASETX:
747 + phydev->speed = SPEED_100;
748 + config_reg = VEND1_GLOBAL_CFG_100M;
749 + break;
750 + case MDIO_AN_TX_VEND_STATUS1_1000BASET:
751 + phydev->speed = SPEED_1000;
752 + config_reg = VEND1_GLOBAL_CFG_1G;
753 + break;
754 + case MDIO_AN_TX_VEND_STATUS1_2500BASET:
755 + phydev->speed = SPEED_2500;
756 + config_reg = VEND1_GLOBAL_CFG_2_5G;
757 + break;
758 + case MDIO_AN_TX_VEND_STATUS1_5000BASET:
759 + phydev->speed = SPEED_5000;
760 + config_reg = VEND1_GLOBAL_CFG_5G;
761 + break;
762 + case MDIO_AN_TX_VEND_STATUS1_10GBASET:
763 + phydev->speed = SPEED_10000;
764 + config_reg = VEND1_GLOBAL_CFG_10G;
765 + break;
766 + default:
767 + phydev->speed = SPEED_UNKNOWN;
768 + return 0;
769 + }
770 +
771 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
772 + if (val < 0)
773 + return val;
774 +
775 + if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
776 + VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
777 + phydev->rate_matching = RATE_MATCH_PAUSE;
778 + else
779 + phydev->rate_matching = RATE_MATCH_NONE;
780 +
781 + return 0;
782 +}
783 +
784 +static int aqr107_read_status(struct phy_device *phydev)
785 +{
786 + int val, ret;
787 +
788 + ret = aqr_read_status(phydev);
789 + if (ret)
790 + return ret;
791 +
792 + if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
793 + return 0;
794 +
795 + val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
796 + if (val < 0)
797 + return val;
798 +
799 + switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
800 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
801 + phydev->interface = PHY_INTERFACE_MODE_10GKR;
802 + break;
803 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
804 + phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
805 + break;
806 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
807 + phydev->interface = PHY_INTERFACE_MODE_10GBASER;
808 + break;
809 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
810 + phydev->interface = PHY_INTERFACE_MODE_USXGMII;
811 + break;
812 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
813 + phydev->interface = PHY_INTERFACE_MODE_XAUI;
814 + break;
815 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
816 + phydev->interface = PHY_INTERFACE_MODE_SGMII;
817 + break;
818 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
819 + phydev->interface = PHY_INTERFACE_MODE_RXAUI;
820 + break;
821 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
822 + phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
823 + break;
824 + default:
825 + phydev->interface = PHY_INTERFACE_MODE_NA;
826 + break;
827 + }
828 +
829 + /* Read possibly downshifted rate from vendor register */
830 + return aqr107_read_rate(phydev);
831 +}
832 +
833 +static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
834 +{
835 + int val, cnt, enable;
836 +
837 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
838 + if (val < 0)
839 + return val;
840 +
841 + enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
842 + cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
843 +
844 + *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
845 +
846 + return 0;
847 +}
848 +
849 +static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
850 +{
851 + int val = 0;
852 +
853 + if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
854 + return -E2BIG;
855 +
856 + if (cnt != DOWNSHIFT_DEV_DISABLE) {
857 + val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
858 + val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
859 + }
860 +
861 + return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
862 + MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
863 + MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
864 +}
865 +
866 +static int aqr107_get_tunable(struct phy_device *phydev,
867 + struct ethtool_tunable *tuna, void *data)
868 +{
869 + switch (tuna->id) {
870 + case ETHTOOL_PHY_DOWNSHIFT:
871 + return aqr107_get_downshift(phydev, data);
872 + default:
873 + return -EOPNOTSUPP;
874 + }
875 +}
876 +
877 +static int aqr107_set_tunable(struct phy_device *phydev,
878 + struct ethtool_tunable *tuna, const void *data)
879 +{
880 + switch (tuna->id) {
881 + case ETHTOOL_PHY_DOWNSHIFT:
882 + return aqr107_set_downshift(phydev, *(const u8 *)data);
883 + default:
884 + return -EOPNOTSUPP;
885 + }
886 +}
887 +
888 +/* If we configure settings whilst firmware is still initializing the chip,
889 + * then these settings may be overwritten. Therefore make sure chip
890 + * initialization has completed. Use presence of the firmware ID as
891 + * indicator for initialization having completed.
892 + * The chip also provides a "reset completed" bit, but it's cleared after
893 + * read. Therefore function would time out if called again.
894 + */
895 +static int aqr107_wait_reset_complete(struct phy_device *phydev)
896 +{
897 + int val;
898 +
899 + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
900 + VEND1_GLOBAL_FW_ID, val, val != 0,
901 + 20000, 2000000, false);
902 +}
903 +
904 +static void aqr107_chip_info(struct phy_device *phydev)
905 +{
906 + u8 fw_major, fw_minor, build_id, prov_id;
907 + int val;
908 +
909 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
910 + if (val < 0)
911 + return;
912 +
913 + fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
914 + fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
915 +
916 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
917 + if (val < 0)
918 + return;
919 +
920 + build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
921 + prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
922 +
923 + phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
924 + fw_major, fw_minor, build_id, prov_id);
925 +}
926 +
927 +static int aqr107_config_init(struct phy_device *phydev)
928 +{
929 + int ret;
930 +
931 + /* Check that the PHY interface type is compatible */
932 + if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
933 + phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
934 + phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
935 + phydev->interface != PHY_INTERFACE_MODE_XGMII &&
936 + phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
937 + phydev->interface != PHY_INTERFACE_MODE_10GKR &&
938 + phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
939 + phydev->interface != PHY_INTERFACE_MODE_XAUI &&
940 + phydev->interface != PHY_INTERFACE_MODE_RXAUI)
941 + return -ENODEV;
942 +
943 + WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
944 + "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
945 +
946 + ret = aqr107_wait_reset_complete(phydev);
947 + if (!ret)
948 + aqr107_chip_info(phydev);
949 +
950 + return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
951 +}
952 +
953 +static int aqcs109_config_init(struct phy_device *phydev)
954 +{
955 + int ret;
956 +
957 + /* Check that the PHY interface type is compatible */
958 + if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
959 + phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
960 + return -ENODEV;
961 +
962 + ret = aqr107_wait_reset_complete(phydev);
963 + if (!ret)
964 + aqr107_chip_info(phydev);
965 +
966 + /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
967 + * PMA speed ability bits are the same for all members of the family,
968 + * AQCS109 however supports speeds up to 2.5G only.
969 + */
970 + ret = phy_set_max_speed(phydev, SPEED_2500);
971 + if (ret)
972 + return ret;
973 +
974 + return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
975 +}
976 +
977 +static void aqr107_link_change_notify(struct phy_device *phydev)
978 +{
979 + u8 fw_major, fw_minor;
980 + bool downshift, short_reach, afr;
981 + int mode, val;
982 +
983 + if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
984 + return;
985 +
986 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
987 + /* call failed or link partner is no Aquantia PHY */
988 + if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
989 + return;
990 +
991 + short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
992 + downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
993 +
994 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
995 + if (val < 0)
996 + return;
997 +
998 + fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
999 + fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
1000 +
1001 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
1002 + if (val < 0)
1003 + return;
1004 +
1005 + afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
1006 +
1007 + phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
1008 + fw_major, fw_minor,
1009 + short_reach ? ", short reach mode" : "",
1010 + downshift ? ", fast-retrain downshift advertised" : "",
1011 + afr ? ", fast reframe advertised" : "");
1012 +
1013 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
1014 + if (val < 0)
1015 + return;
1016 +
1017 + mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
1018 + if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
1019 + phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
1020 +}
1021 +
1022 +static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
1023 +{
1024 + int val, err;
1025 +
1026 + /* The datasheet notes to wait at least 1ms after issuing a
1027 + * processor intensive operation before checking.
1028 + * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
1029 + * because that just determines the maximum time slept, not the minimum.
1030 + */
1031 + usleep_range(1000, 5000);
1032 +
1033 + err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1034 + VEND1_GLOBAL_GEN_STAT2, val,
1035 + !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
1036 + AQR107_OP_IN_PROG_SLEEP,
1037 + AQR107_OP_IN_PROG_TIMEOUT, false);
1038 + if (err) {
1039 + phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
1040 + return err;
1041 + }
1042 +
1043 + return 0;
1044 +}
1045 +
1046 +static int aqr107_get_rate_matching(struct phy_device *phydev,
1047 + phy_interface_t iface)
1048 +{
1049 + if (iface == PHY_INTERFACE_MODE_10GBASER ||
1050 + iface == PHY_INTERFACE_MODE_2500BASEX ||
1051 + iface == PHY_INTERFACE_MODE_NA)
1052 + return RATE_MATCH_PAUSE;
1053 + return RATE_MATCH_NONE;
1054 +}
1055 +
1056 +static int aqr107_suspend(struct phy_device *phydev)
1057 +{
1058 + int err;
1059 +
1060 + err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1061 + MDIO_CTRL1_LPOWER);
1062 + if (err)
1063 + return err;
1064 +
1065 + return aqr107_wait_processor_intensive_op(phydev);
1066 +}
1067 +
1068 +static int aqr107_resume(struct phy_device *phydev)
1069 +{
1070 + int err;
1071 +
1072 + err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1073 + MDIO_CTRL1_LPOWER);
1074 + if (err)
1075 + return err;
1076 +
1077 + return aqr107_wait_processor_intensive_op(phydev);
1078 +}
1079 +
1080 +static int aqr107_probe(struct phy_device *phydev)
1081 +{
1082 + phydev->priv = devm_kzalloc(&phydev->mdio.dev,
1083 + sizeof(struct aqr107_priv), GFP_KERNEL);
1084 + if (!phydev->priv)
1085 + return -ENOMEM;
1086 +
1087 + return aqr_hwmon_probe(phydev);
1088 +}
1089 +
1090 +static struct phy_driver aqr_driver[] = {
1091 +{
1092 + PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
1093 + .name = "Aquantia AQ1202",
1094 + .config_aneg = aqr_config_aneg,
1095 + .config_intr = aqr_config_intr,
1096 + .handle_interrupt = aqr_handle_interrupt,
1097 + .read_status = aqr_read_status,
1098 +},
1099 +{
1100 + PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
1101 + .name = "Aquantia AQ2104",
1102 + .config_aneg = aqr_config_aneg,
1103 + .config_intr = aqr_config_intr,
1104 + .handle_interrupt = aqr_handle_interrupt,
1105 + .read_status = aqr_read_status,
1106 +},
1107 +{
1108 + PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
1109 + .name = "Aquantia AQR105",
1110 + .config_aneg = aqr_config_aneg,
1111 + .config_intr = aqr_config_intr,
1112 + .handle_interrupt = aqr_handle_interrupt,
1113 + .read_status = aqr_read_status,
1114 + .suspend = aqr107_suspend,
1115 + .resume = aqr107_resume,
1116 +},
1117 +{
1118 + PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
1119 + .name = "Aquantia AQR106",
1120 + .config_aneg = aqr_config_aneg,
1121 + .config_intr = aqr_config_intr,
1122 + .handle_interrupt = aqr_handle_interrupt,
1123 + .read_status = aqr_read_status,
1124 +},
1125 +{
1126 + PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
1127 + .name = "Aquantia AQR107",
1128 + .probe = aqr107_probe,
1129 + .get_rate_matching = aqr107_get_rate_matching,
1130 + .config_init = aqr107_config_init,
1131 + .config_aneg = aqr_config_aneg,
1132 + .config_intr = aqr_config_intr,
1133 + .handle_interrupt = aqr_handle_interrupt,
1134 + .read_status = aqr107_read_status,
1135 + .get_tunable = aqr107_get_tunable,
1136 + .set_tunable = aqr107_set_tunable,
1137 + .suspend = aqr107_suspend,
1138 + .resume = aqr107_resume,
1139 + .get_sset_count = aqr107_get_sset_count,
1140 + .get_strings = aqr107_get_strings,
1141 + .get_stats = aqr107_get_stats,
1142 + .link_change_notify = aqr107_link_change_notify,
1143 +},
1144 +{
1145 + PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
1146 + .name = "Aquantia AQCS109",
1147 + .probe = aqr107_probe,
1148 + .get_rate_matching = aqr107_get_rate_matching,
1149 + .config_init = aqcs109_config_init,
1150 + .config_aneg = aqr_config_aneg,
1151 + .config_intr = aqr_config_intr,
1152 + .handle_interrupt = aqr_handle_interrupt,
1153 + .read_status = aqr107_read_status,
1154 + .get_tunable = aqr107_get_tunable,
1155 + .set_tunable = aqr107_set_tunable,
1156 + .suspend = aqr107_suspend,
1157 + .resume = aqr107_resume,
1158 + .get_sset_count = aqr107_get_sset_count,
1159 + .get_strings = aqr107_get_strings,
1160 + .get_stats = aqr107_get_stats,
1161 + .link_change_notify = aqr107_link_change_notify,
1162 +},
1163 +{
1164 + PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
1165 + .name = "Aquantia AQR405",
1166 + .config_aneg = aqr_config_aneg,
1167 + .config_intr = aqr_config_intr,
1168 + .handle_interrupt = aqr_handle_interrupt,
1169 + .read_status = aqr_read_status,
1170 +},
1171 +{
1172 + PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
1173 + .name = "Aquantia AQR113C",
1174 + .probe = aqr107_probe,
1175 + .get_rate_matching = aqr107_get_rate_matching,
1176 + .config_init = aqr107_config_init,
1177 + .config_aneg = aqr_config_aneg,
1178 + .config_intr = aqr_config_intr,
1179 + .handle_interrupt = aqr_handle_interrupt,
1180 + .read_status = aqr107_read_status,
1181 + .get_tunable = aqr107_get_tunable,
1182 + .set_tunable = aqr107_set_tunable,
1183 + .suspend = aqr107_suspend,
1184 + .resume = aqr107_resume,
1185 + .get_sset_count = aqr107_get_sset_count,
1186 + .get_strings = aqr107_get_strings,
1187 + .get_stats = aqr107_get_stats,
1188 + .link_change_notify = aqr107_link_change_notify,
1189 +},
1190 +};
1191 +
1192 +module_phy_driver(aqr_driver);
1193 +
1194 +static struct mdio_device_id __maybe_unused aqr_tbl[] = {
1195 + { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
1196 + { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
1197 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
1198 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
1199 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
1200 + { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
1201 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
1202 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
1203 + { }
1204 +};
1205 +
1206 +MODULE_DEVICE_TABLE(mdio, aqr_tbl);
1207 +
1208 +MODULE_DESCRIPTION("Aquantia PHY driver");
1209 +MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
1210 +MODULE_LICENSE("GPL v2");
1211 --- a/drivers/net/phy/aquantia_hwmon.c
1212 +++ /dev/null
1213 @@ -1,250 +0,0 @@
1214 -// SPDX-License-Identifier: GPL-2.0
1215 -/* HWMON driver for Aquantia PHY
1216 - *
1217 - * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
1218 - * Author: Andrew Lunn <andrew@lunn.ch>
1219 - * Author: Heiner Kallweit <hkallweit1@gmail.com>
1220 - */
1221 -
1222 -#include <linux/phy.h>
1223 -#include <linux/device.h>
1224 -#include <linux/ctype.h>
1225 -#include <linux/hwmon.h>
1226 -
1227 -#include "aquantia.h"
1228 -
1229 -/* Vendor specific 1, MDIO_MMD_VEND2 */
1230 -#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
1231 -#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
1232 -#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
1233 -#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
1234 -#define VEND1_THERMAL_STAT1 0xc820
1235 -#define VEND1_THERMAL_STAT2 0xc821
1236 -#define VEND1_THERMAL_STAT2_VALID BIT(0)
1237 -#define VEND1_GENERAL_STAT1 0xc830
1238 -#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
1239 -#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
1240 -#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
1241 -#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
1242 -
1243 -#if IS_REACHABLE(CONFIG_HWMON)
1244 -
1245 -static umode_t aqr_hwmon_is_visible(const void *data,
1246 - enum hwmon_sensor_types type,
1247 - u32 attr, int channel)
1248 -{
1249 - if (type != hwmon_temp)
1250 - return 0;
1251 -
1252 - switch (attr) {
1253 - case hwmon_temp_input:
1254 - case hwmon_temp_min_alarm:
1255 - case hwmon_temp_max_alarm:
1256 - case hwmon_temp_lcrit_alarm:
1257 - case hwmon_temp_crit_alarm:
1258 - return 0444;
1259 - case hwmon_temp_min:
1260 - case hwmon_temp_max:
1261 - case hwmon_temp_lcrit:
1262 - case hwmon_temp_crit:
1263 - return 0644;
1264 - default:
1265 - return 0;
1266 - }
1267 -}
1268 -
1269 -static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
1270 -{
1271 - int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
1272 -
1273 - if (temp < 0)
1274 - return temp;
1275 -
1276 - /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
1277 - *value = (s16)temp * 1000 / 256;
1278 -
1279 - return 0;
1280 -}
1281 -
1282 -static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
1283 -{
1284 - int temp;
1285 -
1286 - if (value >= 128000 || value < -128000)
1287 - return -ERANGE;
1288 -
1289 - temp = value * 256 / 1000;
1290 -
1291 - /* temp is in s16 range and we're interested in lower 16 bits only */
1292 - return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
1293 -}
1294 -
1295 -static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
1296 -{
1297 - int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
1298 -
1299 - if (val < 0)
1300 - return val;
1301 -
1302 - return !!(val & bit);
1303 -}
1304 -
1305 -static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
1306 -{
1307 - int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
1308 -
1309 - if (val < 0)
1310 - return val;
1311 -
1312 - *value = val;
1313 -
1314 - return 0;
1315 -}
1316 -
1317 -static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
1318 - u32 attr, int channel, long *value)
1319 -{
1320 - struct phy_device *phydev = dev_get_drvdata(dev);
1321 - int reg;
1322 -
1323 - if (type != hwmon_temp)
1324 - return -EOPNOTSUPP;
1325 -
1326 - switch (attr) {
1327 - case hwmon_temp_input:
1328 - reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
1329 - VEND1_THERMAL_STAT2_VALID);
1330 - if (reg < 0)
1331 - return reg;
1332 - if (!reg)
1333 - return -EBUSY;
1334 -
1335 - return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
1336 -
1337 - case hwmon_temp_lcrit:
1338 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
1339 - value);
1340 - case hwmon_temp_min:
1341 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
1342 - value);
1343 - case hwmon_temp_max:
1344 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
1345 - value);
1346 - case hwmon_temp_crit:
1347 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
1348 - value);
1349 - case hwmon_temp_lcrit_alarm:
1350 - return aqr_hwmon_status1(phydev,
1351 - VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
1352 - value);
1353 - case hwmon_temp_min_alarm:
1354 - return aqr_hwmon_status1(phydev,
1355 - VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
1356 - value);
1357 - case hwmon_temp_max_alarm:
1358 - return aqr_hwmon_status1(phydev,
1359 - VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
1360 - value);
1361 - case hwmon_temp_crit_alarm:
1362 - return aqr_hwmon_status1(phydev,
1363 - VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
1364 - value);
1365 - default:
1366 - return -EOPNOTSUPP;
1367 - }
1368 -}
1369 -
1370 -static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
1371 - u32 attr, int channel, long value)
1372 -{
1373 - struct phy_device *phydev = dev_get_drvdata(dev);
1374 -
1375 - if (type != hwmon_temp)
1376 - return -EOPNOTSUPP;
1377 -
1378 - switch (attr) {
1379 - case hwmon_temp_lcrit:
1380 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
1381 - value);
1382 - case hwmon_temp_min:
1383 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
1384 - value);
1385 - case hwmon_temp_max:
1386 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
1387 - value);
1388 - case hwmon_temp_crit:
1389 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
1390 - value);
1391 - default:
1392 - return -EOPNOTSUPP;
1393 - }
1394 -}
1395 -
1396 -static const struct hwmon_ops aqr_hwmon_ops = {
1397 - .is_visible = aqr_hwmon_is_visible,
1398 - .read = aqr_hwmon_read,
1399 - .write = aqr_hwmon_write,
1400 -};
1401 -
1402 -static u32 aqr_hwmon_chip_config[] = {
1403 - HWMON_C_REGISTER_TZ,
1404 - 0,
1405 -};
1406 -
1407 -static const struct hwmon_channel_info aqr_hwmon_chip = {
1408 - .type = hwmon_chip,
1409 - .config = aqr_hwmon_chip_config,
1410 -};
1411 -
1412 -static u32 aqr_hwmon_temp_config[] = {
1413 - HWMON_T_INPUT |
1414 - HWMON_T_MAX | HWMON_T_MIN |
1415 - HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
1416 - HWMON_T_CRIT | HWMON_T_LCRIT |
1417 - HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
1418 - 0,
1419 -};
1420 -
1421 -static const struct hwmon_channel_info aqr_hwmon_temp = {
1422 - .type = hwmon_temp,
1423 - .config = aqr_hwmon_temp_config,
1424 -};
1425 -
1426 -static const struct hwmon_channel_info *aqr_hwmon_info[] = {
1427 - &aqr_hwmon_chip,
1428 - &aqr_hwmon_temp,
1429 - NULL,
1430 -};
1431 -
1432 -static const struct hwmon_chip_info aqr_hwmon_chip_info = {
1433 - .ops = &aqr_hwmon_ops,
1434 - .info = aqr_hwmon_info,
1435 -};
1436 -
1437 -int aqr_hwmon_probe(struct phy_device *phydev)
1438 -{
1439 - struct device *dev = &phydev->mdio.dev;
1440 - struct device *hwmon_dev;
1441 - char *hwmon_name;
1442 - int i, j;
1443 -
1444 - hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
1445 - if (!hwmon_name)
1446 - return -ENOMEM;
1447 -
1448 - for (i = j = 0; hwmon_name[i]; i++) {
1449 - if (isalnum(hwmon_name[i])) {
1450 - if (i != j)
1451 - hwmon_name[j] = hwmon_name[i];
1452 - j++;
1453 - }
1454 - }
1455 - hwmon_name[j] = '\0';
1456 -
1457 - hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
1458 - phydev, &aqr_hwmon_chip_info, NULL);
1459 -
1460 - return PTR_ERR_OR_ZERO(hwmon_dev);
1461 -}
1462 -
1463 -#endif
1464 --- a/drivers/net/phy/aquantia_main.c
1465 +++ /dev/null
1466 @@ -1,844 +0,0 @@
1467 -// SPDX-License-Identifier: GPL-2.0
1468 -/*
1469 - * Driver for Aquantia PHY
1470 - *
1471 - * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
1472 - *
1473 - * Copyright 2015 Freescale Semiconductor, Inc.
1474 - */
1475 -
1476 -#include <linux/kernel.h>
1477 -#include <linux/module.h>
1478 -#include <linux/delay.h>
1479 -#include <linux/bitfield.h>
1480 -#include <linux/phy.h>
1481 -
1482 -#include "aquantia.h"
1483 -
1484 -#define PHY_ID_AQ1202 0x03a1b445
1485 -#define PHY_ID_AQ2104 0x03a1b460
1486 -#define PHY_ID_AQR105 0x03a1b4a2
1487 -#define PHY_ID_AQR106 0x03a1b4d0
1488 -#define PHY_ID_AQR107 0x03a1b4e0
1489 -#define PHY_ID_AQCS109 0x03a1b5c2
1490 -#define PHY_ID_AQR405 0x03a1b4b0
1491 -#define PHY_ID_AQR113C 0x31c31c12
1492 -
1493 -#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
1494 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
1495 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
1496 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
1497 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
1498 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
1499 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
1500 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
1501 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
1502 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
1503 -
1504 -#define MDIO_AN_VEND_PROV 0xc400
1505 -#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
1506 -#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
1507 -#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
1508 -#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
1509 -#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
1510 -#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
1511 -#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
1512 -
1513 -#define MDIO_AN_TX_VEND_STATUS1 0xc800
1514 -#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
1515 -#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
1516 -#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
1517 -#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
1518 -#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
1519 -#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
1520 -#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
1521 -#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
1522 -
1523 -#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
1524 -#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
1525 -
1526 -#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
1527 -#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
1528 -
1529 -#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
1530 -#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
1531 -
1532 -#define MDIO_AN_RX_LP_STAT1 0xe820
1533 -#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
1534 -#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
1535 -#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
1536 -#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
1537 -#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
1538 -
1539 -#define MDIO_AN_RX_LP_STAT4 0xe823
1540 -#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
1541 -#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
1542 -
1543 -#define MDIO_AN_RX_VEND_STAT3 0xe832
1544 -#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
1545 -
1546 -/* MDIO_MMD_C22EXT */
1547 -#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
1548 -#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
1549 -#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
1550 -#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
1551 -#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
1552 -#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
1553 -#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
1554 -#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
1555 -#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
1556 -#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
1557 -
1558 -/* Vendor specific 1, MDIO_MMD_VEND1 */
1559 -#define VEND1_GLOBAL_FW_ID 0x0020
1560 -#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
1561 -#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
1562 -
1563 -#define VEND1_GLOBAL_GEN_STAT2 0xc831
1564 -#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
1565 -
1566 -/* The following registers all have similar layouts; first the registers... */
1567 -#define VEND1_GLOBAL_CFG_10M 0x0310
1568 -#define VEND1_GLOBAL_CFG_100M 0x031b
1569 -#define VEND1_GLOBAL_CFG_1G 0x031c
1570 -#define VEND1_GLOBAL_CFG_2_5G 0x031d
1571 -#define VEND1_GLOBAL_CFG_5G 0x031e
1572 -#define VEND1_GLOBAL_CFG_10G 0x031f
1573 -/* ...and now the fields */
1574 -#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
1575 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
1576 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
1577 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
1578 -
1579 -#define VEND1_GLOBAL_RSVD_STAT1 0xc885
1580 -#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
1581 -#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
1582 -
1583 -#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
1584 -#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
1585 -#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
1586 -
1587 -#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
1588 -#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
1589 -
1590 -#define VEND1_GLOBAL_INT_STD_MASK 0xff00
1591 -#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
1592 -#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
1593 -#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
1594 -#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
1595 -#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
1596 -#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
1597 -#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
1598 -#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
1599 -#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
1600 -#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
1601 -#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
1602 -
1603 -#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
1604 -#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
1605 -#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
1606 -#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
1607 -#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
1608 -#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
1609 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
1610 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
1611 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
1612 -
1613 -/* Sleep and timeout for checking if the Processor-Intensive
1614 - * MDIO operation is finished
1615 - */
1616 -#define AQR107_OP_IN_PROG_SLEEP 1000
1617 -#define AQR107_OP_IN_PROG_TIMEOUT 100000
1618 -
1619 -struct aqr107_hw_stat {
1620 - const char *name;
1621 - int reg;
1622 - int size;
1623 -};
1624 -
1625 -#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
1626 -static const struct aqr107_hw_stat aqr107_hw_stats[] = {
1627 - SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
1628 - SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
1629 - SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
1630 - SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
1631 - SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
1632 - SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
1633 - SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
1634 - SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
1635 - SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
1636 - SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
1637 -};
1638 -#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
1639 -
1640 -struct aqr107_priv {
1641 - u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
1642 -};
1643 -
1644 -static int aqr107_get_sset_count(struct phy_device *phydev)
1645 -{
1646 - return AQR107_SGMII_STAT_SZ;
1647 -}
1648 -
1649 -static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
1650 -{
1651 - int i;
1652 -
1653 - for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
1654 - strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
1655 - ETH_GSTRING_LEN);
1656 -}
1657 -
1658 -static u64 aqr107_get_stat(struct phy_device *phydev, int index)
1659 -{
1660 - const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
1661 - int len_l = min(stat->size, 16);
1662 - int len_h = stat->size - len_l;
1663 - u64 ret;
1664 - int val;
1665 -
1666 - val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
1667 - if (val < 0)
1668 - return U64_MAX;
1669 -
1670 - ret = val & GENMASK(len_l - 1, 0);
1671 - if (len_h) {
1672 - val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
1673 - if (val < 0)
1674 - return U64_MAX;
1675 -
1676 - ret += (val & GENMASK(len_h - 1, 0)) << 16;
1677 - }
1678 -
1679 - return ret;
1680 -}
1681 -
1682 -static void aqr107_get_stats(struct phy_device *phydev,
1683 - struct ethtool_stats *stats, u64 *data)
1684 -{
1685 - struct aqr107_priv *priv = phydev->priv;
1686 - u64 val;
1687 - int i;
1688 -
1689 - for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
1690 - val = aqr107_get_stat(phydev, i);
1691 - if (val == U64_MAX)
1692 - phydev_err(phydev, "Reading HW Statistics failed for %s\n",
1693 - aqr107_hw_stats[i].name);
1694 - else
1695 - priv->sgmii_stats[i] += val;
1696 -
1697 - data[i] = priv->sgmii_stats[i];
1698 - }
1699 -}
1700 -
1701 -static int aqr_config_aneg(struct phy_device *phydev)
1702 -{
1703 - bool changed = false;
1704 - u16 reg;
1705 - int ret;
1706 -
1707 - if (phydev->autoneg == AUTONEG_DISABLE)
1708 - return genphy_c45_pma_setup_forced(phydev);
1709 -
1710 - ret = genphy_c45_an_config_aneg(phydev);
1711 - if (ret < 0)
1712 - return ret;
1713 - if (ret > 0)
1714 - changed = true;
1715 -
1716 - /* Clause 45 has no standardized support for 1000BaseT, therefore
1717 - * use vendor registers for this mode.
1718 - */
1719 - reg = 0;
1720 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1721 - phydev->advertising))
1722 - reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
1723 -
1724 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1725 - phydev->advertising))
1726 - reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
1727 -
1728 - /* Handle the case when the 2.5G and 5G speeds are not advertised */
1729 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1730 - phydev->advertising))
1731 - reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
1732 -
1733 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1734 - phydev->advertising))
1735 - reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
1736 -
1737 - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
1738 - MDIO_AN_VEND_PROV_1000BASET_HALF |
1739 - MDIO_AN_VEND_PROV_1000BASET_FULL |
1740 - MDIO_AN_VEND_PROV_2500BASET_FULL |
1741 - MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
1742 - if (ret < 0)
1743 - return ret;
1744 - if (ret > 0)
1745 - changed = true;
1746 -
1747 - return genphy_c45_check_and_restart_aneg(phydev, changed);
1748 -}
1749 -
1750 -static int aqr_config_intr(struct phy_device *phydev)
1751 -{
1752 - bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
1753 - int err;
1754 -
1755 - if (en) {
1756 - /* Clear any pending interrupts before enabling them */
1757 - err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
1758 - if (err < 0)
1759 - return err;
1760 - }
1761 -
1762 - err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
1763 - en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
1764 - if (err < 0)
1765 - return err;
1766 -
1767 - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
1768 - en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
1769 - if (err < 0)
1770 - return err;
1771 -
1772 - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
1773 - en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
1774 - VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
1775 - if (err < 0)
1776 - return err;
1777 -
1778 - if (!en) {
1779 - /* Clear any pending interrupts after we have disabled them */
1780 - err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
1781 - if (err < 0)
1782 - return err;
1783 - }
1784 -
1785 - return 0;
1786 -}
1787 -
1788 -static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
1789 -{
1790 - int irq_status;
1791 -
1792 - irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
1793 - MDIO_AN_TX_VEND_INT_STATUS2);
1794 - if (irq_status < 0) {
1795 - phy_error(phydev);
1796 - return IRQ_NONE;
1797 - }
1798 -
1799 - if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
1800 - return IRQ_NONE;
1801 -
1802 - phy_trigger_machine(phydev);
1803 -
1804 - return IRQ_HANDLED;
1805 -}
1806 -
1807 -static int aqr_read_status(struct phy_device *phydev)
1808 -{
1809 - int val;
1810 -
1811 - if (phydev->autoneg == AUTONEG_ENABLE) {
1812 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
1813 - if (val < 0)
1814 - return val;
1815 -
1816 - linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1817 - phydev->lp_advertising,
1818 - val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
1819 - linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1820 - phydev->lp_advertising,
1821 - val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
1822 - }
1823 -
1824 - return genphy_c45_read_status(phydev);
1825 -}
1826 -
1827 -static int aqr107_read_rate(struct phy_device *phydev)
1828 -{
1829 - u32 config_reg;
1830 - int val;
1831 -
1832 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
1833 - if (val < 0)
1834 - return val;
1835 -
1836 - if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
1837 - phydev->duplex = DUPLEX_FULL;
1838 - else
1839 - phydev->duplex = DUPLEX_HALF;
1840 -
1841 - switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
1842 - case MDIO_AN_TX_VEND_STATUS1_10BASET:
1843 - phydev->speed = SPEED_10;
1844 - config_reg = VEND1_GLOBAL_CFG_10M;
1845 - break;
1846 - case MDIO_AN_TX_VEND_STATUS1_100BASETX:
1847 - phydev->speed = SPEED_100;
1848 - config_reg = VEND1_GLOBAL_CFG_100M;
1849 - break;
1850 - case MDIO_AN_TX_VEND_STATUS1_1000BASET:
1851 - phydev->speed = SPEED_1000;
1852 - config_reg = VEND1_GLOBAL_CFG_1G;
1853 - break;
1854 - case MDIO_AN_TX_VEND_STATUS1_2500BASET:
1855 - phydev->speed = SPEED_2500;
1856 - config_reg = VEND1_GLOBAL_CFG_2_5G;
1857 - break;
1858 - case MDIO_AN_TX_VEND_STATUS1_5000BASET:
1859 - phydev->speed = SPEED_5000;
1860 - config_reg = VEND1_GLOBAL_CFG_5G;
1861 - break;
1862 - case MDIO_AN_TX_VEND_STATUS1_10GBASET:
1863 - phydev->speed = SPEED_10000;
1864 - config_reg = VEND1_GLOBAL_CFG_10G;
1865 - break;
1866 - default:
1867 - phydev->speed = SPEED_UNKNOWN;
1868 - return 0;
1869 - }
1870 -
1871 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
1872 - if (val < 0)
1873 - return val;
1874 -
1875 - if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
1876 - VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
1877 - phydev->rate_matching = RATE_MATCH_PAUSE;
1878 - else
1879 - phydev->rate_matching = RATE_MATCH_NONE;
1880 -
1881 - return 0;
1882 -}
1883 -
1884 -static int aqr107_read_status(struct phy_device *phydev)
1885 -{
1886 - int val, ret;
1887 -
1888 - ret = aqr_read_status(phydev);
1889 - if (ret)
1890 - return ret;
1891 -
1892 - if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
1893 - return 0;
1894 -
1895 - val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
1896 - if (val < 0)
1897 - return val;
1898 -
1899 - switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
1900 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
1901 - phydev->interface = PHY_INTERFACE_MODE_10GKR;
1902 - break;
1903 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
1904 - phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
1905 - break;
1906 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
1907 - phydev->interface = PHY_INTERFACE_MODE_10GBASER;
1908 - break;
1909 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
1910 - phydev->interface = PHY_INTERFACE_MODE_USXGMII;
1911 - break;
1912 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
1913 - phydev->interface = PHY_INTERFACE_MODE_XAUI;
1914 - break;
1915 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
1916 - phydev->interface = PHY_INTERFACE_MODE_SGMII;
1917 - break;
1918 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
1919 - phydev->interface = PHY_INTERFACE_MODE_RXAUI;
1920 - break;
1921 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
1922 - phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1923 - break;
1924 - default:
1925 - phydev->interface = PHY_INTERFACE_MODE_NA;
1926 - break;
1927 - }
1928 -
1929 - /* Read possibly downshifted rate from vendor register */
1930 - return aqr107_read_rate(phydev);
1931 -}
1932 -
1933 -static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
1934 -{
1935 - int val, cnt, enable;
1936 -
1937 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
1938 - if (val < 0)
1939 - return val;
1940 -
1941 - enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
1942 - cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
1943 -
1944 - *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
1945 -
1946 - return 0;
1947 -}
1948 -
1949 -static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
1950 -{
1951 - int val = 0;
1952 -
1953 - if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
1954 - return -E2BIG;
1955 -
1956 - if (cnt != DOWNSHIFT_DEV_DISABLE) {
1957 - val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
1958 - val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
1959 - }
1960 -
1961 - return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
1962 - MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
1963 - MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
1964 -}
1965 -
1966 -static int aqr107_get_tunable(struct phy_device *phydev,
1967 - struct ethtool_tunable *tuna, void *data)
1968 -{
1969 - switch (tuna->id) {
1970 - case ETHTOOL_PHY_DOWNSHIFT:
1971 - return aqr107_get_downshift(phydev, data);
1972 - default:
1973 - return -EOPNOTSUPP;
1974 - }
1975 -}
1976 -
1977 -static int aqr107_set_tunable(struct phy_device *phydev,
1978 - struct ethtool_tunable *tuna, const void *data)
1979 -{
1980 - switch (tuna->id) {
1981 - case ETHTOOL_PHY_DOWNSHIFT:
1982 - return aqr107_set_downshift(phydev, *(const u8 *)data);
1983 - default:
1984 - return -EOPNOTSUPP;
1985 - }
1986 -}
1987 -
1988 -/* If we configure settings whilst firmware is still initializing the chip,
1989 - * then these settings may be overwritten. Therefore make sure chip
1990 - * initialization has completed. Use presence of the firmware ID as
1991 - * indicator for initialization having completed.
1992 - * The chip also provides a "reset completed" bit, but it's cleared after
1993 - * read. Therefore function would time out if called again.
1994 - */
1995 -static int aqr107_wait_reset_complete(struct phy_device *phydev)
1996 -{
1997 - int val;
1998 -
1999 - return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2000 - VEND1_GLOBAL_FW_ID, val, val != 0,
2001 - 20000, 2000000, false);
2002 -}
2003 -
2004 -static void aqr107_chip_info(struct phy_device *phydev)
2005 -{
2006 - u8 fw_major, fw_minor, build_id, prov_id;
2007 - int val;
2008 -
2009 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
2010 - if (val < 0)
2011 - return;
2012 -
2013 - fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
2014 - fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
2015 -
2016 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
2017 - if (val < 0)
2018 - return;
2019 -
2020 - build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
2021 - prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
2022 -
2023 - phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
2024 - fw_major, fw_minor, build_id, prov_id);
2025 -}
2026 -
2027 -static int aqr107_config_init(struct phy_device *phydev)
2028 -{
2029 - int ret;
2030 -
2031 - /* Check that the PHY interface type is compatible */
2032 - if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
2033 - phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
2034 - phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
2035 - phydev->interface != PHY_INTERFACE_MODE_XGMII &&
2036 - phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
2037 - phydev->interface != PHY_INTERFACE_MODE_10GKR &&
2038 - phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
2039 - phydev->interface != PHY_INTERFACE_MODE_XAUI &&
2040 - phydev->interface != PHY_INTERFACE_MODE_RXAUI)
2041 - return -ENODEV;
2042 -
2043 - WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
2044 - "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
2045 -
2046 - ret = aqr107_wait_reset_complete(phydev);
2047 - if (!ret)
2048 - aqr107_chip_info(phydev);
2049 -
2050 - return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
2051 -}
2052 -
2053 -static int aqcs109_config_init(struct phy_device *phydev)
2054 -{
2055 - int ret;
2056 -
2057 - /* Check that the PHY interface type is compatible */
2058 - if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
2059 - phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
2060 - return -ENODEV;
2061 -
2062 - ret = aqr107_wait_reset_complete(phydev);
2063 - if (!ret)
2064 - aqr107_chip_info(phydev);
2065 -
2066 - /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
2067 - * PMA speed ability bits are the same for all members of the family,
2068 - * AQCS109 however supports speeds up to 2.5G only.
2069 - */
2070 - ret = phy_set_max_speed(phydev, SPEED_2500);
2071 - if (ret)
2072 - return ret;
2073 -
2074 - return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
2075 -}
2076 -
2077 -static void aqr107_link_change_notify(struct phy_device *phydev)
2078 -{
2079 - u8 fw_major, fw_minor;
2080 - bool downshift, short_reach, afr;
2081 - int mode, val;
2082 -
2083 - if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
2084 - return;
2085 -
2086 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
2087 - /* call failed or link partner is no Aquantia PHY */
2088 - if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
2089 - return;
2090 -
2091 - short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
2092 - downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
2093 -
2094 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
2095 - if (val < 0)
2096 - return;
2097 -
2098 - fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
2099 - fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
2100 -
2101 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
2102 - if (val < 0)
2103 - return;
2104 -
2105 - afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
2106 -
2107 - phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
2108 - fw_major, fw_minor,
2109 - short_reach ? ", short reach mode" : "",
2110 - downshift ? ", fast-retrain downshift advertised" : "",
2111 - afr ? ", fast reframe advertised" : "");
2112 -
2113 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
2114 - if (val < 0)
2115 - return;
2116 -
2117 - mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
2118 - if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
2119 - phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
2120 -}
2121 -
2122 -static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
2123 -{
2124 - int val, err;
2125 -
2126 - /* The datasheet notes to wait at least 1ms after issuing a
2127 - * processor intensive operation before checking.
2128 - * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
2129 - * because that just determines the maximum time slept, not the minimum.
2130 - */
2131 - usleep_range(1000, 5000);
2132 -
2133 - err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2134 - VEND1_GLOBAL_GEN_STAT2, val,
2135 - !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
2136 - AQR107_OP_IN_PROG_SLEEP,
2137 - AQR107_OP_IN_PROG_TIMEOUT, false);
2138 - if (err) {
2139 - phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
2140 - return err;
2141 - }
2142 -
2143 - return 0;
2144 -}
2145 -
2146 -static int aqr107_get_rate_matching(struct phy_device *phydev,
2147 - phy_interface_t iface)
2148 -{
2149 - if (iface == PHY_INTERFACE_MODE_10GBASER ||
2150 - iface == PHY_INTERFACE_MODE_2500BASEX ||
2151 - iface == PHY_INTERFACE_MODE_NA)
2152 - return RATE_MATCH_PAUSE;
2153 - return RATE_MATCH_NONE;
2154 -}
2155 -
2156 -static int aqr107_suspend(struct phy_device *phydev)
2157 -{
2158 - int err;
2159 -
2160 - err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
2161 - MDIO_CTRL1_LPOWER);
2162 - if (err)
2163 - return err;
2164 -
2165 - return aqr107_wait_processor_intensive_op(phydev);
2166 -}
2167 -
2168 -static int aqr107_resume(struct phy_device *phydev)
2169 -{
2170 - int err;
2171 -
2172 - err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
2173 - MDIO_CTRL1_LPOWER);
2174 - if (err)
2175 - return err;
2176 -
2177 - return aqr107_wait_processor_intensive_op(phydev);
2178 -}
2179 -
2180 -static int aqr107_probe(struct phy_device *phydev)
2181 -{
2182 - phydev->priv = devm_kzalloc(&phydev->mdio.dev,
2183 - sizeof(struct aqr107_priv), GFP_KERNEL);
2184 - if (!phydev->priv)
2185 - return -ENOMEM;
2186 -
2187 - return aqr_hwmon_probe(phydev);
2188 -}
2189 -
2190 -static struct phy_driver aqr_driver[] = {
2191 -{
2192 - PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
2193 - .name = "Aquantia AQ1202",
2194 - .config_aneg = aqr_config_aneg,
2195 - .config_intr = aqr_config_intr,
2196 - .handle_interrupt = aqr_handle_interrupt,
2197 - .read_status = aqr_read_status,
2198 -},
2199 -{
2200 - PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
2201 - .name = "Aquantia AQ2104",
2202 - .config_aneg = aqr_config_aneg,
2203 - .config_intr = aqr_config_intr,
2204 - .handle_interrupt = aqr_handle_interrupt,
2205 - .read_status = aqr_read_status,
2206 -},
2207 -{
2208 - PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
2209 - .name = "Aquantia AQR105",
2210 - .config_aneg = aqr_config_aneg,
2211 - .config_intr = aqr_config_intr,
2212 - .handle_interrupt = aqr_handle_interrupt,
2213 - .read_status = aqr_read_status,
2214 - .suspend = aqr107_suspend,
2215 - .resume = aqr107_resume,
2216 -},
2217 -{
2218 - PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
2219 - .name = "Aquantia AQR106",
2220 - .config_aneg = aqr_config_aneg,
2221 - .config_intr = aqr_config_intr,
2222 - .handle_interrupt = aqr_handle_interrupt,
2223 - .read_status = aqr_read_status,
2224 -},
2225 -{
2226 - PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
2227 - .name = "Aquantia AQR107",
2228 - .probe = aqr107_probe,
2229 - .get_rate_matching = aqr107_get_rate_matching,
2230 - .config_init = aqr107_config_init,
2231 - .config_aneg = aqr_config_aneg,
2232 - .config_intr = aqr_config_intr,
2233 - .handle_interrupt = aqr_handle_interrupt,
2234 - .read_status = aqr107_read_status,
2235 - .get_tunable = aqr107_get_tunable,
2236 - .set_tunable = aqr107_set_tunable,
2237 - .suspend = aqr107_suspend,
2238 - .resume = aqr107_resume,
2239 - .get_sset_count = aqr107_get_sset_count,
2240 - .get_strings = aqr107_get_strings,
2241 - .get_stats = aqr107_get_stats,
2242 - .link_change_notify = aqr107_link_change_notify,
2243 -},
2244 -{
2245 - PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
2246 - .name = "Aquantia AQCS109",
2247 - .probe = aqr107_probe,
2248 - .get_rate_matching = aqr107_get_rate_matching,
2249 - .config_init = aqcs109_config_init,
2250 - .config_aneg = aqr_config_aneg,
2251 - .config_intr = aqr_config_intr,
2252 - .handle_interrupt = aqr_handle_interrupt,
2253 - .read_status = aqr107_read_status,
2254 - .get_tunable = aqr107_get_tunable,
2255 - .set_tunable = aqr107_set_tunable,
2256 - .suspend = aqr107_suspend,
2257 - .resume = aqr107_resume,
2258 - .get_sset_count = aqr107_get_sset_count,
2259 - .get_strings = aqr107_get_strings,
2260 - .get_stats = aqr107_get_stats,
2261 - .link_change_notify = aqr107_link_change_notify,
2262 -},
2263 -{
2264 - PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
2265 - .name = "Aquantia AQR405",
2266 - .config_aneg = aqr_config_aneg,
2267 - .config_intr = aqr_config_intr,
2268 - .handle_interrupt = aqr_handle_interrupt,
2269 - .read_status = aqr_read_status,
2270 -},
2271 -{
2272 - PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
2273 - .name = "Aquantia AQR113C",
2274 - .probe = aqr107_probe,
2275 - .get_rate_matching = aqr107_get_rate_matching,
2276 - .config_init = aqr107_config_init,
2277 - .config_aneg = aqr_config_aneg,
2278 - .config_intr = aqr_config_intr,
2279 - .handle_interrupt = aqr_handle_interrupt,
2280 - .read_status = aqr107_read_status,
2281 - .get_tunable = aqr107_get_tunable,
2282 - .set_tunable = aqr107_set_tunable,
2283 - .suspend = aqr107_suspend,
2284 - .resume = aqr107_resume,
2285 - .get_sset_count = aqr107_get_sset_count,
2286 - .get_strings = aqr107_get_strings,
2287 - .get_stats = aqr107_get_stats,
2288 - .link_change_notify = aqr107_link_change_notify,
2289 -},
2290 -};
2291 -
2292 -module_phy_driver(aqr_driver);
2293 -
2294 -static struct mdio_device_id __maybe_unused aqr_tbl[] = {
2295 - { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
2296 - { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
2297 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
2298 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
2299 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
2300 - { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
2301 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
2302 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
2303 - { }
2304 -};
2305 -
2306 -MODULE_DEVICE_TABLE(mdio, aqr_tbl);
2307 -
2308 -MODULE_DESCRIPTION("Aquantia PHY driver");
2309 -MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
2310 -MODULE_LICENSE("GPL v2");
OpenWrt Source Repository