target/linux/generic/backport-5.15/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch

   1 From: Lorenzo Bianconi <lorenzo@kernel.org>
   2 Date: Sat, 14 Jan 2023 18:01:30 +0100
   3 Subject: [PATCH] net: ethernet: mtk_eth_soc: align reset procedure to vendor
   4  sdk
   5
   6 Avoid to power-down the ethernet chip during hw reset and align reset
   7 procedure to vendor sdk.
   8
   9 Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
  10 Tested-by: Daniel Golle <daniel@makrotopia.org>
  11 Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
  12 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
  13 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  14 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  15 ---
  16
  17 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  18 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  19 @@ -2789,14 +2789,29 @@ static void mtk_dma_free(struct mtk_eth
  20         kfree(eth->scratch_head);
  21  }
  22
  23 +static bool mtk_hw_reset_check(struct mtk_eth *eth)
  24 +{
  25 +       u32 val = mtk_r32(eth, MTK_INT_STATUS2);
  26 +
  27 +       return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) ||
  28 +              (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) ||
  29 +              (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL);
  30 +}
  31 +
  32  static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
  33  {
  34         struct mtk_mac *mac = netdev_priv(dev);
  35         struct mtk_eth *eth = mac->hw;
  36
  37 +       if (test_bit(MTK_RESETTING, &eth->state))
  38 +               return;
  39 +
  40 +       if (!mtk_hw_reset_check(eth))
  41 +               return;
  42 +
  43         eth->netdev[mac->id]->stats.tx_errors++;
  44 -       netif_err(eth, tx_err, dev,
  45 -                 "transmit timed out\n");
  46 +       netif_err(eth, tx_err, dev, "transmit timed out\n");
  47 +
  48         schedule_work(&eth->pending_work);
  49  }
  50
  51 @@ -3278,15 +3293,17 @@ static int mtk_hw_init(struct mtk_eth *e
  52         const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  53         int i, val, ret;
  54
  55 -       if (test_and_set_bit(MTK_HW_INIT, &eth->state))
  56 +       if (!reset && test_and_set_bit(MTK_HW_INIT, &eth->state))
  57                 return 0;
  58
  59 -       pm_runtime_enable(eth->dev);
  60 -       pm_runtime_get_sync(eth->dev);
  61 +       if (!reset) {
  62 +               pm_runtime_enable(eth->dev);
  63 +               pm_runtime_get_sync(eth->dev);
  64
  65 -       ret = mtk_clk_enable(eth);
  66 -       if (ret)
  67 -               goto err_disable_pm;
  68 +               ret = mtk_clk_enable(eth);
  69 +               if (ret)
  70 +                       goto err_disable_pm;
  71 +       }
  72
  73         if (eth->ethsys)
  74                 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
  75 @@ -3412,8 +3429,10 @@ static int mtk_hw_init(struct mtk_eth *e
  76         return 0;
  77
  78  err_disable_pm:
  79 -       pm_runtime_put_sync(eth->dev);
  80 -       pm_runtime_disable(eth->dev);
  81 +       if (!reset) {
  82 +               pm_runtime_put_sync(eth->dev);
  83 +               pm_runtime_disable(eth->dev);
  84 +       }
  85
  86         return ret;
  87  }
  88 @@ -3475,30 +3494,53 @@ static int mtk_do_ioctl(struct net_devic
  89         return -EOPNOTSUPP;
  90  }
  91
  92 +static void mtk_prepare_for_reset(struct mtk_eth *eth)
  93 +{
  94 +       u32 val;
  95 +       int i;
  96 +
  97 +       /* disabe FE P3 and P4 */
  98 +       val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3;
  99 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
 100 +               val |= MTK_FE_LINK_DOWN_P4;
 101 +       mtk_w32(eth, val, MTK_FE_GLO_CFG);
 102 +
 103 +       /* adjust PPE configurations to prepare for reset */
 104 +       for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
 105 +               mtk_ppe_prepare_reset(eth->ppe[i]);
 106 +
 107 +       /* disable NETSYS interrupts */
 108 +       mtk_w32(eth, 0, MTK_FE_INT_ENABLE);
 109 +
 110 +       /* force link down GMAC */
 111 +       for (i = 0; i < 2; i++) {
 112 +               val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK;
 113 +               mtk_w32(eth, val, MTK_MAC_MCR(i));
 114 +       }
 115 +}
 116 +
 117  static void mtk_pending_work(struct work_struct *work)
 118  {
 119         struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
 120 -       int err, i;
 121         unsigned long restart = 0;
 122 +       u32 val;
 123 +       int i;
 124
 125         rtnl_lock();
 126 -
 127 -       dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
 128         set_bit(MTK_RESETTING, &eth->state);
 129
 130 +       mtk_prepare_for_reset(eth);
 131 +
 132         /* stop all devices to make sure that dma is properly shut down */
 133         for (i = 0; i < MTK_MAC_COUNT; i++) {
 134 -               if (!eth->netdev[i])
 135 +               if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
 136                         continue;
 137 +
 138                 mtk_stop(eth->netdev[i]);
 139                 __set_bit(i, &restart);
 140         }
 141 -       dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
 142
 143 -       /* restart underlying hardware such as power, clock, pin mux
 144 -        * and the connected phy
 145 -        */
 146 -       mtk_hw_deinit(eth);
 147 +       usleep_range(15000, 16000);
 148
 149         if (eth->dev->pins)
 150                 pinctrl_select_state(eth->dev->pins->p,
 151 @@ -3509,15 +3551,19 @@ static void mtk_pending_work(struct work
 152         for (i = 0; i < MTK_MAC_COUNT; i++) {
 153                 if (!test_bit(i, &restart))
 154                         continue;
 155 -               err = mtk_open(eth->netdev[i]);
 156 -               if (err) {
 157 +
 158 +               if (mtk_open(eth->netdev[i])) {
 159                         netif_alert(eth, ifup, eth->netdev[i],
 160 -                             "Driver up/down cycle failed, closing device.\n");
 161 +                                   "Driver up/down cycle failed\n");
 162                         dev_close(eth->netdev[i]);
 163                 }
 164         }
 165
 166 -       dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
 167 +       /* enabe FE P3 and P4 */
 168 +       val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3;
 169 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
 170 +               val &= ~MTK_FE_LINK_DOWN_P4;
 171 +       mtk_w32(eth, val, MTK_FE_GLO_CFG);
 172
 173         clear_bit(MTK_RESETTING, &eth->state);
 174
 175 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 176 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 177 @@ -72,12 +72,24 @@
 178  #define        MTK_HW_LRO_REPLACE_DELTA        1000
 179  #define        MTK_HW_LRO_SDL_REMAIN_ROOM      1522
 180
 181 +/* Frame Engine Global Configuration */
 182 +#define MTK_FE_GLO_CFG         0x00
 183 +#define MTK_FE_LINK_DOWN_P3    BIT(11)
 184 +#define MTK_FE_LINK_DOWN_P4    BIT(12)
 185 +
 186  /* Frame Engine Global Reset Register */
 187  #define MTK_RST_GL             0x04
 188  #define RST_GL_PSE             BIT(0)
 189
 190  /* Frame Engine Interrupt Status Register */
 191  #define MTK_INT_STATUS2                0x08
 192 +#define MTK_FE_INT_ENABLE      0x0c
 193 +#define MTK_FE_INT_FQ_EMPTY    BIT(8)
 194 +#define MTK_FE_INT_TSO_FAIL    BIT(12)
 195 +#define MTK_FE_INT_TSO_ILLEGAL BIT(13)
 196 +#define MTK_FE_INT_TSO_ALIGN   BIT(14)
 197 +#define MTK_FE_INT_RFIFO_OV    BIT(18)
 198 +#define MTK_FE_INT_RFIFO_UF    BIT(19)
 199  #define MTK_GDM1_AF            BIT(28)
 200  #define MTK_GDM2_AF            BIT(29)
 201
 202 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
 203 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
 204 @@ -716,6 +716,33 @@ int mtk_foe_entry_idle_time(struct mtk_p
 205         return __mtk_foe_entry_idle_time(ppe, entry->data.ib1);
 206  }
 207
 208 +int mtk_ppe_prepare_reset(struct mtk_ppe *ppe)
 209 +{
 210 +       if (!ppe)
 211 +               return -EINVAL;
 212 +
 213 +       /* disable KA */
 214 +       ppe_clear(ppe, MTK_PPE_TB_CFG, MTK_PPE_TB_CFG_KEEPALIVE);
 215 +       ppe_clear(ppe, MTK_PPE_BIND_LMT1, MTK_PPE_NTU_KEEPALIVE);
 216 +       ppe_w32(ppe, MTK_PPE_KEEPALIVE, 0);
 217 +       usleep_range(10000, 11000);
 218 +
 219 +       /* set KA timer to maximum */
 220 +       ppe_set(ppe, MTK_PPE_BIND_LMT1, MTK_PPE_NTU_KEEPALIVE);
 221 +       ppe_w32(ppe, MTK_PPE_KEEPALIVE, 0xffffffff);
 222 +
 223 +       /* set KA tick select */
 224 +       ppe_set(ppe, MTK_PPE_TB_CFG, MTK_PPE_TB_TICK_SEL);
 225 +       ppe_set(ppe, MTK_PPE_TB_CFG, MTK_PPE_TB_CFG_KEEPALIVE);
 226 +       usleep_range(10000, 11000);
 227 +
 228 +       /* disable scan mode */
 229 +       ppe_clear(ppe, MTK_PPE_TB_CFG, MTK_PPE_TB_CFG_SCAN_MODE);
 230 +       usleep_range(10000, 11000);
 231 +
 232 +       return mtk_ppe_wait_busy(ppe);
 233 +}
 234 +
 235  struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
 236                              int version, int index)
 237  {
 238 --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
 239 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
 240 @@ -307,6 +307,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
 241  void mtk_ppe_deinit(struct mtk_eth *eth);
 242  void mtk_ppe_start(struct mtk_ppe *ppe);
 243  int mtk_ppe_stop(struct mtk_ppe *ppe);
 244 +int mtk_ppe_prepare_reset(struct mtk_ppe *ppe);
 245
 246  void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash);
 247
 248 --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
 249 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
 250 @@ -58,6 +58,12 @@
 251  #define MTK_PPE_TB_CFG_SCAN_MODE               GENMASK(17, 16)
 252  #define MTK_PPE_TB_CFG_HASH_DEBUG              GENMASK(19, 18)
 253  #define MTK_PPE_TB_CFG_INFO_SEL                        BIT(20)
 254 +#define MTK_PPE_TB_TICK_SEL                    BIT(24)
 255 +
 256 +#define MTK_PPE_BIND_LMT1                      0x230
 257 +#define MTK_PPE_NTU_KEEPALIVE                  GENMASK(23, 16)
 258 +
 259 +#define MTK_PPE_KEEPALIVE                      0x234
 260
 261  enum {
 262         MTK_PPE_SCAN_MODE_DISABLED,