target/linux/gemini/patches-4.14/0001-cache-patch-from-OpenWRT.patch

   1 From 57615e112aba6ae4c831d50e769c2c102f013686 Mon Sep 17 00:00:00 2001
   2 From: Linus Walleij <linus.walleij@linaro.org>
   3 Date: Tue, 7 Jun 2016 22:53:24 +0200
   4 Subject: [PATCH 01/31] cache patch from OpenWRT
   5
   6 ---
   7  arch/arm/mm/cache-fa.S | 17 ++++++++++++++++-
   8  1 file changed, 16 insertions(+), 1 deletion(-)
   9
  10 --- a/arch/arm/mm/cache-fa.S
  11 +++ b/arch/arm/mm/cache-fa.S
  12 @@ -24,7 +24,8 @@
  13  /*
  14   * The size of one data cache line.
  15   */
  16 -#define CACHE_DLINESIZE        16
  17 +#define CACHE_DLINESIZE                16
  18 +#define CACHE_DLINESHIFT       4
  19
  20  /*
  21   * The total size of the data cache.
  22 @@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area)
  23   *     - start  - virtual start address
  24   *     - end    - virtual end address
  25   */
  26 +__flush_whole_dcache:
  27 +       mcr     p15, 0, r0, c7, c14, 0          @ clean/invalidate D cache
  28 +       mov     r0, #0
  29 +       mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
  30 +       mov     pc, lr
  31 +
  32  fa_dma_inv_range:
  33 +       sub     r3, r1, r0                      @ calculate total size
  34 +       cmp     r3, #CACHE_DLIMIT               @ total size >= limit?
  35 +       bhs     __flush_whole_dcache            @ flush whole D cache
  36 +
  37         tst     r0, #CACHE_DLINESIZE - 1
  38         bic     r0, r0, #CACHE_DLINESIZE - 1
  39         mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D entry
  40 @@ -193,6 +204,10 @@ fa_dma_inv_range:
  41   *     - end    - virtual end address
  42   */
  43  fa_dma_clean_range:
  44 +       sub     r3, r1, r0                      @ calculate total size
  45 +       cmp     r3, #CACHE_DLIMIT               @ total size >= limit?
  46 +       bhs     __flush_whole_dcache            @ flush whole D cache
  47 +
  48         bic     r0, r0, #CACHE_DLINESIZE - 1
  49  1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  50         add     r0, r0, #CACHE_DLINESIZE